Hardware acceleration apparatus, method and system, and storage medium

Abstract

Disclosed in the present invention are a hardware acceleration apparatus, method and system, and a storage medium, specifically, an FFT and IFFT hardware acceleration apparatus, method and system, and a storage medium for any recursive call of ultra-low latency. The apparatus comprises one or more of an initial module, a read pointer loop module, a first mirror image address conversion module, an FFT module, a second mirror image address conversion module, and an IFFT module. An FFT recursive body module in the FFT module performs a butterfly nesting operation having variable iterations, so as to convert data of a time domain signal to be processed into a frequency domain signal of which the period is continuously updated. An IFFT recursive body module in the IFFT module performs a butterfly nesting operation having variable iterations, so as to restore data of a frequency domain signal to be processed to an original time domain signal. The FFT module and the IFFT module of the present invention can be described by the same code, and any points which are multiples of 2 can be randomly customized by modifying parameters and changing the number of instantiated nested levels, thereby improving the reusability and flexibility of operators, and reducing the economic and time costs of version maintenance and management.

Description

Hardware acceleration device, method, system and storage medium TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to a hardware acceleration device, method, system and storage medium, and more particularly to a hardware acceleration device, method, system and storage medium for ultra-low latency arbitrary recursive call FFT and IFFT. BACKGROUND

[0002] Fast Fourier transform (FFT) is a high-efficiency and fast computing method for computing discrete Fourier transform (DFT) using a computer. It was proposed by J.W. Cooley and T.W. Tukey in 1965. Using this algorithm can greatly reduce the number of multiplications required by the computer to compute the discrete Fourier transform, especially when the number of sampling points N is large, the savings in computation of the FFT algorithm are more significant.

[0003] FFT has a wide range of applications in many fields, including but not limited to signal processing, communication, computer science, audio processing, image processing, machine learning, data encryption and security, etc. Although FFT hardware acceleration has significant advantages in many applications, there are still some drawbacks, including:

[0004] 1. High cost: FFT hardware acceleration usually requires specially designed and manufactured hardware circuits, resulting in high cost. This may not be practical for individual users or small-scale applications.

[0005] 2. Limited flexibility: Once the FFT hardware accelerator is designed and manufactured, its functions and performance are usually fixed and difficult to modify or upgrade flexibly. This may not be suitable for applications that require frequent changes in demand.

[0006] 3. Physical space occupation: FFT hardware accelerators usually require a large physical space. For space-limited devices or systems, such as embedded systems or mobile devices, it may be difficult to integrate such hardware accelerators.

[0007] 4. Dependence on specific hardware platforms: FFT hardware accelerators are usually designed for specific hardware platforms, and compatibility between different platforms may be a problem. This makes it more difficult to port or develop cross-platform on different platforms.

[0008] Therefore, FFT hardware accelerators have obvious advantages in some specific scenarios, but also have some limitations and drawbacks. When deciding whether to use FFT hardware acceleration, factors such as application requirements, cost, flexibility and platform compatibility need to be considered. SUMMARY

[0009] In view of the deficiencies of the prior art, the purpose of the present application is to provide a hardware acceleration device, method, system and storage medium, which can change parameter configurations according to the power consumption limit and performance requirement of computing resources, flexibly adjust the computing complexity and resource utilization, realize the balance between precision, power consumption and computing power, and push the operation delay to the extreme.

[0010] The first aspect of the present disclosure provides a hardware acceleration device, which comprises one or more of the following modules:

[0011] An initial module configured to cache an original time-domain signal;

[0012] A read pointer cycle module configured to generate a periodically and continuously replaced initial signal based on the original time-domain signal;

[0013] A first mirror address translation module configured to convert the periodically and continuously replaced initial signal into a pointer timing adapted to an FFT module, so as to continuously provide the FFT module with data of a time-domain signal to be processed;

[0014] An FFT module comprising an FFT recursive body module, which is configured to receive data of the time-domain signal to be processed in an optimal timing, and convert the data of the time-domain signal to be processed into a periodically and continuously replaced frequency-domain signal through the FFT recursive body module, the FFT recursive body module being configured to perform a butterfly doll operation with an arbitrary number of cycles;

[0015] A second mirror address translation module configured to receive the periodically and continuously replaced frequency-domain signal, and convert the periodically and continuously replaced frequency-domain signal into a pointer timing adapted to an IFFT module, so as to continuously provide the IFFT module with data of a frequency-domain signal to be processed; and

[0016] An IFFT module comprising an IFFT recursive body module, which is configured to receive data of the frequency-domain signal to be processed in an optimal timing, and restore the data of the frequency-domain signal to be processed into the original time-domain signal through the IFFT recursive body module, the IFFT recursive body module being configured to perform a butterfly doll operation with an arbitrary number of cycles.

[0017] Optionally, the FFT module realizes the FFT operation of 4 to positive infinity points by performing an arbitrary number of recursive calls on the FFT recursive body module, so as to convert the data of the time-domain signal to be processed into the periodically and continuously replaced frequency-domain signal.

[0018] The IFFT module realizes the FFT operation of 4 to positive infinite points by recursively calling the IFFT recursive body module, so as to restore the data of the frequency domain signal to be processed into the original time domain signal.

[0019] Optionally, the FFT recursive body module and the IFFT recursive body module each comprise a basic recursive unit module and N layers of recursive body modules, N being the maximum nesting number of recursive calls of the FFT recursive body module or the IFFT recursive body module,

[0020] The FFT recursive body module and the IFFT recursive body module each comprise a topmost recursive body module and a bottommost recursive body module, the topmost recursive body module being a recursive body module performing the Nth layer of recursive calls, and the bottommost recursive body module being the basic recursive unit module.

[0021] Optionally, the value of the maximum recursive call nesting number N is determined according to the following formula:

[0022]

[0023] Wherein, M is the operation point number of FFT or IFFT.

[0024] Optionally, each layer of recursive body modules comprises a butterfly pipeline gating timing sequence module which has the same sequence but whose execution time is twice that of the previous layer of recursive body modules.

[0025] Optionally, the butterfly pipeline gating timing sequence module comprises at least one invisible state machine module, the trigger condition and output pointer of the invisible state machine module being hidden by the multiple nature of the counter module.

[0026] Optionally, the invisible state machine module in each layer of recursive body modules comprises four states of 0, 1, 2 and 3 of the butterfly operation of the current layer, and the butterfly pipeline pointers in the four states are in the same direction, wherein 0 represents multiplying and accumulating the left front wing of the butterfly, 1 represents multiplying and accumulating the left rear wing of the butterfly, 2 represents multiplying and accumulating the right front wing of the butterfly, and 3 represents multiplying and accumulating the right rear wing of the butterfly.

[0027] Optionally, each layer of recursive body modules has four directions of butterfly pointers, wherein any one direction of butterfly pointers comprises two small pointers in the same direction of the previous layer of recursive body modules; each time the recursive body module performs a pointer operation, the two small pointers in the same direction of the previous layer of recursive body modules successively perform two pointer operations at a rate of twice.

[0028] ​Optionally, the state cycle of the current layer of recursive body module is twice that of the previous layer of recursive body module, and the data bit width of the current layer of recursive body module is twice that of the previous layer of recursive body module.

[0029] Optionally, the data bit width of each layer of recursive body module is W, and the data pipeline includes two data pipelines with a data bit width of W / 2.

[0030] The second aspect of the present disclosure provides a hardware acceleration method, which comprises one or more of the following steps:

[0031] Caching the original time domain signal;

[0032] Generating a periodically continuous replacement initial signal based on the original time domain signal;

[0033] Converting the periodically continuous replacement initial signal into a pointer timing suitable for FFT transformation to obtain data of the time domain signal to be processed;

[0034] Receiving the data of the time domain signal to be processed in an optimal timing, and converting the data of the time domain signal to be processed into a periodically continuous replacement frequency domain signal through an FFT recursive body module configured to perform a butterfly Russian doll operation with an arbitrary number of loops;

[0035] Converting the periodically continuous replacement frequency domain signal into a pointer timing suitable for IFFT transformation to obtain data of the frequency domain signal to be processed;

[0036] Receiving the data of the frequency domain signal to be processed in an optimal timing, and restoring the data of the frequency domain signal to be processed into the original time domain signal through an IFFT recursive body module configured to perform a butterfly Russian doll operation with an arbitrary number of loops.

[0037] Optionally, the FFT operation with 4 to positive infinite points is realized by recursively calling the FFT recursive body module an arbitrary number of times to convert the data of the time domain signal to be processed into a periodically continuous replacement frequency domain signal;

[0038] The IFFT operation with 4 to positive infinite points is realized by recursively calling the IFFT recursive body module an arbitrary number of times to restore the data of the frequency domain signal to be processed into the original time domain signal.

[0039] Optionally, the FFT recursive body module and the IFFT recursive body module each comprise a basic recursive unit module and N layers of recursive body modules, N being the maximum number of nested layers of recursive calls performed by the FFT recursive body module or the IFFT recursive body module,

[0040] The FFT recursive body module and the IFFT recursive body module each include a topmost recursive body module and a bottommost recursive body module, the topmost recursive body module is a recursive body module for performing an Nth layer recursive call, and the bottommost recursive body module is the basic recursive unit module.

[0041] Optionally, the value of the maximum recursive call nesting layer number N is determined according to the following formula:

[0042]

[0043] wherein M is the operation point number of the FFT or the IFFT.

[0044] Optionally, each layer recursive body module includes a butterfly pipeline gating timing sequence that is the same in sequence but has an execution time twice that of a previous layer recursive body module.

[0045] Optionally, the butterfly pipeline gating timing sequence includes at least one invisible state machine, and the trigger condition and output pointer of the invisible state machine are hidden by the multiple characteristics of a counter.

[0046] Optionally, the invisible state machine module in each layer recursive body module includes four states of 0, 1, 2, and 3 of the current layer butterfly operation, and the butterfly pipeline pointers in the four states are consistently directed, wherein 0 represents multiplying and accumulating the left front wing of the butterfly, 1 represents multiplying and accumulating the left rear wing of the butterfly, 3 represents multiplying and accumulating the right front wing of the butterfly, and 4 represents multiplying and accumulating the right rear wing of the butterfly.

[0047] Optionally, each layer recursive body module has four direction butterfly pointers, and any one direction butterfly pointer includes two small pointers of the same direction in a previous layer recursive body module; each time the recursive body module performs a pointer operation, the two small pointers of the same direction in the previous layer recursive body module successively perform two pointer operations at a rate of twice.

[0048] Optionally, the state period of the current layer recursive body module is twice that of the previous layer recursive body module, and the data bit width of the current layer recursive body module is twice that of the previous layer recursive body module.

[0049] Optionally, the data bit width of each layer recursive body module includes two data pipes with a data bit width of W / 2 in a data pipe with a data bit width of W.

[0050] A third aspect of the present disclosure provides a hardware acceleration system, the hardware acceleration system including the hardware acceleration device of the first aspect.

[0051] ​The fourth aspect of the present disclosure provides a non-transitory computer readable storage medium, which stores computer instructions suitable for a processor to load to implement the hardware acceleration method of the first aspect.

[0052] The above scheme is implemented, and has the following beneficial effects:

[0053] In the present disclosure, the architecture of the FFT module and the architecture of the IFFT module are very similar, and the two architectures can be described by the same code. By modifying the define macro definition value to determine whether to play the role of FFT or the role of IFFT when instantiated, the difficulty of code maintenance and management is reduced.

[0054] The FFT recursive body module is configured to perform a butterfly doll operation that can be looped any number of times. The IFFT recursive body module is configured to perform a butterfly doll operation that can be looped any number of times. By modifying the parameters, the number of nested layers can be arbitrarily customized to any multiple of 2. The reusability and flexibility of the operator are improved, and the economic and time cost of version maintenance and management is reduced.

[0055] The hidden state machine module is used to implement the same timing for each recursive layer, but the execution cycle is 2 n The data flow state guide is increased by 2, so that the recursive calls between different levels do not produce any operation gaps, and data packet loss is also avoided. In limited resources, the operation delay is pushed to the extreme. Moreover, the "jump condition" of the hidden state machine module and the "task execution identification signal" of the current state are completely "hidden", thereby reducing the area and power consumption of the circuit.

[0056] Additional aspects and advantages of the present application will be partially given in the following description, partially will become obvious from the following description, or will be understood by the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0057] The disclosure of the present application will become more readily apparent from the following description. Those skilled in the art will readily appreciate that the drawings are only for purposes of illustration and are not intended to limit the scope of the present application. In addition, like reference numerals are used to designate like parts throughout the several views in which:

[0058] Fig. 1 is a structural block diagram of the hardware acceleration device of the present disclosure;

[0059] Fig. 2 is a schematic diagram of a butterfly doll;

[0060] Fig. 3 is a schematic diagram of the regions corresponding to the four states of the butterfly operation;

[0061] Figure 4 is a diagram of mirror addressing for 8-point FFT;

[0062] Figure 5 is a diagram of implementing 128-point FFT operation by 6 recursive calls in RTL code;

[0063] Figure 6 is a timing diagram of single stream data feeding into 16-point FFT (IFFT) operator;

[0064] Figure 7 is a timing diagram of two stream data feeding into 16-point FFT (IFFT) operator simultaneously;

[0065] Figure 8 is a timing diagram of two stream data feeding into 16-point FFT (IFFT) operator simultaneously;

[0066] Figure 9 is a timing diagram of two stream data feeding into 16-point FFT (IFFT) operator simultaneously;

[0067] Figure 10 is a flow diagram of the hardware acceleration method of the present disclosure.

[0068] In the drawings:

[0069] 110 initial module, 120 read pointer loop module, 130 first mirror address conversion module, 140 FFT module, 150 second mirror address conversion module, 160 IFFT module,

[0070] 0 left front wing, 1 left rear wing, 2 right front wing, 3 right rear wing. DETAILED DESCRIPTION

[0071] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions of the present application will be described below in conjunction with specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0072] Embodiments of the present application will be described in detail below, examples of which are shown in the drawings, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0073] The embodiment of the application provides a hardware acceleration device, in particular, an FFT and IFFT hardware acceleration device for ultra-low latency arbitrary recursive call, please refer to figure 1, the hardware acceleration device comprises one or more of the following modules: initial module 110, read pointer cycle module 120, first mirror address conversion module 130, FFT module 140, second mirror address conversion module 150 and IFFT module 160.Initial module 110 is configured to cache the original time domain signal.Read pointer cycle module 120 is configured to generate the initial signal of periodical continuous alternation based on the original time domain signal.The first mirror address conversion module 130 is configured to convert the initial signal of periodical continuous alternation into the pointer timing suitable for the FFT module, so as to continuously provide the data of the time domain signal to be processed for the FFT module 140.The FFT module 140 comprises an FFT recursive body module, and the FFT module 140 is configured to receive the data of the time domain signal to be processed in the optimal timing, and convert the data of the time domain signal to be processed into the frequency domain signal of periodical continuous alternation through the FFT recursive body module, and the FFT recursive body module is configured to perform the butterfly nested operation which can be cyclically called for any times.The "butterfly nested operation" can be understood as that there is a nested progressive relationship between the levels of the butterfly operation.The second mirror address conversion module 150 is configured to receive the frequency domain signal of periodical continuous alternation, and convert the frequency domain signal of periodical continuous alternation into the pointer timing suitable for the IFFT module 160, so as to continuously provide the data of the frequency domain signal to be processed for the IFFT module 160.The IFFT module 160 comprises an IFFT recursive body module, and the IFFT module 160 is configured to receive the data of the frequency domain signal to be processed in the optimal timing, and restore the data of the frequency domain signal to be processed into the original time domain signal through the IFFT recursive body module, and the IFFT recursive body module is configured to perform the recursive call nested operation which can be cyclically called for any times.

[0074] In the scheme, the operation points of the FFT and the IFFT are equal, and both are M.The optimal timing is the M / 2th operation period.The FFT module 140 receives the data of the time domain signal to be processed in the optimal timing, that is, when the operation reaches the M / 2th operation period, the FFT module starts to receive the new data of the time domain signal to be processed, so that the delay of the FFT transformation operation is greatly reduced.The IFFT module 160 receives the data of the frequency domain signal to be processed in the optimal timing, that is, when the operation reaches the M / 2th operation period, the IFFT module starts to receive the new data of the frequency domain signal to be processed, so that the delay of the IFFT transformation operation is greatly reduced,

[0075] Specifically, the FFT module 140 realizes the FFT operation of 4 to positive infinite points by recursively calling the FFT recursive body module for any times, so as to convert the data of the time domain signal to be processed into the frequency domain signal with periodically continuous alternation. The IFFT module 160 realizes the IFFT operation of 4 to positive infinite points by recursively calling the IFFT recursive body module for any times, so as to restore the data of the frequency domain signal to be processed into the original time domain signal.

[0076] The FFT recursive body module and the IFFT recursive body module have the same design structure, and each includes a basic recursive unit module and N layers of recursive body modules, where N is the maximum nesting number of recursive calls of the FFT recursive body module. The maximum nesting number of recursive calls of the IFFT recursive body module is equal to the maximum nesting number of recursive calls of the FFT recursive body module, and is also N. The value of the maximum nesting number of recursive calls N is determined according to the following formula:

[0077]

[0078] In the formula, M is the operation point number of the FFT or the IFFT.

[0079] The FFT recursive body module and the IFFT recursive body module each include a topmost recursive body module and a bottommost recursive body module. In the FFT recursive body module, the topmost recursive body module is the recursive body module that performs the Nth recursive call in the FFT, and the bottommost recursive body module is the basic recursive unit module in the FFT. In the IFFT recursive body module, the topmost recursive body module is the recursive body module that performs the Nth recursive call in the IFFT, and the bottommost recursive body module is the basic recursive unit module in the IFFT.

[0080] Further, the FFT recursive body module and the IFFT recursive body module also have the following common features:

[0081] 1. Each layer of recursive body modules includes a butterfly pipeline strobe timing module with the same sequence but the execution time being twice that of the previous layer of recursive body modules. The butterfly pipeline strobe timing module includes at least one invisible state machine module, and the trigger condition and the output pointer of the invisible state machine module are hidden by the multiple nature of the counter module.

[0082] ​2. The state machine module in each layer of the recursive body module includes four states of the current layer butterfly operation 0, 1, 2, 3, and the butterfly pipeline pointers in the four states are consistent in direction, wherein 0 represents multiply-accumulate on the left front wing of the butterfly, 1 represents multiply-accumulate on the left rear wing of the butterfly, 3 represents multiply-accumulate on the right front wing of the butterfly, and 4 represents multiply-accumulate on the right rear wing of the butterfly. FIG. 2 shows a schematic diagram of a "butterfly doll" that can be arbitrarily nested, in which the length and width of the "butterfly wing" of the current layer are both 2 times the length and width of the "butterfly wing" of the previous layer. FIG. 3 shows the calculation regions corresponding to the four states of the butterfly operation 0, 1, 2, 3. Each layer of the recursive body module (i.e., each layer of "butterfly wing") divides the four states of the butterfly operation into multiply-accumulate in different regions. They are respectively: 0 represents multiply-accumulate on the left front wing, 1 represents multiply-accumulate on the left rear wing, 2 represents multiply-accumulate on the right front wing, and 3 represents multiply-accumulate on the right rear wing.

[0083] 3. Each layer of the recursive body module has four directions of butterfly pointers, wherein any one direction of the butterfly pointers contains two small pointers of the same direction in the previous layer of the recursive body module; each time the recursive body module performs a pointer operation, the two small pointers of the same direction in the previous layer of the recursive body module successively perform two pointer operations at a rate of 2 times.

[0084] 4. The state period of the recursive body module of the current layer is 2 times the state period of the recursive body module of the previous layer, and the data bit width of the recursive body module of the current layer is 2 times the data bit width of the recursive body module of the previous layer. In the data pipeline with a data bit width of W of each layer of the recursive body module, two data pipelines with a data bit width of W / 2 are contained.

[0085] FIG. 1 describes the overall trend of the signal flow in the present scheme from a macroscopic point of view. The dotted line in the figure is the watershed of the time domain (Time Domain) and the frequency domain (Frequency Domain). The FFT module and the IFFT module are both core components of the design. Since the architecture of the FFT module and the architecture of the IFFT module are extremely similar, the two architectures can be described by the same code, and by modifying the `define macro definition value to determine whether to play the role of FFT or IFFT when instantiated, thereby reducing the difficulty of code maintenance and management.

[0086] Please continue to see Figure 1, in order to facilitate the analysis of the test, first of all, the original time domain signal is cached to the initial module, through the read pointer cycle module pointer cycle to produce a periodic continuous replacement of the initial signal (this is a sine wave signal), output to the left of the first mirror address conversion module, the periodic continuous replacement of the initial signal via the mirror pointer ptr_raddr_mirrormirror address conversion module in the first module is converted to adapt to the pointer timing of the FFT module, for the FFT module to provide a steady stream of time domain (time domain) signal data to be processed.

[0087] The operation point number of the FFT can be set to 2n, n is an integer greater than or equal to 2, for example, the operation point number of the FFT can be 4, 8, 16, 32, 64 or 128. Taking an 8-point FFT addressing as an example, the original order of the time domain signal address is: x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7]; the reordering before participating in the FFT operation is: x[0], x[4], x[2], x[6], x[1], x[5], x[3], x[7]; the above address ordering is converted to three-bit binary of [2:0] as shown in the following table:

[0088]

[0089] It can be seen from the data in the table that the 0th bit of the original order binary expression corresponds to the 2nd bit of the reordering binary expression; the 1st bit of the original order binary expression corresponds to the 1st bit of the reordering binary expression; the 2nd bit of the original order binary expression corresponds to the 0th bit of the reordering binary expression. That is, the binary of the original order and the reordering address presents a mirror relationship. The first mirror address conversion module changes the time domain signal data input in natural order into a code bit inversion arrangement order after index calculation, which can enter the FFT module to perform butterfly operation.

[0090] The FFT module takes in the above-mentioned time-domain signal data in an optimal timing, converts the time-domain signal data into frequency-domain signal data, and outputs the frequency-domain signal data to the right second mirror address conversion module. The periodically and continuously replaced frequency-domain signal is converted into a pointer timing suitable for the IFFT module by the mirror pointer ptr_raddr_mirr in the second mirror address conversion module, and the IFFT module is continuously provided with the frequency-domain signal data to be processed. Similar to the first mirror address conversion module, the second mirror address conversion module restores the reordered frequency-domain signal data into a natural order through index calculation, and then inputs the frequency-domain signal data into the IFFT module to perform a butterfly operation. The IFFT module takes in the above-mentioned frequency-domain signal data in an optimal timing, and restores the original time-domain signal.

[0091] The FFT module and the IFFT module are core modules of the design. The FFT recursive body module and the IFFT recursive body module each include a basic recursive element module and N layers of recursive body modules. N is the maximum number of nested layers of recursive calls of the FFT recursive body module. The maximum number of nested layers of recursive calls of the FFT recursive body module is equal to the maximum number of nested layers of recursive calls of the IFFT recursive body module, and the operation point number of the FFT module is also equal to the operation point number of the IFFT module. The FFT module realizes FFT operation of 4 to positive infinity points by performing recursive calls on the FFT recursive body module any number of times, so as to convert the time-domain signal data to be processed into a periodically and continuously replaced frequency-domain signal. The IFFT module realizes FFT operation of 4 to positive infinity points by performing recursive calls on the IFFT recursive body module any number of times, so as to restore the frequency-domain signal data to be processed into an original time-domain signal.

[0092] The design adopts a recursive call nesting mode that can be recycled any number of times to realize FFT or IFFT (default 128 points) operation of 4 to positive infinity. By modifying the parameter parameter, the nesting relationship between levels can be modified, so that based on the same set of RTL code, different scales and different operation precisions of the logic netlist can be cleverly realized. For example, as shown in FIG. 4: the default operation point number of the RTL code is parameter POINT_NUM == 128, and the recursive nesting number of the core code fft_stru_i is [log2(128)]-1. fft_stru_6 is the topmost layer, and fft_stru_0 (that is, fft_elmnt) is the bottommost layer. Each layer of logic has a butterfly pipeline gating timing sequence that is exactly twice the execution time of the next layer but has the same order. Therefore:

[0093] (1) fft_stru_0~6 can completely share the same set of RTL code fft_stru_i. That is, to implement 128-point FFT operation, only 6 recursive call instances of stru_i are needed to instantiate. Similarly, to implement 32-point FFT operation, only 4 recursive call instances of stru_i are needed to instantiate.

[0094] (2) Since the time of performing the same set of butterfly data channel gating operations between the levels just presents the 2^n characteristic, this means that the trigger condition and output pointer of the state machine for the butterfly channel timing can be hidden by the 2^n multiple characteristics in the counter cnt_seq, called the invisible state machine.

[0095] (3) For example: in STRU_5, that is, the operation of the 5th level, the current layer butterfly operation is performed once, and the current layer state current_state is just equal to cnt_seq[5:4]. Similarly, in STRU_3, that is, the operation of the 3rd level, the current layer butterfly operation is performed once, and the current layer state current_state is just equal to cnt_seq[3:2]. In this way, in STRU_i, that is, the operation of the i-th level, the current layer butterfly operation is performed once, and the current layer state current_state is just equal to cnt_seq[i:i-1].

[0096] No matter which layer the current layer is in, current_state contains 0, 1, 2, and 3 states. The butterfly channel pointer directions of the four states are completely consistent. And since the state period of the current layer is just 2 times the state period of its next layer, and the data bit width is just 2 times that of the previous layer. This means that in the current layer data pipe with a width of W, there are two data pipes with a width of W / 2 buried in it. No matter which layer it is in, there are 4 directions of butterfly pointers, and in any one direction of the butterfly pointers, there are two small pointers of the same direction in the next layer. Each time the current layer performs a pointer operation, the two small pointers of the same direction in the next layer it buries successively perform two pointer operations at twice the rate. In turn.

[0097] The recursive call of the FFT module or the IFFT module has the following characteristics: in the static call process, the upper limit of the number of logical calls is determined by the STRU_NUM of the top layer, and the upper limit of the number of physical calls is determined by the physical resources in the FPGA; whether the fft_stru_i module currently called is the bottom layer is determined by the generate if (STRU_NUM == 1) statement in the RTL code; if it is the bottom layer, the fft_elmnt module is called to perform basic multiplication and addition operations. In the dynamic call process, the same logical resource can be called any number of times in theory.

[0098] The following technical breakthroughs can be achieved through the above design:

[0099] 1) Arbitrary recursive call technology of operation architecture

[0100] Each recursive call increases the operation point number by one in an exponential form. This means that by modifying the parameter STRU_NUM, different operation point numbers of FFT or IFFT can be implemented in the same set of codes, and different scale logic netlists can be generated. For example, to implement 8192-point FFT or IFFT, only STRU_NUM = 17 is required. In this embodiment, the FFT operation is 128 points by default, so parameter STRU_NUM = log2(128)-1 == 6, that is, fft_stru_i is recursively called 6 times, as shown in FIG. 5. The above recursive call is further divided into the following two types: resource expansion recursive call before the RTL code is compiled and synthesized to form a logic netlist; and invariant resource recursive call before the RTL code is compiled and synthesized to form a logic netlist.

[0101] 2) "Time division multiplexing - seamless" technology

[0102] Each level only has one "physical multiplier-adder", which can split into n "virtual multiplier-adders" without affecting the operation performance (n is the operation point number of FFT transformation).

[0103] The FFT module starts to input new data when it operates to the M / 2th operation period, and the IFFT module starts to input new data when it operates to the M / 2th operation period, thereby greatly reducing the delay of FFT and IFFT transformation operation.

[0104] The "invisible state machine" based on cnt_seq counter is used to implement the same timing for each recursive layer, but the data stream state guidance is 2^n incremental. This means that the recursive call between different levels will not produce any operation gap, and will not produce data packet loss. The "jump condition" of the "invisible state machine" and the "task execution identification signal" of the current state are completely "invisible", thereby reducing the area and power consumption of the circuit.

[0105] Taking the 16-point FFT or IFFT as an example, first, the physical resources of 4 sets of multiplication and addition units (1 set per column) are called by time-sharing, and 32 sets of multiplication and addition units are virtually generated. When the first data stream is operated to the 8th, the first column multiplication and addition unit will be idle, but at this time, the second data stream seamlessly enters, although the operation number has changed, but still operates according to the path trajectory of the first set of data. Subsequently, the third, fourth and fifth data streams will come in large numbers and be seamlessly connected. For details, see the accompanying drawings 6-9.

[0106] Referring to FIG. 6, a single data stream enters the 16-point FFT (IFFT) operator, and the first data stream enters the fourth period. At this time, the fifth multiplication and addition unit of the first set of multiplication and addition units and the third multiplication and addition unit of the second set of multiplication and addition units are activated.

[0107] Referring to FIG. 7, two data streams simultaneously enter the 16-point FFT (IFFT) operator, and the first data stream enters the eighth period and the second data stream enters the zeroth period. When the first data stream is operated to the eighth period, the first set of multiplication and addition units will be idle, but at this time, the second data stream seamlessly enters. At this time, the first multiplication and addition unit of the first set of multiplication and addition units, the seventh multiplication and addition unit of the second set of multiplication and addition units, and the fourth multiplication and addition unit of the third set of multiplication and addition units are activated. The physical multiplication and addition units required are less than or equal to 4 sets.

[0108] Referring to FIG. 8, two data streams simultaneously enter the 16-point FFT (IFFT) operator, and the first data stream enters the thirteenth period and the second data stream enters the fifth period. At this time, the sixth multiplication and addition unit of the first set of multiplication and addition units, the fourth multiplication and addition unit of the second set of multiplication and addition units, the first multiplication and addition unit of the third set of multiplication and addition units, and the fourth multiplication and addition unit of the fourth set of multiplication and addition units are activated. The physical multiplication and addition units required are less than or equal to 4 sets.

[0109] Referring to FIG. 9, two data streams simultaneously enter the 16-point FFT (IFFT) operator, and the second data stream enters the tenth period. At this time, the output of the first FFT (IFFT) operator has been calculated. At this time, the sixth multiplication and addition unit of the third set of multiplication and addition units and the first multiplication and addition unit of the fourth set of multiplication and addition units are activated. The physical multiplication and addition units required are also less than or equal to 4 sets.

[0110] Therefore, the delay of completing one 16-point FFT (IFFT) is only 10 cycles.

[0111] The number of physical multiplication and addition units required to complete one N-point FFT (IFFT) is suites, where N is the number of points of FFT (IFFT) operation.

[0112] The number of cycles T of the delay Latency It can be determined by the following formula:

[0113]

[0114] Where N is the number of points of FFT (IFFT) operation.

[0115] When the number of butterfly operation points of the present disclosure is 4, 8, 16, 32, 64, 128, the corresponding butterfly operation delay is 1, 4, 9, 18, 35, 68 system clock cycles, which is better than most similar FFT hardware acceleration operators on the market.

[0116] In addition to the above device embodiments, the embodiments of the present application also provide a hardware acceleration method, which will be exemplarily described below.

[0117] FIG. 10 shows a flowchart of the hardware acceleration method, as shown in FIG. 10, the hardware acceleration method includes one or more of steps S601-S611.

[0118] S601, cache the original time domain signal.

[0119] S603, generate a periodically continuous replacement initial signal based on the original time domain signal.

[0120] S605, convert the periodically continuous replacement initial signal into a pointer timing suitable for FFT transformation, to obtain the data of the time domain signal to be processed.

[0121] S607, receive the data of the time domain signal to be processed in the optimal timing, and convert the data of the time domain signal to be processed into a periodically continuous replacement frequency domain signal through an FFT recursive body module, the FFT recursive body module is configured to perform a butterfly Russian nesting doll operation that can be looped any number of times.

[0122] The FFT recursive body module comprises a basic recursive unit module and N-layer recursive body modules, N being the maximum number of nested recursive calls of the FFT recursive body module, the recursive body module performing the Nth-layer recursive call being the topmost recursive body module, and the basic recursive unit module being the bottommost recursive body module. Through recursive calls of the FFT recursive body module, the FFT operation of 4 to positive infinity points is realized to convert the data of the time-domain signal to be processed into the periodically and continuously replaced frequency-domain signal.

[0123] In S609, the periodically and continuously replaced frequency-domain signal is converted into a pointer timing adapted to the IFFT transformation to obtain the data of the frequency-domain signal to be processed.

[0124] In S611, the data of the frequency-domain signal to be processed is received in the optimal timing, and the data of the frequency-domain signal to be processed is restored into the original time-domain signal through the IFFT recursive body module configured to perform the butterfly doll operation of any number of cycles.

[0125] The IFFT recursive body module comprises a basic recursive unit module and N-layer recursive body modules, N being the maximum number of nested recursive calls of the IFFT recursive body module, the recursive body module performing the Nth-layer recursive call being the topmost recursive body module, and the basic recursive unit module being the bottommost recursive body module. Through recursive calls of the IFFT recursive body module, the FFT operation of 4 to positive infinity points is realized to convert the data of the time-domain signal to be processed into the original time-domain signal.

[0126] The operation points of the IFFT are the same as those of the FFT, both being M. The value of the maximum number of recursive call nested layers N is determined according to the formula The optimal timing in S607 and S611 is the M / 2th operation period. When the operation reaches the M / 2th operation period, the FFT module starts to receive new time-domain signal data to be processed, and the IFFT module starts to receive new frequency-domain signal data to be processed, thereby greatly reducing the delay of the FFT and IFFT transformation operation.

[0127] In the FFT recursive body module and the IFFT recursive body module, each recursive body module comprises a butterfly pipeline gating timing sequence which is the same in sequence but has twice the execution time of the previous recursive body module. The butterfly pipeline gating timing sequence comprises at least one invisible state machine, the trigger condition and output pointer of the invisible state machine being counted by a counter The hidden state machine module in each recursive body module includes four states of the current layer butterfly operation 0, 1, 2 and 3, and the butterfly pipeline pointers in the four states are guided in the same direction, wherein 0 represents multiplying and accumulating the left front wing of the butterfly, 1 represents multiplying and accumulating the left rear wing of the butterfly, 3 represents multiplying and accumulating the right front wing of the butterfly, and 4 represents multiplying and accumulating the right rear wing of the butterfly.

[0128] Each recursive body module has four-direction butterfly pointers, and each of the four-direction butterfly pointers includes two small pointers in the same direction of the previous recursive body module; after the recursive body module performs a pointer operation, the two small pointers in the same direction of the previous recursive body module perform two pointer operations in turn at a rate of 2 times.

[0129] The state period of the current recursive body module is twice the state period of the previous recursive body module, and the data bit width of the current recursive body module is twice the data bit width of the previous recursive body module. In the data pipeline with a data bit width of W, two data pipelines with a data bit width of W / 2 are included.

[0130] In the embodiments of the present disclosure, the FFT recursive body module can perform a butterfly nesting operation with an arbitrary number of loops, and the FFT operation with an arbitrary point number can be realized by calling the FFT recursive body module. The IFFT recursive body module can perform a butterfly nesting operation with an arbitrary number of loops, and the FFT operation with an arbitrary point number can be realized by calling the IFFT recursive body module. The point number of any 2 times can be arbitrarily customized by modifying the parameters and changing the instantiation level of the nested layers. The reusability and flexibility of the operator are improved, and the economic and time cost of version maintenance and management is reduced.

[0131] The present disclosure uses the hidden state machine module to realize the same timing for each recursive layer, but the execution period is 2 n The data stream state guide is increased, so that the recursive calls between different levels do not produce any operation gap, and data packet loss is also avoided. In limited resources, the operation delay is pushed to the extreme. Moreover, the "jump condition" of the hidden state machine module and the "task execution identification signal" of the current state are completely "hidden", thereby reducing the area and power consumption of the circuit.

[0132] Correspondingly, the embodiment of the present application also provides a hardware acceleration system, which includes the hardware acceleration device described above.

[0133] Correspondingly, the embodiment of the present application also provides a non-transitory computer readable storage medium, which stores computer instructions, and the computer instructions are suitable for being loaded by a processor to implement the steps in the hardware acceleration method described above.

[0134] In embodiments of the present application, the memory is configured to store computer programs and can be configured to store other various data to support operations on the device where it is located. Among them, the processor can execute the computer program stored in the memory to realize the corresponding control logic. The memory can be realized by any type of volatile or non-volatile storage device or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0135] In embodiments of the present application, the processor can be any hardware processing device that can execute the above method logic. Alternatively, the processor can be a central processing unit (CPU), a graphics processing unit (GPU), or a microcontroller unit (MCU); it can also be a programmable device such as a field-programmable gate array (FPGA), a programmable array logic (PAL), a general array logic (GAL), a complex programmable logic device (CPLD), etc.; or an advanced reduced instruction set (RISC) processor (Advanced RISC Machines, ARM) or system on chip (System on Chip, SOC), etc., but not limited to this.

[0136] In embodiments of the present application, the communication component is configured to facilitate wired or wireless communication between the device where it is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G, 5G or their combination. In an exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component can also be implemented based on near field communication (NFC) technology, radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra wide band (UWB) technology, Bluetooth (BT) technology or other technologies.

[0137] In an embodiment of the present application, the display component can include a liquid crystal display (LCD) and a touch panel (TP). If the display component includes the touch panel, the display component can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide and a gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or a sliding action, but also detect duration and pressure related to the touching or sliding action.

[0138] In an embodiment of the present application, the power component is configured to supply power to various components of the device in which the power component is located. The power component can include a power management system, one or more power sources, and other components associated with generating, managing and distributing power to the device in which the power component is located.

[0139] In an embodiment of the present application, the audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC) that is configured to receive an external audio signal when the device in which the audio component is located is in an operational mode, such as a call mode, a recording mode and a voice recognition mode. The received audio signal can be further stored in a memory or transmitted via the communication component. In some embodiments, the audio component also includes a speaker to output audio signals. For example, for a device having a language interaction function, voice interaction with a user can be implemented through the audio component, etc.

[0140] It should be noted that the terms "first", "second" and the like in this text are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order or limit the types of "first" and "second".

[0141] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can be in the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0142] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in conjunction with the flowcharts.

[0143] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks or in conjunction with the flowcharts.

[0144] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in conjunction with the flowcharts.

[0145] In one typical configuration, the computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0146] The memory can include non-persistent memory and / or volatile memory, such as random access memory (RAM) and / or cache memory, non-volatile memory, such as read-only memory (ROM), optical or optical disk storage, flash memory, etc. The memory can be included as part of the computer-readable media described above.

[0147] Computer-readable media includes permanent and non-permanent, movable and non-movable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device. According to the definition herein, computer-readable media does not include transitory media such as modulated data signals and carriers.

[0148] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article or apparatus that includes a list of elements not only includes those elements, but also includes other elements not explicitly listed, or other elements inherent to such a process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0149] Note that the above are only preferred embodiments of the present application and the principles of technology used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A hardware acceleration device, characterized by, The hardware acceleration device comprises at least one of the following modules: An initial module configured to buffer an original time domain signal; A read pointer cycle module configured to generate a periodically and successively replaced initial signal based on the original time domain signal; A first mirror address translation module configured to convert the periodically and successively replaced initial signal into a pointer timing adapted to an FFT module, so as to continuously provide data of a time domain signal to be processed to the FFT module; The FFT module comprises an FFT recursive body module, and the FFT module is configured to receive data of the time domain signal to be processed in an optimal timing and convert the data of the time domain signal to be processed into a periodically and successively replaced frequency domain signal through the FFT recursive body module, and the FFT recursive body module is configured to perform a butterfly operation of any number of cycles; A second mirror address translation module configured to receive the periodically and successively replaced frequency domain signal and convert the periodically and successively replaced frequency domain signal into a pointer timing adapted to an IFFT module, so as to continuously provide data of a frequency domain signal to be processed to the IFFT module; and / or The IFFT module comprises an IFFT recursive body module, and the IFFT module is configured to receive data of the frequency domain signal to be processed in an optimal timing and restore the data of the frequency domain signal to be processed into an original time domain signal through the IFFT recursive body module, and the IFFT recursive body module is configured to perform a butterfly operation of any number of cycles; The FFT recursive body module and the IFFT recursive body module each comprise a basic recursive unit module and N layers of recursive body modules, N being a maximum number of nested layers of recursive calls performed by the FFT recursive body module or the IFFT recursive body module, The FFT recursive body module and the IFFT recursive body module each comprise a topmost layer recursive body module and a bottommost layer recursive body module, the topmost layer recursive body module being a recursive body module performing an Nth layer of recursive calls, and the bottommost layer recursive body module being the basic recursive unit module; Each layer of recursive body modules has four directions of butterfly pointers, and any one direction of butterfly pointers comprises two small pointers of the same direction in a previous layer of recursive body modules; the two small pointers of the same direction in the previous layer of recursive body modules successively perform two pointer operations at a rate of 2 times per pointer operation of the recursive body module; and A state cycle of a current layer of recursive body modules is 2 times a state cycle of a previous layer of recursive body modules, and a data bit width of the current layer of recursive body modules is 2 times a data bit width of the previous layer of recursive body modules.

2. The hardware acceleration device according to claim 1, wherein The FFT module implements an FFT operation of 4 to positive infinity points by performing any number of recursive calls on the FFT recursive body module, so as to convert the data of the time domain signal to be processed into the periodically and successively replaced frequency domain signal. The IFFT module realizes FFT operation of 4 to positive infinity points by recursively calling the IFFT recursive body module for any times, so as to restore the data of the to-be-processed frequency domain signal to the original time domain signal.

3. The hardware acceleration device of claim 1, wherein, Each recursive body module comprises a butterfly pipeline gating timing module which has the same sequence but whose execution time is twice that of the previous recursive body module.

4. The hardware acceleration device of claim 3, wherein, The butterfly pipeline gating timing module comprises at least one invisible state machine module, the invisible state machine module in each recursive body module comprises four states of 0, 1, 2 and 3 of the current layer butterfly operation, and the butterfly pipeline pointers in the four states are guided in the same direction, wherein 0 represents multiplication and accumulation on the left front wing of the butterfly, 1 represents multiplication and accumulation on the left rear wing of the butterfly, 2 represents multiplication and accumulation on the right front wing of the butterfly, and 3 represents multiplication and accumulation on the right rear wing of the butterfly.

5. The hardware acceleration device of claim 4, wherein, The data pipeline with the data bit width of W in each recursive body module comprises two data pipelines with the data bit width of W / 2.

6. A hardware acceleration method, characterized by, The method comprises one or more of the following steps: buffering the original time domain signal; generating a periodically continuous replacement initial signal based on the original time domain signal; converting the periodically continuous replacement initial signal into a pointer timing suitable for FFT transformation to obtain data of a to-be-processed time domain signal; receiving the data of the to-be-processed time domain signal in an optimal timing and converting the data of the to-be-processed time domain signal into a periodically continuous replacement frequency domain signal through an FFT recursive body module, the FFT recursive body module being configured to perform a butterfly Russian doll operation which can be looped for any times; converting the periodically continuous replacement frequency domain signal into a pointer timing suitable for IFFT transformation to obtain data of a to-be-processed frequency domain signal; receiving the data of the to-be-processed frequency domain signal in an optimal timing and restoring the data of the to-be-processed frequency domain signal to the original time domain signal through an IFFT recursive body module, the IFFT recursive body module being configured to perform a butterfly Russian doll operation which can be looped for any times; The FFT recursive body module and the IFFT recursive body module each comprise a basic recursive unit module and N layers of recursive body modules, N being the maximum nesting number of recursive calls of the FFT recursive body module or the IFFT recursive body module, The FFT recursive body module and the IFFT recursive body module each comprise a topmost recursive body module and a bottommost recursive body module, the topmost recursive body module being a recursive body module which performs the Nth recursive call, and the bottommost recursive body module being the basic recursive unit module. Each recursive body module has four directions of butterfly pointers, and any one direction of butterfly pointers contains two small pointers of the same direction in the previous recursive body module; the two small pointers of the same direction in the previous recursive body module successively perform two pointer operations at a rate of 2 times per execution of the pointer operation of the recursive body module; The state cycle of the current recursive body module is 2 times the state cycle of the previous recursive body module, and the data bit width of the current recursive body module is 2 times the data bit width of the previous recursive body module.

7. The hardware acceleration method of claim 6, wherein, Each recursive body module includes a butterfly pipeline gating timing sequence which is the same as the previous recursive body module but has an execution time of 2 times the execution time of the previous recursive body module.

8. The hardware acceleration method of claim 6, wherein, The butterfly pipeline gating timing sequence module includes at least one invisible state machine module, and the invisible state machine module in each recursive body module includes four states of the current layer butterfly operation 0, 1, 2, and 3, and the directions of the butterfly pipeline pointers in the four states are consistent, wherein 0 represents multiplying and accumulating the left front wing of the butterfly, 1 represents multiplying and accumulating the left rear wing of the butterfly, 3 represents multiplying and accumulating the right front wing of the butterfly, and 4 represents multiplying and accumulating the right rear wing of the butterfly.

9. A hardware acceleration system, characterized by, The hardware acceleration system includes the hardware acceleration device of any one of claims 1-4.

10. A non-transitory computer-readable storage medium, comprising: The non-transitory computer readable storage medium stores computer instructions adapted to be loaded by a processor to implement the hardware acceleration method of any one of claims 6-8.

Images