1results about How to "Implement data access" patented technology

This invention relates to an architecture compatible with cache / tcm for high-speed DSP access to a low-speed bus; it includes: a one-to-two bus switch h1to2 switching module, a two-to-one bus switch h2to1 switching module, a two-to-two system bus interconnect s2to2 module, and a cache; one master terminal of the h1to2 switching module is connected to the DSP, and two slave terminals are respectively connected to the cache and one master terminal of the s2to2 module; two master terminals of the h2to1 switching module are respectively connected to the cache and one slave terminal of the s2to2 module, and one slave terminal is connected to the bus; the remaining master and slave terminals of the s2to2 module are respectively connected to the bus and the cache; by switching the master and slave terminals of the h1to2 and h2to1 switching modules, a data access path from the DSP to the bus via the cache is established in cache mode; or, by combining the access address range of the slave terminals of the s2to2 module, in tcm mode, data flow processing is performed from the DSP to the cache via the s2to2 module, from the DSP to the system bus via the s2to2 module, and from the system bus to the cache via the s2to2 module. This invention supports both cache and TCM working modes.