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Device for supporting rapid rounding of IEEE floating point operation

A floating-point operation and rounding technology, applied in computing, instrumentation, electrical digital data processing, etc., can solve problems such as inability to apply rounding and inability to meet rounding requirements

Inactive Publication Date: 2010-07-21
NORTHWESTERN POLYTECHNICAL UNIV
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  • Abstract
  • Description
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Problems solved by technology

However, the rapid rounding method disclosed in Document 3 cannot provide all six possible results for the final choice
[0017] In summary, when performing the rounding of the bit iteration algorithm, the known fast rounding device can only generate three possible results, which cannot be applied to the rounding based on the IEEE754 standard, nor can it meet the requirements of high-basic iterative algorithms and different calculation bit widths. The rounding requirements under

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  • Device for supporting rapid rounding of IEEE floating point operation
  • Device for supporting rapid rounding of IEEE floating point operation
  • Device for supporting rapid rounding of IEEE floating point operation

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Embodiment Construction

[0045] refer to Figure 1-8 . The device of the invention comprises a register file, a register update circuit, a remainder network circuit, a splicing circuit, a quotient selector and a rounding judgment circuit.

[0046] Among them, the register file includes: 6 m2-bit wide registers: the first register, the second register, the third register, the fourth register, the fifth register, and the sixth register; 5 1-bit wide flag registers: the seventh register , the eighth register, the ninth register, the tenth register, the eleventh register; two m1-bit wide registers: the twelfth register and the thirteenth register. The relationship between the bit widths of these registers is: if the bit width of the final quotient is n, then there are m1+m2=n+3, and m2=2+log 2 a.

[0047] The update circuit of the register is based on the quotient q generated by each beat iteration k+1 Update each register, which is characterized by: according to the quotient q of each beat of the ite...

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Abstract

The invention discloses a device for supporting the rapid rounding of the IEEE floating point operation, which is used for solving the technical problem that the prior art can not be applicable to the rounding based on the IEEE754 standard. The invention comprises the technical scheme that the device comprises a register file, a register updating circuit, a residue network circuit, a split joint circuit, a division result selector and a rounding judging circuit. The invention can fast generate six results meeting the IEEE754 standard rounding requirements through improving the register updating circuit and the register file and adding the split joint circuit, in addition, the six results can cover all possible rounding results under the conditions of the high base iterative algorithm and different bit widths, the six results are selected to obtain the final rounding result, and the invention can meet the rapid rounding requirements based on the IEEE754 standard under the conditions of the high base iterative algorithm and different bit widths.

Description

technical field [0001] The invention relates to a fast rounding device, in particular to a fast rounding device supporting IEEE floating-point calculation. Background technique [0002] When bit iteration algorithm is used for floating-point division, square root operation and other online operations, in order to simplify the generation of times quotient, the pair quotient is often expressed in redundant form. Document 1 "A new class of digital division methods, IRETrans. Electron. Comput., EC-7 (3): 88-92, Sept. 1958. and document Techniques of multiplication and division for automatic binary computers, Quarterly J. of Mechanics and Applied Mathematics, 1958, 11(3): 364-384." discloses a classic SRT method, the selection range of which is {-a, -a+1, ..., -1, 0, 1 ,...a-1, a}, where r 2 ≤ a < r , r is the basis of the SRT method. The redundant form of the quotient can be positive or nega...

Claims

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Application Information

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IPC IPC(8): G06F7/487G06F7/57
Inventor 高德远姚涛樊晓桠张盛兵王党辉魏廷存黄小平张萌郑然
Owner NORTHWESTERN POLYTECHNICAL UNIV