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Big Data Operation Acceleration System and Chip

A computing chip and acceleration system technology, applied in the fields of electrical digital data processing, digital computer components, calculation, etc., can solve the problems of increasing system cost and waste of storage units, etc., to reduce system cost, simplify system structure, and save memory units Quantity effect

Active Publication Date: 2022-05-13
北京算能科技有限公司
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

However, when multiple computing chips work at the same time, the data storage capacity will not exceed 2 G, which causes waste of storage units and increases system cost

Method used

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  • Big Data Operation Acceleration System and Chip
  • Big Data Operation Acceleration System and Chip
  • Big Data Operation Acceleration System and Chip

Examples

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Embodiment Construction

[0027] The following will specifically describe the exemplary implementations of this embodiment based on the accompanying drawings. It should be understood that these implementations are given only to enable those skilled in the art to better understand and realize the present invention, but not to limit the present invention in any way range. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0028] In addition, it should be noted that the directions of up, down, left, and right in the drawings are only examples of specific implementations, and those skilled in the art can adjust the components shown in the drawings according to actual needs. A part or all of them can be applied by changing the direction without affecting the function of each component or the system as a whole. Such a technical solution of changing the direction still belongs to the pro...

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Abstract

The present application provides a big data operation acceleration system and a chip. By setting multiple core cores in the chip, each core core performs calculation and storage control functions, and at least one storage unit is connected to each core core outside the chip. By adopting the technical solution of the present invention, each core can achieve the technical effect that each core can have a large-capacity memory by reading the storage unit connected to itself and the storage unit connected to other cores, reducing the need for data to be moved in or out from the external storage space. The number of times to move out of the memory speeds up the data processing speed; at the same time, because multiple cores can operate independently or cooperatively, this also speeds up the data processing speed.

Description

technical field [0001] The embodiments of the present invention relate to the field of integrated circuits, in particular to a big data operation acceleration system and chip. Background technique [0002] ASIC (Application Specific Integrated Circuits) is an application-specific integrated circuit, which refers to an integrated circuit designed and manufactured in response to specific user requirements and the needs of a specific electronic system. The characteristic of ASIC is that it is oriented to the needs of specific users. Compared with general-purpose integrated circuits, ASIC has the advantages of smaller size, lower power consumption, improved reliability, improved performance, enhanced confidentiality, and reduced cost when mass-produced. [0003] With the development of science and technology, more and more fields, such as artificial intelligence, security computing, etc., involve specific calculations with large amounts of calculations. For specific calculation...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/173
CPCG06F15/17312G06F15/17356G06F15/17375
Inventor 桂文明
Owner 北京算能科技有限公司
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