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Logic output pre-guiding method and structure of macro cell under narrow channel layout

A logic output and guiding structure technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as insufficient routing track resources and inability to meet logic output requirements, and achieve the effect of meeting logic output requirements

Pending Publication Date: 2020-10-30
ANHUI DONGKE SEMICON CO LTD
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Problems solved by technology

[0004] The purpose of the present invention is to provide a logic output pre-guiding method and structure of a macro unit in a narrow channel la

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  • Logic output pre-guiding method and structure of macro cell under narrow channel layout
  • Logic output pre-guiding method and structure of macro cell under narrow channel layout
  • Logic output pre-guiding method and structure of macro cell under narrow channel layout

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Embodiment Construction

[0037] The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0038] An embodiment of the present invention provides a logic output pre-steering method for a macro unit in a narrow channel layout, the main steps of which are as follows figure 1 shown, including:

[0039] Step 110, after the layout of the macro-units, perform pre-winding processing on all the macro-units according to the output logic of all the macro-units, and determine whether the channel size of the channel between any two adjacent macro-units after the layout meets the routing requirements. orbital resource requirements;

[0040] Specifically, after the layout of the macro-units, the position of each macro-unit has been determined. Each macro-unit has its own output logic, and the routing track resources required for the output of each macro-unit can be calculated according to the output logic.

[0041] In ...

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Abstract

The embodiment of the invention relates to a logic output pre-guiding method and structure of a macro cell under a narrow channel layout. The method comprises the following steps: after macro-cell layout, carrying out pre-winding processing on all macro-cells according to output logic of all macro-cells, and determining whether the channel size of a channel between any two adjacent macro-cells after layout meets a routing track resource demand or not; when the channel size of the first channel between the first macro unit and the second macro unit which are adjacent does not meet the routing track resource requirement, performing pre-guide processing on the first channel; increasing an output of each buffer of a first buffer array and a second buffer array by performing a pre-steering process on a first channel. Pin output logics of the first macro unit and the second macro unit are led out of the first channel, so the layout of the corresponding logic function units is carried out, the logic function units are in wiring connection with the pins through buffers, and the problem that logic output requirements cannot be met due to the fact that wiring track resources are insufficientunder the narrow channel layout is solved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit layout design and optimization, in particular to a logic output pre-guiding method and structure of a macro unit under narrow channel layout. Background technique [0002] In digital backend integrated circuit (IC) design, macro cell (Macro) is the most common unit in the design. A macrocell is a predefined logic function implementation unit composed of flip-flops, arithmetic logic units, hardware temporary registers, etc., which have a higher abstraction level than logic gates. These logic cells are placed on the silicon chip as a whole as a macrocell. During the manufacturing process, engineers need to build metal interconnection lines between each predefined unit, and different wiring methods can realize different functions at a higher logic level. [0003] In the design, the macrocells are arranged in an array, and there is a wiring track aisle between every two macrounits, which ...

Claims

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Application Information

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IPC IPC(8): G06F30/3947
CPCG06F30/3947
Inventor 赵少峰
Owner ANHUI DONGKE SEMICON CO LTD