ESD protection device and electronic device

Abstract

The present invention provides an ESD protection device and an electronic device, the ESD protection device comprising: a main thyristor rectifier, the main thyristor rectifier having an anode terminal and a cathode terminal, the anode terminal being connected to the anode of the ESD protection device; at least one trigger unit, each of the trigger units comprising a secondary thyristor rectifier and a resistor unit arranged in parallel, the anode terminal of the secondary thyristor rectifier being connected to the cathode terminal of the main thyristor rectifier or the adjacent secondary thyristor rectifier, the cathode terminal of the secondary thyristor rectifier being connected to the anode terminal of the adjacent secondary thyristor rectifier or the cathode of the ESD protection device, and the resistor unit being connected in parallel between the anode terminal and the cathode terminal of the secondary thyristor rectifier. The ESD protection device can increase the holding voltage while basically keeping the trigger voltage unchanged, so as to better avoid the latch effect. The electronic device has similar advantages.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an ESD protection device and an electronic device. Background Art

[0002] As CMOS technology continues to scale down, IC chip failure caused by electrostatic discharge (ESD) has become a major reliability issue, especially for small devices with ultra-thin gate oxide layers and thin dielectric layers, which show a more serious ESD damage trend. ESD protection design is becoming more and more challenging and difficult in nano-scale CMOS technology.

[0003] Modern power electronics circuits, such as automotive electronics, LCDs, and LED drivers often utilize supply voltages in the tens of volts range. For high voltage applications, this, along with the harsh operating environment and noise from switching, makes latch-up a major consideration in the design of electrostatic discharge (ESD) protection schemes. Increasing the holding voltage (operating voltage after triggering) of ESD protection devices is an effective way to mitigate the latch-up problem. However, for area-efficient SCRs (silicon-controlled rectifiers), it is difficult to increase the holding voltage due to the inherent strong regenerative feedback phenomenon.

[0004] Therefore, it is necessary to improve the ESD protection device composed of SCR to increase its holding voltage, thereby avoiding the latch effect and making it suitable for high voltage applications. Summary of the invention

[0005] The present invention provides an ESD protection device and an electronic device, which can increase the holding voltage while substantially keeping the trigger voltage unchanged, so as to better avoid the latch effect, thereby making the ESD protection device suitable for high voltage applications.

[0006] One aspect of the present invention provides an ESD protection device, which is formed on a semiconductor substrate and includes:

[0007] A main silicon controlled rectifier, the main silicon controlled rectifier having an anode terminal and a cathode terminal, the anode terminal being connected to the anode of the ESD protection device;

[0008] At least one trigger unit, each of the trigger units includes a secondary thyristor rectifier and a resistance unit arranged in parallel, the anode terminal of the secondary thyristor rectifier is connected to the cathode terminal of the main thyristor rectifier or the adjacent secondary thyristor rectifier, the cathode terminal of the secondary thyristor rectifier is connected to the anode terminal of the adjacent secondary thyristor rectifier or the cathode of the ESD protection device, and the resistance unit is connected in parallel between the anode terminal and the cathode terminal of the secondary thyristor rectifier.

[0009] In one embodiment of the present invention, each of the trigger units includes a first N-well and a P-well arranged in parallel, a P+ injection region and N+ injection regions located on both sides of the P+ injection region are formed in the first N-well, an N+ injection region and P+ injection regions located on both sides of the N+ injection region are formed in the P-well, the P+ injection region in the first N-well, the first N-well, the P-well and the N+ injection region in the P-well constitute the thyristor, the N+ injection region in the first N-well, the first N-well, the P-well and the P-well constitute the resistance unit,

[0010] Among them, the P+ injection area in the first N well is used as the anode terminal of the thyristor rectifier, the N+ injection area in the P well is used as the cathode terminal of the thyristor rectifier, the two N+ injection areas of the first N well are respectively connected to the P+ injection area of ​​the first N well and a P+ injection area in the P well, and the two P+ injection areas of the P well are respectively connected to an N+ injection area in the first N well and the N+ injection area in the P well.

[0011] In an embodiment of the present invention, each of the trigger units further includes a second N-well arranged in parallel with the P-well, and the first N-well and the second N-well are arranged on both sides of the P-well.

[0012] In one embodiment of the present invention, the main thyristor rectifier includes a first N-well and a P-well arranged in parallel, a P+ injection area and an N+ injection area are formed in the first N-well, an N+ injection area and a P+ injection area are formed in the P-well, the N+ injection area in the first N-well is connected to the P+ injection area of ​​the first N-well and serves as the anode terminal of the main thyristor rectifier, and the P+ injection area of ​​the P-well is connected to the N+ injection area in the P-well and serves as the cathode terminal of the main thyristor rectifier.

[0013] In one embodiment of the present invention, the main silicon controlled rectifier further includes an N+ implantation region spanning the first N-well and the P-well.

[0014] In one embodiment of the present invention, the main thyristor rectifier further includes a second N-well arranged in parallel with the P-well, and the first N-well and the second N-well are arranged on both sides of the P-well.

[0015] In one embodiment of the present invention, the main thyristor rectifier also includes a gate arranged between an N+ injection region spanning the first N-well and the P-well and an N+ injection region in the P-well, the gate is connected to the P+ injection region in the P-well, and the N+ injection region in the P-well is connected to the anode terminal of the trigger unit.

[0016] In one embodiment of the present invention, the main thyristor rectifier includes a high-voltage N-well and a P-type body region and an N-type drift region arranged in the high-voltage N-well, the P-type body region and the N-type drift region are arranged at intervals, a gate is arranged between the P-type body region and the N-type drift region, an N+ injection region and a P+ injection region are formed in the P-type body region, and an N+ injection region, an N+ injection region and a P+ injection region are formed in the N-type drift region, the N+ injection region and the P+ injection region in the N-type drift region are connected to serve as the anode end of the main thyristor rectifier, and the P+ injection region and the N+ injection region in the P-type body region are connected to serve as the cathode end of the main thyristor rectifier.

[0017] In one embodiment of the present invention, an isolation structure is provided between adjacent P+ implantation regions and N+ implantation regions.

[0018] In one embodiment of the present invention, a deep N-well is disposed adjacent to the P-well.

[0019] In one embodiment of the present invention, the P+ implantation region and the N+ implantation region are arranged in a strip shape.

[0020] In an embodiment of the present invention, the number of the trigger units is 2-6.

[0021] According to the ESD protection device of the present invention, since the main thyristor rectifier is connected in series with the trigger unit, and the trigger unit includes a secondary thyristor rectifier and a resistor unit arranged in parallel, when the main thyristor rectifier is triggered, the current is first released through the resistor unit. As the current increases, when the trigger voltage of the secondary thyristor rectifier in the trigger unit is reached, the secondary thyristor rectifier is triggered, and the current is released through the secondary thyristor rectifier. In this process, the trigger voltage of the entire ESD protection device depends on the trigger voltage of the main thyristor rectifier, and the secondary thyristor rectifier in the trigger unit is triggered by the voltage on the resistor unit. When all are triggered, the maintenance voltage of the entire ESD protection device is equal to the sum of the maintenance voltages of the main thyristor rectifier and each secondary thyristor rectifier, which is much higher than the maintenance voltage of the main thyristor rectifier. That is, the ESD protection device according to the present invention can increase the maintenance voltage while almost not increasing the trigger voltage, and can better overcome the latch effect, so that it is more suitable for high-voltage applications or other applications.

[0022] Another aspect of the present invention provides an electronic device, which includes the ESD protection device as described above and an electronic component connected to the ESD protection device.

[0023] The electronic device proposed by the present invention has similar advantages due to the presence of the above-mentioned ESD protection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0025] In the attached figure:

[0026] Figure 1 A schematic cross-sectional view of a current stacked SCR device is shown;

[0027] Figure 2 A schematic cross-sectional view of a stacked LDMOS-SCR device with current resistance triggering is shown;

[0028] Figure 3 A schematic cross-sectional view of a current self-triggered stacked SCR device is shown;

[0029] Figure 4 A schematic cross-sectional view of an ESD protection device according to an embodiment of the present invention is shown;

[0030] Figure 5 Show Figure 1 The stacked SCR device and Figure 4 The voltage and current simulation curve diagram of the ESD protection device shown;

[0031] Figure 6 A schematic diagram showing an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0033] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0034] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0035] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] In order to fully understand the present invention, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0038] As mentioned above, in order to use SCR (silicon controlled rectifier) ​​devices for ESD protection in high voltage applications, it is necessary to increase their holding voltage (the operating voltage after the ESD device is triggered is called the holding voltage) to avoid the latch effect. There are currently several solutions to increase the holding voltage of SCR devices. Figures 1 to 3 Provide a brief description.

[0039] Currently, one method to increase the maintenance voltage of SCR devices is to stack the SCR devices. Figure 1 FIG. 2 shows a schematic cross-sectional view of a current stacked SCR device. Figure 1 As shown, the stacked SCR device 100 includes N SCR devices connected in series, each SCR device is an MLSCR device (modified lateral silicon-control-rectifier), which includes an N-type epitaxial region (N-epi) / N-type tube region (N-Tub) formed in a substrate P-sub (P-type substrate), an N well (NW) and a P well (PW) are formed in the N-type epitaxial region (N-epi) / N-type tube region (N-Tub), an N+ injection region and a P+ injection region are formed in the N well, an N+ injection region and a P+ injection region are formed in the P well, an N ring surrounding the N well and the P well is also formed in the N-type epitaxial region (N-epi) / N-type tube region (N-Tub), and the stacked SCR device 100 also includes a P ring surrounding each SCR device. The holding voltage of the stacked SCR device 100 is equal to the sum of the holding voltages of the individual SCR devices. The holding voltage of the stacked SCR device 100 can be adjusted by changing the number of stacked units or the size of each unit to be suitable for various applications. At the same time, in order to avoid potential latch-up effects, the N ring is connected to the operating voltage VDD and the P ring is grounded. However, for this stacked SCR device, the trigger voltage increases exponentially with the number of series connections, which is not what is expected of a high-voltage ESD device.

[0040] In order to solve the coupling problem between the trigger voltage and the holding voltage in the stacked structure (ie, both the trigger voltage and the holding voltage increase), a stacked SCR-LDMOS device triggered by a ring resistor is proposed. Figure 2 FIG. 2 shows a schematic cross-sectional view of a stacked LDMOS-SCR device that is currently triggered by a resistor. Figure 2As shown, the stacked SCR-LDMOS device 200 includes a trigger SCR-LDMOS unit and a plurality of stacked units, the stacked unit is a ring resistor triggered SCR-LDMOS, the trigger SCR-LDMOS unit and the ring resistor triggered SCR-LDMOS have the same basic structure, including a high voltage N-well (HVN-Well) formed in a P-type substrate P-sub, a P-type body region and an N-type drift region formed in the high voltage N-well, and a gate formed between the P-type body region and the N-type drift region, a P+ injection region and an N+ injection region formed in the P-type body region and the N-type drift region, the P+ injection region and the N+ injection region in the N-type drift region are connected together as an anode terminal, the P+ injection region and the N+ injection region in the P-type body region are connected together as a cathode terminal, and the ring resistor triggered SCR-LDMOS also includes a ring resistor arranged in parallel between the anode terminal and the cathode terminal. The stacked SCR-LDMOS device 200 also includes a P+ ring surrounding the trigger SCR-LDMOS unit or the ring resistor triggered SCR-LDMOS. This structure can maintain the voltage by adjusting the number of stacks while the trigger voltage remains almost constant. However, in order to implement auxiliary triggering, the P+ ring needs to be disconnected from the operating voltage VDD, which introduces a potential latch-up risk.

[0041] Figure 3 A schematic cross-sectional view of a self-triggered stacked SCR device is shown. The self-triggered stacked SCR device 300 includes a main SCR device (which is an MLSCR device) and a plurality of DTSCR devices (diode-triggered SCR devices) connected in series with the main SCR device. The combination and connection relationship of each unit are as follows: Figure 3 As shown. The trigger voltage of this structure is basically determined by the trigger voltage of the MLSCR device, while the sustaining voltage of the MLSCR device and the number of DTSCRs determine the trigger voltage. That is, this structure can also improve the sustaining voltage while keeping the trigger voltage unchanged. However, the simulation results show that at high currents, the current is mainly released through a single diode channel in the DTSCR device rather than through the desired SCR channel, which makes the device less efficient in improving the sustaining voltage, and thus the voltage drop of the diode is very low.

[0042] The present invention further improves on the structural deficiencies of the aforementioned ESD device and proposes a structure that can increase the sustaining voltage while substantially keeping the triggering voltage unchanged, while having a higher sustaining voltage improvement efficiency.

[0043] Figure 4 A schematic cross-sectional view of an ESD protection device according to an embodiment of the present invention is shown.

[0044] like Figure 4As shown, the ESD provided in this embodiment includes a device 400 formed on a semiconductor substrate P-sub (P-type substrate), and the ESD protection device 400 includes a main thyristor rectifier 401 and a plurality of trigger units 402 to 40n, and the number of the trigger units is greater than or equal to 1.

[0045] The semiconductor substrate may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures formed by these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI). As an example, in this embodiment, the constituent material of the semiconductor substrate is single crystal silicon. Exemplarily, in this embodiment, the substrate is a P-type substrate. It should be understood that in other embodiments, the substrate may also be an N-type substrate.

[0046] In this embodiment, the main thyristor rectifier 401 is a MLSCR device (modified lateral silicon-control-rectifier), which includes a first N-well, a P-well and a second N-well arranged in parallel, and the first N-well and the second N-well are arranged on both sides of the P-well. A P+ injection region and an N+ injection region are formed in the first N-well, and an N+ injection region and a P+ injection region are formed in the P-well. The N+ injection region in the first N-well is connected to the P+ injection region of the first N-well and serves as the anode terminal of the main thyristor rectifier 401, and the P+ injection region of the P-well is connected to the N+ injection region in the P-well and serves as the cathode terminal of the main thyristor rectifier 401. The P+ injection region in the first well, the first N-well, the P-well and the N+ injection region in the P-well constitute an SCR device, and the second N-well is used to isolate the P-well from a substrate or an adjacent trigger unit.

[0047] like Figure 4 As shown, the main thyristor rectifier 401 also includes an N+ injection region spanning the first N-well and the P-well, and the trigger voltage of the main thyristor rectifier 401 can be adjusted through the N+ injection region spanning the first N-well and the P-well.

[0048] In this embodiment, the trigger units 402-402n include a secondary thyristor rectifier and a resistor unit arranged in parallel, the anode terminal of the secondary thyristor rectifier is connected to the cathode terminal of the main thyristor rectifier 401 or the adjacent secondary thyristor rectifier, the cathode terminal of the secondary thyristor rectifier is connected to the anode terminal of the adjacent secondary thyristor rectifier or the cathode of the ESD protection device, and the resistor unit is connected in parallel between the anode terminal and the cathode terminal of the secondary thyristor rectifier. In other words, the anode terminal of the main thyristor rectifier 401 is connected to the anode of the ESD protection device 400, and the cathode terminal is connected to the anode terminal of the first trigger unit, and the cathode terminal of the first trigger unit is connected to the anode terminal of the second trigger unit, and so on, and the cathode terminal of the last trigger unit is connected to the cathode of the ESD protection device.

[0049] Please refer again Figure 4 The trigger unit 402-40n includes a first N-well, a P-well and a second N-well arranged in parallel, and the first N-well and the second N-well are arranged on both sides of the P-well. A P+ injection region and N+ injection regions located on both sides of the P+ injection region are formed in the first N-well, and an N+ injection region and P+ injection regions located on both sides of the N+ injection region are formed in the P-well. The P+ injection region in the first N-well, the first N-well, the P-well and the N+ injection region in the P-well constitute a silicon controlled rectifier (i.e., an SCR device), and the N+ injection region in the first N-well, the first N-well, the P+ injection region in the P-well and the P-well constitute the resistor unit. The P+ injection region in the first N-well is used as the anode terminal of the thyristor, the N+ injection region in the P-well is used as the cathode terminal of the thyristor, the two N+ injection regions of the first N-well are respectively connected to the P+ injection region of the first N-well and one P+ injection region in the P-well, and the two P+ injection regions of the P-well are respectively connected to one N+ injection region in the first N-well and the N+ injection region in the P-well. The second N-well is used to isolate the P-well from a substrate or an adjacent trigger unit.

[0050] That is, the structure of the trigger unit 402-40n is similar to that of the main thyristor rectifier 401, except that, in the trigger unit 402-40n, an N+ injection region and a P+ injection region are respectively inserted into the first N well and the P well to form a resistance unit, so that the trigger unit has a resistance characteristic at the beginning of the trigger stage of the ESD protection device 400.

[0051] In this embodiment, the size of the trigger units 402-40n is substantially the same as the size of the main silicon controlled rectifier 401. Figure 4As shown, the distance between the N+ injection region and the P+ injection region in the first N-well of the main thyristor rectifier 401 and the P-well is L1, and the distance between the N+ injection region and the P+ injection region in the first N-well of the trigger unit 402-40n and the P-well is L2, and L1 is equal to L2. Of course, in other embodiments, L1 may also be greater than or less than L2.

[0052] In this embodiment, an isolation structure is provided between the adjacent P+ implantation region and the N+ implantation region, and the isolation structure is, for example, a STI (shallow trench isolation structure). The isolation between the P+ implantation region and the N+ implantation region is achieved through the isolation structure.

[0053] Furthermore, in this embodiment, a deep N-well is disposed adjacent to the P-well, and the deep N-well can be used to isolate the P-well from the substrate.

[0054] Furthermore, in this embodiment, the ESD protection device further includes a P+ ring surrounding / enclosing the main thyristor 401 or the trigger units 402 - 402 n , and the P+ ring is grounded, which can further avoid the latch-up effect.

[0055] Furthermore, in this embodiment, the P+ injection region and the N+ injection region are arranged in a strip shape.

[0056] It should be understood that the main silicon controlled rectifier 401 is not limited to the MLSCR device used in this embodiment, and other SCR devices may be used as needed. In some embodiments, the main silicon controlled rectifier 401 is a low voltage SCR device (LVTSCR). Figure 4 The structure of the main silicon controlled rectifier 401 shown further includes a gate arranged between the N+ injection region spanning the first N well and the P well and the N+ injection region in the P well, the gate is connected to the P+ injection region in the P well, and the N+ injection region in the P well is connected to the anode terminal of the trigger unit. The N+ injection region spanning the first N well and the P well, the N+ injection region in the P well and the gate constitute a MOS device, the breakdown voltage of the MOS device is the trigger voltage of the low voltage SCR device, so the low voltage SCR device has a lower trigger voltage.

[0057] In some embodiments, the main silicon controlled rectifier 401 is a SCR-LDMOS device, and its structure is shown in FIG. Figure 2As shown, it includes a high-voltage N-well and a P-type body region and an N-type drift region arranged in the high-voltage N-well, the P-type body region and the N-type drift region are arranged at intervals, a gate is arranged between the P-type body region and the N-type drift region, an N+ injection region and a P+ injection region are formed in the P-type body region, and an N+ injection region, an N+ injection region and a P+ injection region are formed in the N-type drift region, the N+ injection region and the P+ injection region in the N-type drift region are connected to serve as the anode end of the main thyristor rectifier, and the P+ injection region and the N+ injection region in the P-type body region are connected to serve as the cathode end of the main thyristor rectifier.

[0058] The working principle of the ESD protection device 400 of this embodiment is as follows: when the electrostatic voltage applied to the anode of the ESD protection device is lower than the trigger voltage of the main thyristor rectifier 401, the ESD protection device 400 is in the cut-off state, and as the voltage increases, when it is greater than the trigger voltage of the main thyristor rectifier 401, the main thyristor rectifier 401 is opened due to avalanche breakdown to release the electrostatic current, and the current is initially released through the resistance channel in the trigger unit, and because the trigger current of the main thyristor rectifier 401 is very small, the voltage on the resistance unit is limited, that is, the voltage on the secondary thyristor rectifier is small, and the secondary thyristor rectifier is not triggered. Therefore, the trigger voltage of the ESD protection device 400 depends on the trigger voltage of the main thyristor rectifier 401. As the current increases further, the PN junction in the parasitic PNP and NPN transistors (i.e., the secondary thyristor rectifier) ​​in the trigger unit is forward biased by the voltage drop on the resistor unit, the secondary thyristor rectifier in the trigger unit is triggered, the SCR channel is turned on, and the electrostatic discharge current is released through the main thyristor rectifier 401 and the SCR channel in the trigger unit, so that the maintenance voltage of the entire ESD protection device 400 is the sum of the maintenance voltages of the SCR devices. By adjusting the number of trigger units, the maintenance voltage can be made higher than the operating voltage VDD, thereby avoiding the latch effect. In other words, the ESD protection device 400 of this embodiment can effectively improve the maintenance voltage (because the SCR device has a relatively high maintenance voltage) while basically keeping the trigger voltage unchanged.

[0059] Figure 5 Show Figure 1 The stacked SCR device and Figure 4 The voltage and current simulation curve of the ESD protection device is shown in Figure 2. Figure 5 The leftmost solid curve represents the voltage-current curve of a single MLSCR device, and the dashed curves to the right of the leftmost solid curve represent Figure 1 The voltage-current curves when the number of stacked SCR devices is 2, 4, and 6, and the solid line curves to the right of the leftmost solid line curve respectively represent the voltage-current curves when the number of trigger units of the ESD protection device according to this embodiment is 2, 4, and 6. Figure 5 It can be seen that compared with a single SCR device, Figure 1 Although the stacked SCR device shown can increase the holding voltage by stacking, the trigger voltage increases exponentially with the number of stacks, which is not expected for ESD protection devices. According to the stacked SCR device, the holding voltage increases with the number of stacks, while the trigger voltage remains basically unchanged.

[0060] According to the ESD protection device of this embodiment, since the main thyristor rectifier is connected in series with the trigger unit, and the trigger unit includes a secondary thyristor rectifier and a resistor unit arranged in parallel, when the main thyristor rectifier is triggered, the current is first released through the resistor unit. As the current increases, when the trigger voltage of the secondary thyristor rectifier in the trigger unit is reached, the secondary thyristor rectifier is triggered, and the current is released through the secondary thyristor rectifier. In this process, the trigger voltage of the entire ESD protection device depends on the trigger voltage of the main thyristor rectifier, and the secondary thyristor rectifier in the trigger unit is triggered by the voltage on the resistor unit. When all are triggered, the maintenance voltage of the entire ESD protection device is equal to the sum of the maintenance voltages of the main thyristor rectifier and each secondary thyristor rectifier, which is much higher than the maintenance voltage of the main thyristor rectifier. That is, the ESD protection device according to the present invention can increase the maintenance voltage while almost not increasing the trigger voltage, and can better overcome the latch effect, so that it is more suitable for high-voltage applications or other applications.

[0061] Another aspect of the present invention also provides an electronic device, including an ESD protection device for an IC chip and an electronic component connected to the ESD protection device. The ESD protection device is located on a semiconductor substrate and includes: a main thyristor rectifier, the main thyristor rectifier has an anode terminal and a cathode terminal, the anode terminal is connected to the anode of the ESD protection device; at least one trigger unit, each of the trigger units includes a secondary thyristor rectifier and a resistor unit arranged in parallel, the anode terminal of the secondary thyristor rectifier is connected to the cathode terminal of the main thyristor rectifier or the adjacent secondary thyristor rectifier, the cathode terminal of the secondary thyristor rectifier is connected to the anode terminal of the adjacent secondary thyristor rectifier or the cathode of the ESD protection device, and the resistor unit is connected in parallel between the anode terminal and the cathode terminal of the secondary thyristor rectifier.

[0062] The electronic component may be any electronic component such as a discrete device or an integrated circuit.

[0063] The electronic device of this embodiment can be any electronic product or equipment such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or any intermediate product including the semiconductor device.

[0064] in, Figure 6 The exterior of the mobile phone 600 is provided with a display portion 602 included in a housing 601, operation buttons 603, an external connection port 604, a speaker 605, a microphone 606, and the like.

[0065] The electronic device of the embodiment of the present invention can increase the holding voltage while substantially maintaining the trigger voltage to better avoid the latch-up effect, thereby making the ESD protection device suitable for high-voltage applications. Therefore, the electronic device also has similar advantages.

[0066] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. An ESD protection device, the ESD protection device is formed on a semiconductor substrate, characterized in that: The ESD protection device includes: A main silicon controlled rectifier, the main silicon controlled rectifier having an anode terminal and a cathode terminal, the anode terminal being connected to the anode of the ESD protection device; at least one trigger unit, each of the trigger units comprises a secondary thyristor rectifier and a resistance unit arranged in parallel, the anode end of the secondary thyristor rectifier is connected to the cathode end of the main thyristor rectifier or the adjacent secondary thyristor rectifier, the cathode end of the secondary thyristor rectifier is connected to the anode end of the adjacent secondary thyristor rectifier or the cathode of the ESD protection device, and the resistance unit is connected in parallel between the anode end and the cathode end of the secondary thyristor rectifier; each of the trigger units comprises a first N-well and a P-well arranged in parallel, a P+ injection region and N+ injection regions located on both sides of the P+ injection region are formed in the first N-well, an N+ injection region and P+ injection regions located on both sides of the N+ injection region are formed in the P-well, the P+ injection region in the first N-well, the first N-well, the P-well and the N+ injection region in the P-well constitute the thyristor rectifier, and the N+ injection region in the first N-well, the first N-well and the P+ injection region in the P-well and the P-well constitute the resistance unit, Among them, the P+ injection area in the first N well is used as the anode terminal of the thyristor rectifier, the N+ injection area in the P well is used as the cathode terminal of the thyristor rectifier, the two N+ injection areas of the first N well are respectively connected to the P+ injection area of ​​the first N well and a P+ injection area in the P well, and the two P+ injection areas of the P well are respectively connected to an N+ injection area in the first N well and the N+ injection area in the P well.

2. The ESD protection device according to claim 1, characterized in that: Each of the trigger units further includes a second N-well arranged in parallel with the P-well, and the first N-well and the second N-well are arranged on both sides of the P-well.

3. The ESD protection device according to claim 1, characterized in that: The main thyristor rectifier includes a first N-well and a P-well arranged in parallel, a P+ injection area and an N+ injection area are formed in the first N-well, an N+ injection area and a P+ injection area are formed in the P-well, the N+ injection area in the first N-well is connected to the P+ injection area of ​​the first N-well and serves as the anode terminal of the main thyristor rectifier, and the P+ injection area of ​​the P-well is connected to the N+ injection area in the P-well and serves as the cathode terminal of the main thyristor rectifier.

4. The ESD protection device according to claim 3, characterized in that: The main silicon controlled rectifier also includes an N+ implantation region spanning the first N-well and the P-well.

5. The ESD protection device according to claim 4, characterized in that: The main silicon controlled rectifier further includes a second N-well arranged in parallel with the P-well, and the first N-well and the second N-well are arranged on both sides of the P-well.

6. The ESD protection device according to claim 4, characterized in that: The main thyristor rectifier also includes a gate arranged between an N+ injection region spanning the first N-well and the P-well and an N+ injection region in the P-well, the gate being connected to the P+ injection region in the P-well, and the N+ injection region in the P-well being connected to the anode terminal of the trigger unit.

7. The ESD protection device according to claim 1, characterized in that: The main thyristor rectifier includes a high-voltage N-well and a P-type body region and an N-type drift region arranged in the high-voltage N-well, the P-type body region and the N-type drift region are arranged at intervals, a gate is arranged between the P-type body region and the N-type drift region, an N+ injection region and a P+ injection region are formed in the P-type body region, an N+ injection region and a P+ injection region are formed in the N-type drift region, the N+ injection region and the P+ injection region in the N-type drift region are connected to serve as the anode terminal of the main thyristor rectifier, and the P+ injection region and the N+ injection region in the P-type body region are connected to serve as the cathode terminal of the main thyristor rectifier.

8. The ESD protection device according to claim 1 or 3, characterized in that: An isolation structure is arranged between the adjacent P+ implantation regions and the adjacent N+ implantation regions.

9. The ESD protection device according to claim 1 or 3, characterized in that: A deep N-well is disposed adjacent to the P-well.

10. The ESD protection device according to claim 1 or 3, characterized in that: The P+ implantation region and the N+ implantation region are arranged in a strip shape.

11. The ESD protection device according to claim 1, characterized in that: The number of the trigger units is 2-6.

12. An electronic device, characterized in that: The invention comprises an ESD protection device as claimed in any one of claims 1 to 11.

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