A GIP circuit and driving method thereof

Abstract

The present invention discloses a GIP circuit, wherein the input end of T1 is connected to VGH, and the output end is connected to Q1; the input end of T2 is connected to P1, and the control end is connected to Q1; the input end of T3 is connected to Q1, and the control end is connected to P1; the control end of T4 is connected to Q1; the input end of T7 is connected to Q1, and the control end is connected to G n+4 ; T12 input connected to P2, output connected to VGL, control connected to Q1; T13 input connected to Q1, output connected to VGL, control connected to P2; T14 input connected to VGH, output connected to Q2, control connected to G n‑4 ; The input end of T15 is connected to VGH, the output end is connected to Q1, and the control end is connected to Q2; the input end of T16 is connected to Q2, the output end is connected to VGL, and the control end is connected to CK; The above technical solution uses T14, T15, and T16 to control the potential of Q2, thereby preventing the output signal distortion caused by the GIP Q leakage of the GIP circuit in different touch modes, and at the same time improving the display quality and quality of the panel.

Description

Technical Field

[0001] The present invention relates to the field of LCD display screens, and in particular to a GIP circuit and a driving method thereof. Background Art

[0002] With the development of the times and the advancement of technology, people are becoming more and more picky about the appearance of mobile phones and other products, which has promoted the continuous development of electronic products towards lightness, thinness and power saving. Since the release of Apple iPhone 5 in 2012, the use of In-Cell technology to effectively reduce the thickness of mobile phones and other products has become more and more widely used.

[0003] Currently, touch technology is mainly divided into On-Cell technology and In-Celll technology: On Cell refers to the method of embedding the touch screen between the display screen and the polarizer, that is, equipping the display panel with a touch sensor; In-cell refers to embedding the touch panel function into the array substrate, so that the thickness of the In-Cell panel is greatly reduced due to the lack of a touch screen layer.

[0004] The screen using In-Cell technology has the advantages of lighter product, lower thickness, better light transmittance, reduced screen bonding time and improved production efficiency. However, the screen using In-Cell technology will have some problems when using different touch methods. Please refer to Figure 1 The In-Cell panel has two modes when displaying touch screen: the first mode is to divide a frame into Display Time and Blanking Time when displaying a frame, and the touch screen is inserted into the Blanking Time, that is, the touch screen is placed after the display time, and the sum of the two time periods is the time of a frame (we can call it Long V); the other mode is to insert the touch screen into the Display in batches when displaying a frame, that is, in a frame from top to bottom, it will be divided into a cycle of display-touch-display-touch-display (we can call it Long H). When the touch mode of Long H mode is used, since the touch stage will be inserted in the display stage, when the GIP design is adopted, a touch segment will be inserted between the two display segments, so that the Q1 point of the GIP of the second display segment will maintain a high potential for a longer period of time (about 200us). Due to the leakage problem of TFT, the Q1 point of the second display stage will have a large leakage problem, resulting in a large difference between the Q1 points of the first row GIP of the second display stage and the GIP of the first display stage, which may cause differences in the panel GIP output signals and cause horizontal dark lines to appear on the display. Summary of the invention

[0005] Therefore, it is necessary to provide a GIP circuit and a driving method thereof to prevent the output signal distortion problem caused by leakage of the GIPQ node of the GIP circuit in different touch modes, while improving the display image quality and quality of the panel.

[0006] To achieve the above object, the present application provides a GIP circuit, including transistors: T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16, and capacitors: C1 and C2;

[0007] The input end of T1 is connected to VGH, the output end of T1 is connected to Q1 node, and the control end of T1 is connected to G n-4 connect;

[0008] The input end of T2 is connected to the P1 node, the output end of T2 is connected to VGL, and the control end of T2 is connected to the Q1 node;

[0009] The input end of T3 is connected to the Q1 node, the output end of T3 is connected to VGL, and the control end of T3 is connected to the P1 node;

[0010] The input end of T4 is connected to CK, and the output end of T4 is connected to G n Connecting, the control end of T4 is connected to the Q1 node;

[0011] The input of T5 is connected to G n The output end of T5 is connected to VGL, and the control end of T5 is connected to the P1 node;

[0012] The input of T6 is connected to G n The output end of T6 is connected to VGL, and the control end of T6 is connected to the P2 node;

[0013] The input end of T7 is connected to the Q1 node, the output end of T7 is connected to VGL, and the control end of T7 is connected to G n+4 connect;

[0014] The input end of T8 is connected to V1, the output end of T8 is connected to the P1 node, and the control end of T8 is connected to V1;

[0015] The input end of T9 is connected to V2, the output end of T9 is connected to the P2 node, and the control end of T9 is connected to V2;

[0016] The input end of T10 is connected to the P1 node, the output end of T10 is connected to VGL, and the control end of T10 is connected to V2;

[0017] The input end of T11 is connected to the P2 node, the output end of T11 is connected to VGL, and the control end of T11 is connected to V1;

[0018] The input end of T12 is connected to the P2 node, the output end of T12 is connected to VGL, and the control end of T12 is connected to the Q1 node;

[0019] The input end of T13 is connected to the Q1 node, the output end of T13 is connected to VGL, and the control end of T13 is connected to the P2 node;

[0020] The input end of T14 is connected to VGH, the output end of T14 is connected to Q2 node, and the control end of T14 is connected to G n-4 connect;

[0021] The input end of T15 is connected to VGH, the output end of T15 is connected to the Q1 node, and the control end of T15 is connected to the Q2 node;

[0022] The input end of T16 is connected to the Q2 node, the output end of T16 is connected to VGL, and the control end of T16 is connected to CK;

[0023] One plate of C1 is connected to the Q1 node, and the other plate of C1 is connected to the G n connect;

[0024] The C2 is connected to the Q2 node.

[0025] Furthermore, one plate of C2 is connected to the Q2 node, and the other plate of C2 is grounded.

[0026] Furthermore, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 are all thin film transistors.

[0027] Furthermore, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 are all thin film transistors, and T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 are arranged on the display panel.

[0028] Furthermore, the display panel is an In-Cell touch panel.

[0029] The present application also provides a driving method of a GIP circuit, which is used for any one of the GIP circuits described above, and includes a display stage and a touch stage. The steps of the touch stage are as follows:

[0030] During touch precharge a1, G n-4 Write high potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK writes low potential, VGL writes low potential, V2 writes low potential;

[0031] During the touch voltage stabilization period a2, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK writes low potential, VGL writes low potential, V2 writes low potential;

[0032] During touch output a3, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, write high potential to CK, write low potential to VGL, and write low potential to V2;

[0033] During touch pull-down a4, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write high potential, write CK to low potential, write VGL to low potential, and write V2 to low potential;

[0034] During the touch pull-down maintenance period a4, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, write high potential to CK, write low potential to VGL, and write low potential to V2.

[0035] Furthermore, the display stage comprises the steps of:

[0036] During the display precharge period t1, G n-4 Write high potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK writes low potential, VGL writes low potential, V2 writes low potential;

[0037] During the display output period t2, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, write high potential to CK, write low potential to VGL, and write low potential to V2;

[0038] During the display pull-down period t3, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write high potential, write CK to low potential, write VGL to low potential, and write V2 to low potential;

[0039] During the display pull-down maintenance period t3, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, write high potential to CK, write low potential to VGL, and write low potential to V2.

[0040] Furthermore, the display phase and the touch phase are cycled multiple times within a preset time.

[0041] Different from the prior art, the above technical solution uses T14 / T15 / T16 to control the potential of Q2 point, thereby preventing the output signal distortion problem caused by leakage of GIP Q1 point of GIP circuit in different touch modes, and improving the display quality of the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is the Long V and Long H touch modes in the background technology;

[0043] Figure 2 A GIP circuit as described above;

[0044] Figure 3 A timing diagram showing a phase of a GIP circuit;

[0045] Figure 4 A timing diagram of the touch control phase of the GIP circuit;

[0046] Figure 5 This is a schematic diagram of the touch pre-charging stage;

[0047] Figure 6 is a schematic diagram of the touch control voltage stabilization stage;

[0048] Figure 7 is a schematic diagram of the touch output stage;

[0049] Figure 8 is a schematic diagram of the touch pull-down stage;

[0050] Fig. 9 It is a schematic diagram of the touch pull-down maintenance stage;

[0051] Fig.10 This is a timing diagram of the GIP circuit. DETAILED DESCRIPTION

[0052] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0053] Please refer to Figures 1 to Fig.10The application provides a GIP circuit, including transistors: T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16, and capacitors: C1 and C2; the input end of T1 is connected to VGH. Please refer to Figure 2 The output end of T1 is connected to the Q1 node, and the control end of T1 is connected to G n-4 The input end of T2 is connected to the P1 node, the output end of T2 is connected to VGL, and the control end of T2 is connected to the Q1 node; the input end of T3 is connected to the Q1 node, the output end of T3 is connected to VGL, and the control end of T3 is connected to the P1 node; the input end of T4 is connected to CK, and the output end of T4 is connected to G n The control end of T4 is connected to the Q1 node; the input end of T5 is connected to G n The output end of T5 is connected to VGL, the control end of T5 is connected to the P1 node; the input end of T6 is connected to G n The output end of T6 is connected to VGL, and the control end of T6 is connected to the P2 node; the input end of T7 is connected to the Q1 node, the output end of T7 is connected to VGL, and the control end of T7 is connected to G n+4 The input end of T8 is connected to V1, the output end of T8 is connected to the P1 node, and the control end of T8 is connected to V1; the input end of T9 is connected to V2, the output end of T9 is connected to the P2 node, and the control end of T9 is connected to V2; the input end of T10 is connected to the P1 node, the output end of T10 is connected to VGL, and the control end of T10 is connected to V2; the input end of T11 is connected to the P2 node, the output end of T11 is connected to VGL, and the control end of T11 is connected to V1; the input end of T12 is connected to the P2 node, the output end of T12 is connected to VGL, and the control end of T12 is connected to the Q1 node; the input end of T13 is connected to the Q1 node, the output end of T13 is connected to VGL, and the control end of T13 is connected to the P2 node; the input end of T14 is connected to VGH, the output end of T14 is connected to the Q2 node, and the control end of T14 is connected to G n-4 The input end of T15 is connected to VGH, the output end of T15 is connected to Q1 node, and the control end of T15 is connected to Q2 node; the input end of T16 is connected to Q2 node, the output end of T16 is connected to VGL, and the control end of T16 is connected to CK; one plate of C1 is connected to Q1 node, and the other plate of C1 is connected to G n One plate of C2 is connected to the Q2 node, and the other plate of C2 is grounded.

[0054] It should be noted that the transistors in this application can be P-type or N-type, that is, in N-type transistors, the input terminal is the drain and the output terminal is the source; in P-type transistors, the input terminal is the source and the output terminal is the drain; and no matter which type of transistor, the control terminal is the gate. G(n) is the output voltage, and G(n) is connected to a pixel; G is the gate voltage, and CK is the clock signal line; in this application, G (n) Indicates the nth sub-pixel in a row; G (n+4) and G (n-4) (n-4) and (n+4) are used to indicate the start-up cycle of the pixels in a row, that is, how many pixels are turned on in turn in each cycle. There are multiple such GIP circuits in the display panel, each GIP circuit is connected to a sub-pixel through G(n), and G(n+4) and G(n-4) are connected to the driver IC. Multiple sub-pixels are arranged in an array on the display panel, and a GIP circuit is provided on one side of each sub-pixel. In the accompanying drawings, the dotted transistors are transistors in the on state, and the solid line transistors are transistors in the off state. The gate, that is, the control terminal in this application, is used to control the on or off of the transistor. When a high voltage is written to the control terminal, the transistor will be turned on; for example: since VGH is continuously written to a high voltage, but only when G n-4 When a high voltage is input, T1 will be turned on. It should also be noted that in this application, VGL continuously writes a high potential, VGL continuously writes a low potential, V1 and V2 are connected to external components, and the corresponding voltage signal is input by the external components, and CK is a clock signal line.

[0055] In different time periods, the devices turned on by the GIP circuit are different, such as:

[0056] During the precharge period, G n-4 , V1 and VGH are high potential, and the corresponding T1, T8, T11, and T14 are turned on; VGH charges Q1 and Q2 through T1 and T14, causing Q1 and Q2 to rise to a high potential, and controlling T2, T4, T12, and T15 to turn on. At this time, CK, V2, and VGL are low potentials, P2 is pulled down to a low potential by VGL through T11 and T12, and P1 is pulled down to a low potential by VGL through T2, G n The voltage is maintained at a low level by being pulled down by CK through T4.

[0057] In the touch control stage, V1, VGH, Q1 and Q2 are at high potential, and the corresponding T2, T4, T8, T11, T12 and T15 are turned on; G n-4 , G n+4, CK, VGL, and V2 are low potentials, P2 is maintained at a low potential by VGL through T11 and T12, P1 is maintained at a low potential by VGL through T2, G n T4 is pulled down by CK to maintain a low potential, and the corresponding T1, T3, T5, T6, T7, T9, T10, T13, T14, and T16 are turned off. This stage is the touch stage, which lasts for about 200us, that is, the high potential of Q1 point of a certain level of GIP remains high within 200us, but in general GIP circuits, the leakage of TFT will cause leakage of Q1 point (please refer to Fig.10 , Q1), which will cause G in the subsequent output stage n The output will be lower than that of the previous stage, which may cause the panel to have a dark line problem at a fixed position, resulting in poor display effect. In the GIP circuit of this patent, since Q2 is at a high potential at this stage and T15 is turned on, Q1 always supplements the VGH potential through T15, preventing leakage at the Q1 point, so that the GIP output signal of the subsequent output stage of this level will not be abnormal, solving the problem of dark lines on the display of the general GIP circuit after touch.

[0058] During the output period, V1, CK and Q1 are at high potential, and the corresponding T2, T4, T8, T11, T12 and T16 are turned on; G n-4 , G n+4 , VGL and V2 are at low potential, Q2 is pulled down to low potential by VGL through T16, P2 is maintained at low potential by VGL through T11 and T12, and P1 is maintained at low potential by VGL through T2. At this time, the corresponding T1, T3, T5, T6, T7, T9, T10, T13, T14, and T15 are closed. At this stage, since T4 is open, CK is at high potential, and the output G n The potential of Q1 is high, and the potential of Q1 is increased to 2H by the coupling effect of capacitor C2, which stabilizes and improves G n Output.

[0059] During the pull-down period, G n+4 , V1, and VGH are high potential, and the corresponding T4, T7, T8, and T11 are turned on; V1, G n-4 , CK and VGL are low potential, the initial G n It is pulled down to a low potential by CK through T4, P2 is maintained at a low potential by VGL through T11 and T12, and then Q1 is pulled down to a low potential by VGL through T7. At this time, T2, T4, and 12 are closed, and P1 is pulled up to a high potential by V1 through T8. At this time, the corresponding T3 and T5 are opened, and Q1 and Gn are pulled down to a low potential by VGL through T3 and T5 respectively.

[0060] During the display pull-down period, V1 is at a high potential, corresponding to T8 and T11 being turned on, P1 is maintained at a high potential by V1 through T8, and P2 is maintained at a low potential by VGL through T11. At this time, P1 is at a high potential, T3 and T5 are turned on, Q1 and Gn are maintained at a low potential by VGL, CK is a high-frequency waveform, and Q2 is maintained at a low potential by VGL through T16.

[0061] The above technical solution uses a total of 16 TFTs and 2 capacitors, with T4 outputting Gn and using T14 / T15 / T16 to control the potential of Q2 point, thereby preventing the output signal distortion problem caused by leakage of GIP Q1 point of the GIP circuit in different touch modes, and improving the display image quality and quality of the panel.

[0062] There are many types of transistors. T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 can be thin film transistors, MOS transistors (metal-oxide-semiconductor field-effect transistors MOSFET), junction field-effect transistors, etc.

[0063] Preferably, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 are all thin film transistors (TFT). Thin film transistors are used as switches to drive liquid crystal pixels to achieve the characteristics of high speed, high brightness and high contrast.

[0064] In a preferred embodiment, the GIP circuit is arranged on an In-Cell touch panel. Currently, touch technologies are mainly divided into On-Cell technology and In-Cell technology: On Cell refers to a method of embedding a touch screen between a display screen and a polarizer, that is, a touch sensor is provided on a display panel; In-cell refers to embedding a touch panel function into an array substrate. Thus, the thickness of an In-Cell panel is greatly reduced due to the lack of a touch screen layer.

[0065] In some embodiments, a method for driving a GIP circuit is also provided, which is applied to any of the above-mentioned GIP circuits, including a display stage and a touch stage. It should be noted that the display stage and the touch stage are alternated multiple times within a preset time, and the preset time can be a frame time; of course, in some embodiments, they can be alternated only once within a frame time. Different from the Long V in the background technology; the steps of the touch stage are as follows: During the touch pre-charge period a1, G n-4 Write high potential, V1 write high potential, VGH write high potential, G n+4Write low potential, CK write low potential, VGL write low potential, V2 write low potential; during the touch control voltage stabilization period a2, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK write low potential, VGL write low potential, V2 write low potential; during the touch output period a3, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK write high potential, VGL write low potential, V2 write low potential; during the touch pull-down period a4, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write high potential, CK write low potential, VGL write low potential, V2 write low potential; during the touch pull-down maintenance period a4, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK write high potential, VGL write low potential, V2 write low potential. It should be noted that the display stage includes the following steps: during the display pre-charge period t1, G n-4 Write high potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK write low potential, VGL write low potential, V2 write low potential; during display output period t2, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK write high potential, VGL write low potential, V2 write low potential; during the display pull-down period t3, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write high potential, CK write low potential, VGL write low potential, V2 write low potential; during the display pull-down maintenance period t3, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, write high potential to CK, write low potential to VGL, and write low potential to V2.

[0066] For details, please refer to Figure 3 , Figure 4 and Figure 5 During the touch pre-charge period, the touch pre-charge period a1 works in the same way as the display pre-charge period t1. n-4, V1 and VGH are high potential, and the corresponding T1, T8, T11, and T14 are turned on; VGH charges Q1 and Q2 through T1 and T14, causing Q1 and Q2 to rise to a high potential, and controlling T2, T4, T12, and T15 to turn on. At this time, CK, V2, and VGL are low potentials, P2 is pulled down to a low potential by VGL through T11 and T12, and P1 is pulled down to a low potential by VGL through T2, G n The voltage is maintained at a low level by being pulled down by CK through T4.

[0067] See also Figure 3 , Figure 4 and Figure 6 , during the touch control voltage stabilization period: this working period only exists in the touch control stage, and there is no voltage stabilization period in the display stage. That is, during the touch control voltage stabilization period a2, V1, VGH, Q1 and Q2 are at high potential, and the corresponding T2, T4, T8, T11, T12, and T15 are turned on; G n-4 , G n+4 , CK, VGL, and V2 are low potentials, P2 is maintained at a low potential by VGL through T11 and T12, P1 is maintained at a low potential by VGL through T2, G n T4 is pulled down by CK to maintain a low potential, and the corresponding T1, T3, T5, T6, T7, T9, T10, T13, T14, and T16 are turned off. This stage is the touch voltage stabilization period, and the duration of this stage is about 200us, that is, the high potential of Q1 point of a certain level of GIP remains high within 200us, but in the general GIP circuit, the leakage of TFT will cause leakage of Q1 point (please refer to Fig.10 , Q1), which will cause G in the subsequent output stage n The output will be lower than that of the previous stage, which may cause the panel to have a dark line problem at a fixed position, resulting in poor display effect. In the GIP circuit of this patent, since Q2 is at a high potential at this stage and T15 is turned on, Q1 always supplements the VGH potential through T15, preventing leakage at the Q1 point, so that the GIP output signal of the subsequent output stage of this level will not be abnormal, solving the problem of dark lines on the display of the general GIP circuit after touch.

[0068] See also Figure 3 , Figure 4 and Figure 7 During the touch output period: The display output period t2 works in the same way as the touch output period a3. At this time, V1, CK and Q1 are high potential, and the corresponding T2, T4, T8, T11, T12, and T16 are turned on; G n-4 , G n+4, VGL and V2 are at low potential, Q2 is pulled down to low potential by VGL through T16, P2 is maintained at low potential by VGL through T11 and T12, and P1 is maintained at low potential by VGL through T2. At this time, the corresponding T1, T3, T5, T6, T7, T9, T10, T13, T14, and T15 are closed. At this stage, since T4 is open, CK is at high potential, and the output G n The potential of Q1 is high, and the potential of Q1 is increased to 2H by the coupling effect of capacitor C2, which stabilizes and improves G n Output.

[0069] See also Figure 3 , Figure 4 and Figure 8 During the touch pull-down period: the display pull-down period and the display pull-down maintenance period t3 work in the same manner as the touch pull-down period and the touch pull-down maintenance period a4. That is, in the early stage of t3 and a4, at this time G n+4 , V1, and VGH are high potential, and the corresponding T4, T7, T8, and T11 are turned on; V1, G n-4 , CK and VGL are low potential, the initial G n It is pulled down to a low potential by CK through T4, P2 is maintained at a low potential by VGL through T11 and T12, and then Q1 is pulled down to a low potential by VGL through T7. At this time, T2, T4, and 12 are closed, and P1 is pulled up to a high potential by V1 through T8. At this time, the corresponding T3 and T5 are opened, and Q1 and Gn are pulled down to a low potential by VGL through T3 and T5 respectively.

[0070] See also Figure 3 , Figure 4 and Fig. 9 , the display pull-down period and the display pull-down maintenance period t3 work in the same way as the touch pull-down period and the touch pull-down maintenance period a4. That is, in the later period of t3 and a4, V1 is at a high potential, corresponding to T8 and T11 being turned on, P1 is maintained at a high potential by V1 through T8, and P2 is maintained at a low potential by VGL through T11. At this time, P1 is at a high potential, T3 and T5 are turned on, Q1 and Gn are maintained at a low potential by VGL, CK is a high-frequency waveform, and Q2 is maintained at a low potential by VGL through T16. When using the touch control mode of LongH mode, since the touch control stage will be inserted into the display stage, when using the GIP design, a touch control segment will be inserted between two display segments, so that the Q1 point of the GIP of the second display segment will maintain a high potential for a longer period of time (about 200us). Due to the leakage problem of TFT, the Q1 point of the second display stage will have a large leakage problem, resulting in a large difference between the Q1 points of the first row GIP of the second display stage and the GIP of the first display stage, which may cause a difference in the panel GIP output signal, resulting in the problem of horizontal dark lines on the display. Please refer to Fig.10 The above technical solution uses T14 / T15 / T16 to control the potential of Q2 point, which prevents the output signal distortion problem caused by the leakage of GIP Q1 point of GIP circuit in different touch modes, and improves the display quality of the panel.

[0071] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A GIP circuit, characterized in that: Including transistors: T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16, and capacitors: C1 and C2; The input end of T1 is connected to VGH, the output end of T1 is connected to Q1 node, and the control end of T1 is connected to G n-4 connect; The input end of T2 is connected to the P1 node, the output end of T2 is connected to VGL, and the control end of T2 is connected to the Q1 node; The input end of T3 is connected to the Q1 node, the output end of T3 is connected to VGL, and the control end of T3 is connected to the P1 node; The input end of T4 is connected to CK, and the output end of T4 is connected to G n Connecting, the control end of T4 is connected to the Q1 node; The input of T5 is connected to G n The output end of T5 is connected to VGL, and the control end of T5 is connected to the P1 node; The input of T6 is connected to G n The output end of T6 is connected to VGL, and the control end of T6 is connected to the P2 node; The input end of T7 is connected to the Q1 node, the output end of T7 is connected to VGL, and the control end of T7 is connected to G n+4 connect; The input end of T8 is connected to V1, the output end of T8 is connected to the P1 node, and the control end of T8 is connected to V1; The input end of T9 is connected to V2, the output end of T9 is connected to the P2 node, and the control end of T9 is connected to V2; The input end of T10 is connected to the P1 node, the output end of T10 is connected to VGL, and the control end of T10 is connected to V2; The input end of T11 is connected to the P2 node, the output end of T11 is connected to VGL, and the control end of T11 is connected to V1; The input end of T12 is connected to the P2 node, the output end of T12 is connected to VGL, and the control end of T12 is connected to the Q1 node; The input end of T13 is connected to the Q1 node, the output end of T13 is connected to VGL, and the control end of T13 is connected to the P2 node; The input end of T14 is connected to VGH, the output end of T14 is connected to Q2 node, and the control end of T14 is connected to G n-4 connect; The input end of T15 is connected to VGH, the output end of T15 is connected to the Q1 node, and the control end of T15 is connected to the Q2 node; The input end of T16 is connected to the Q2 node, the output end of T16 is connected to VGL, and the control end of T16 is connected to CK; One plate of C1 is connected to the Q1 node, and the other plate of C1 is connected to the G n connect; The C2 is connected to the Q2 node.

2. A GIP circuit according to claim 1, characterized in that: One plate of C2 is connected to the Q2 node, and the other plate of C2 is grounded.

3. A GIP circuit according to claim 1 or 2, characterized in that: T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 are all thin film transistors.

4. A GIP circuit according to claim 1, characterized in that: The T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 are all thin film transistors, and the T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15 and T16 are arranged on the display panel.

5. A GIP circuit according to claim 4, characterized in that: The display panel is an In-Cell touch panel.

6. A driving method of a GIP circuit, characterized in that: A GIP circuit as claimed in any one of claims 1 to 5, comprising a display stage and a touch stage, wherein the steps of the touch stage are as follows: During touch precharge a1, G n-4 Write high potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK writes low potential, VGL writes low potential, V2 writes low potential; During the touch voltage regulation period a2, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK writes low potential, VGL writes low potential, V2 writes low potential; During touch output a3, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, write high potential to CK, write low potential to VGL, and write low potential to V2; During touch pull-down a4, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write high potential, write CK to low potential, write VGL to low potential, and write V2 to low potential; During the touch pull-down maintenance period a4, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, write high potential to CK, write low potential to VGL, and write low potential to V2.

7. A driving method for a GIP circuit according to claim 6, characterized in that: The display stage includes the steps of: During the display precharge period t1, G n-4 Write high potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, CK writes low potential, VGL writes low potential, V2 writes low potential; During the display output period t2, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, write high potential to CK, write low potential to VGL, and write low potential to V2; During the display pull-down period t3, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write high potential, write CK to low potential, write VGL to low potential, and write V2 to low potential; During the display pull-down maintenance period t3, G n-4 Write low potential, V1 write high potential, VGH write high potential, G n+4 Write low potential, write high potential to CK, write low potential to VGL, and write low potential to V2.

8. A driving method for a GIP circuit according to claim 6, characterized in that: The display phase and the touch control phase are cycled multiple times within a preset time.

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