A built-in panel structure and manufacturing method thereof

Abstract

The present invention discloses an embedded panel structure and a manufacturing method thereof: manufacturing a first light-transmitting conductive layer and a gate metal layer, manufacturing a first insulating layer; removing the first insulating layer on the substrate area, removing the upper part of the first insulating layer on the light-transmitting capacitor area; removing the first light-transmitting conductive layer and the gate metal layer; ashing the first insulating layer, etching the gate metal layer, and removing the first insulating layer; manufacturing a second insulating layer; manufacturing an active layer; manufacturing a second light-transmitting conductive layer and a source-drain metal layer, and manufacturing a third insulating layer; removing the third insulating layer on the substrate area and above the middle of the active layer; removing the upper part of the third insulating layer on the light-transmitting capacitor area; removing the second light-transmitting conductive layer and the source-drain metal layer; removing the third insulating layer; etching the source-drain metal layer; and removing the third insulating layer. By adding a light-transmitting capacitor area, the light-emitting layer does not need to have a blank avoidance area, and light is emitted directly from the light-transmitting capacitor area, thereby reducing the area of ​​a single pixel and improving the aperture ratio of the display area.

Description

Technical Field

[0001] The present invention relates to the field of touch display screens, and in particular to an embedded panel structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of display technology, various new technologies are constantly emerging. Transparent display technology has attracted more and more attention due to its transparent display panel characteristics and unique applications. Thin and transparent display is the trend of future display development.

[0003] Currently, the touch technologies used in AMOLED panels are mainly divided into three types: out-cell, in-cell, and on-cell. Out-cell touch technology is dominated by touch panel manufacturers and can be divided into glass-based and thin-film approaches. This technology places the touch sensor between the cover glass and the display module. However, its disadvantage is its thickness, which is inconsistent with the trend of thinner and lighter displays.

[0004] In-Cell embeds the touch module into the AMOLED panel. On-Cell refers to a method where the touch screen is embedded between the display and the polarizer, meaning the touch sensor is installed on the display panel. In-Cell saves on glass and lamination costs, resulting in a lightweight module with high light transmittance, which better meets the quality requirements of the display panel. However, when the touch sensor is embedded into the pixel, the corresponding touch integrated circuit must also be embedded there. Otherwise, it is easy to cause erroneous touch sensing signals or excessive noise, and the manufacturing process is extremely complex and difficult. The organic layers in OLEDs are all deposited using a vapor deposition method, which is technically demanding and difficult, resulting in a low yield. Adding another layer of touch IC to the vapor deposition structure will inevitably further reduce the yield, so the current embedded touch technology in OLED panels still needs a breakthrough.

[0005] The aperture ratio refers to the ratio between the area of ​​the light-transmitting portion of each sub-pixel, excluding the wiring and transistor sections (usually hidden by a black matrix) and the overall area of ​​each sub-pixel. The higher the aperture ratio, the more efficient the light transmission. When light is emitted through the backlight, not all of it can pass through the panel. For example, some areas of light pass through the signal traces for the LCD source and gate driver chips, the TFTs themselves, and the storage capacitors used to store voltage. These areas are not only not completely transparent, but also because the light passing through them is not controlled by voltage and cannot display the correct grayscale, they must be shielded by a black matrix to prevent interference with other light-transmitting areas. The ratio of the effective light-transmitting area to the total area is called the aperture ratio. Summary of the Invention

[0006] Therefore, it is necessary to provide an embedded panel structure and a manufacturing method thereof to increase the aperture ratio of the panel and reduce the thickness of the panel.

[0007] To achieve the above objectives, the present application provides a method for manufacturing an embedded panel structure, comprising the steps of:

[0008] The substrate is divided into a light-transmitting capacitor area, a TFT area and a substrate area;

[0009] forming a first light-transmitting conductive layer and a gate metal layer in sequence on the substrate, and forming a first insulating layer on the gate metal layer;

[0010] exposing and developing to remove the first insulating layer on the substrate area, and removing an upper portion of the first insulating layer on the light-transmitting capacitor area;

[0011] Etching and removing the first light-transmitting conductive layer and the gate metal layer on the substrate region;

[0012] removing the remaining first insulating layer on the light-transmitting capacitor region by an ashing process, and etching the gate metal layer on the light-transmitting capacitor region;

[0013] removing the first insulating layer located on the TFT area;

[0014] forming a second insulating layer; and forming an active layer on the second insulating layer, wherein the active layer is located above the gate metal layer;

[0015] A second light-transmitting conductive layer and a source-drain metal layer are sequentially formed, and a third insulating layer is formed on the source-drain metal layer;

[0016] Exposing and developing to remove the substrate region and the third insulating layer above the middle portion of the active layer; and removing the upper portion of the third insulating layer on the light-transmitting capacitor region;

[0017] Etching and removing the second light-transmitting conductive layer and the source-drain metal layer on the substrate region and the middle portion of the active layer;

[0018] removing the remaining third insulating layer on the second light-transmitting conductive layer in the light-transmitting capacitor region by an ashing process;

[0019] Etching the source and drain metal layers on the light-transmitting capacitor region to form a source metal layer and a drain metal layer located on both sides of the active layer;

[0020] The third insulating layer located on the TFT region is removed.

[0021] Furthermore, the light-transmitting capacitor area is connected to the TFT area.

[0022] Furthermore, a half-tone mask is used to expose and develop the first insulating layer and the third insulating layer;

[0023] The half-color mask includes: a first light-transmitting area, a second light-transmitting area and a third light-transmitting area; the transmittance of the first light-transmitting area is 100%, the transmittance of the third light-transmitting area is 0%, and the transmittance of the second light-transmitting area is between the transmittance of the first light-transmitting area and the transmittance of the third light-transmitting area.

[0024] Furthermore, the method further comprises the steps of:

[0025] forming a fourth insulating layer; and forming a first through hole on the fourth insulating layer, wherein the first through hole has the source metal layer or the drain metal layer as a bottom;

[0026] Making a flat layer, and making a second through hole on the flat layer, wherein the second through hole is electrically connected to the first through hole;

[0027] Making a light-transmitting anode, wherein the light-transmitting anode is connected to the source metal layer or the drain metal layer through a first through hole and a second through hole;

[0028] A pixel definition layer is fabricated, and the pixel definition layer is exposed and developed to form a third through hole with the light-transmitting anode as a bottom, wherein the third through hole is located in the light-transmitting capacitor region;

[0029] A light-emitting layer is manufactured, and the light-emitting layer is placed in the second through hole; and a cathode is manufactured on the light-emitting layer and the pixel definition layer.

[0030] Furthermore, before the step of sequentially forming the first light-transmitting conductive layer and the gate metal layer, the method further includes the following steps:

[0031] Manufacturing a plurality of first conductive film layers on a substrate, wherein the plurality of first conductive film layer arrays are arranged on the substrate;

[0032] A fifth insulating layer is manufactured, where the fifth insulating layer covers the first conductive film layers.

[0033] Furthermore, before the step of sequentially forming the first light-transmitting conductive layer and the gate metal layer, the method further includes the following steps:

[0034] Manufacturing a plurality of second conductive film layers on a substrate, wherein the plurality of second conductive film layer arrays are arranged on the substrate;

[0035] forming a sixth insulating layer, and removing the sixth insulating layer located between the second conductive film layers;

[0036] A third conductive film layer is formed, and a seventh insulating layer is formed on the third conductive film layer.

[0037] The present application also provides an in-cell panel structure, the in-cell panel structure being manufactured by any of the embodiments of the method for manufacturing an in-cell panel structure described above, wherein a first light-transmitting conductive layer and a gate metal layer are sequentially provided on a substrate, the gate metal layer being located on one side of the first light-transmitting conductive layer, a TFT region and a light-transmitting capacitor region with the gate metal layer being formed on the first light-transmitting conductive layer, and an area outside the first light-transmitting conductive layer being a substrate region; a second insulating layer is provided on the TFT region, the light-transmitting capacitor region, and the substrate region, and an active layer is provided on the second insulating layer, the active layer being located above the gate metal layer;

[0038] A second light-transmitting conductive layer is also provided above the active layer. The second light-transmitting conductive layer is placed on both sides of the active layer, and the second light-transmitting conductive layers on both sides overlap the active layer. The side of the second light-transmitting conductive layer close to the light-transmitting capacitor area is located above the first light-transmitting conductive layer. A source metal layer and a drain metal layer are provided on the second light-transmitting conductive layer. The source metal layer and the drain metal layer are placed in the TFT area and overlap the active layer through the second light-transmitting conductive layer on one side.

[0039] Furthermore, it also includes: a fourth insulating layer, a planar layer, a light-transmitting anode, a pixel definition layer, a light-emitting layer and a cathode;

[0040] The fourth insulating layer is disposed on the second insulating layer, the second light-transmitting conductive layer, the active layer source metal layer, and the drain metal layer, and a first through hole with the source metal layer or the drain metal layer as a bottom is further disposed on the fourth insulating layer; the flat layer is disposed on the fourth insulating layer, and a second through hole is further disposed on the flat layer, the first through hole being electrically connected to the second through hole;

[0041] A light-transmitting anode is provided on the flat layer, and the light-transmitting anode is connected to the source metal layer or the drain metal layer through a first through hole and a second through hole; a pixel definition layer is provided on the light-transmitting anode and the flat layer, and a third through hole is provided in the pixel definition layer with the light-transmitting anode as the bottom; a light-emitting layer is provided in the second through hole, and a cathode is provided on the light-emitting layer and the pixel definition layer.

[0042] Furthermore, the third through hole is located above the second light-transmitting conductive layer.

[0043] Furthermore, it also includes: a touch structure; the touch structure is placed between the first light-transmitting conductive layer and the substrate.

[0044] Unlike existing technologies, this solution embeds touch functionality within the display panel by directly placing a touch-sensitive layer on the substrate. Compared to external, independent touch-sensitive film or glass, this reduces panel thickness, lowers costs, and increases panel transmittance. Furthermore, by adding a transparent capacitor area, the light-emitting layer can eliminate the need for a blank escape zone. Light can be emitted directly from the transparent capacitor area, thereby reducing the area of ​​a single pixel and further increasing the display area aperture ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a panel structure with blank areas;

[0046] Figure 2 is a positional relationship diagram of the light-transmitting capacitor area and the light-emitting layer;

[0047] Figure 3 is a positional relationship diagram of the light-transmitting capacitor area, TFT area, and substrate area;

[0048] Figure 4 is a structural diagram of the first conductive film layer;

[0049] Figure 5 is a structural diagram of the fifth insulating layer;

[0050] Figure 6 is a structural diagram of the first light-transmitting conductive layer and the gate metal layer;

[0051] Figure 7 is a structural diagram of the second insulating layer;

[0052] Figure 8 is the active layer structure diagram;

[0053] Figure 9 A structural diagram of the source metal layer, the drain metal layer and the second light-transmitting conductive layer;

[0054] Figure 10 is a structural diagram of the fourth insulating layer and the first through hole;

[0055] Figure 11 A structural diagram of the first through hole, the planar layer, and the second through hole;

[0056] Figure 12 is a structural diagram of the light-transmitting anode;

[0057] Figure 13 The pixel definition layer and the third through hole structure diagram;

[0058] Figure 14 is a structural diagram of the light-emitting layer;

[0059] Figure 15 is the cathode structure diagram;

[0060] Figure 16 is a structural diagram of the second conductive film, the sixth insulating layer, the third conductive film layer and the seventh insulating layer;

[0061] Figure 17 exposing and developing the first insulating layer through a half-tone mask;

[0062] Figure 18 ashing the first insulating layer on the light-transmitting capacitor region;

[0063] Figure 19 The gate metal layer on the light-transmitting capacitor area is etched.

[0064] Description of reference numerals:

[0065] 1. Substrate; 2. First light-transmitting conductive layer; 3. Gate metal layer; 4. Second insulating layer; 5. Second light-transmitting conductive layer; 6. Source / drain metal layer; 7. Fourth insulating layer; 8. First through-hole; 9. Planarization layer; 10. Second through-hole; 11. Light-transmitting anode; 12. Pixel definition layer; 13. Third through-hole; 14. Light-emitting layer; 15. Cathode; 16. Active layer; 17. First insulating layer.

[0066] 61. Source metal layer; 62. Drain metal layer;

[0067] 20. First conductive film layer; 21. Fifth insulating layer; 22. Second conductive film layer; 23. Sixth insulating layer; 24. Third conductive film layer; 25. Seventh insulating layer;

[0068] 100, light-transmitting capacitor area; 200, TFT area; 300, substrate area. DETAILED DESCRIPTION

[0069] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0070] See also Figures 1 to 19 In this application, a method for manufacturing an embedded panel structure is provided, comprising the steps of: dividing a substrate 1 into a light-transmitting capacitor region 100, a TFT region 200, and a substrate region 300; refer to Figures 17 to 19 ,exist Figures 17 to 19 The etching methods for the gate metal layer 3 and the first light-transmitting conductive layer are listed in the same way. The same is true for the manufacturing methods of the second light-transmitting conductive layer and the source-drain metal layer. It is only necessary to replace the first light-transmitting conductive layer with the second light-transmitting conductive layer and the gate metal layer with the source-drain metal layer. Figures 6 to 9, on the substrate 1, a first light-transmitting conductive layer 2 and a gate metal layer 3 are sequentially formed on the entire surface of the panel, and a first insulating layer 17 is formed on the gate metal layer 3; the first insulating layer 17 on the substrate area 300 is removed by exposure and development, and the upper half of the first insulating layer 17 on the light-transmitting capacitor area 100 is removed; the first light-transmitting conductive layer 2 and the gate metal layer 3 on the substrate area 300 are etched away, and at this time, etching can be performed once or twice according to the film material; the remaining first insulating layer 17 on the light-transmitting capacitor area 100 is removed by ashing treatment, the gate metal layer 3 on the light-transmitting capacitor area 100 is etched, and the first insulating layer 17 located on the TFT area 200 is removed; a second insulating layer 4 is formed on the entire surface of the panel; and an active layer 16 is formed on the second insulating layer 4, and the active layer 16 is located on the gate metal layer 3 The method further comprises the steps of: forming a second light-transmitting conductive layer 5 and a source-drain metal layer 6 on the entire panel, and forming a third insulating layer on the source-drain metal layer 6; exposing and developing to remove the third insulating layer above the substrate area 300 and the middle of the active layer 16; and removing the upper half of the third insulating layer on the light-transmitting capacitor area 100; etching to remove the second light-transmitting conductive layer 5 and the source-drain metal layer 6 on the substrate area 300 and the middle of the active layer 16. At this time, etching can be performed once or twice according to the film material; removing the remaining third insulating layer on the second light-transmitting conductive layer 5 in the light-transmitting capacitor area 100 by ashing treatment; etching the source-drain metal layer 6 on the light-transmitting capacitor area 100 to form a source metal layer 61 and a drain metal layer 62 on both sides of the active layer 16; and removing the third insulating layer on the TFT area 200.

[0071] It should be noted that the panel is an OLED panel. The first light-transmitting conductive layer 2 and the second light-transmitting conductive layer 5 are made of transparent conductive films such as ITO, ZnO, SnO2, or other oxides, carbon nanotubes, and graphene, and are primarily used to allow light in the light-emitting layer 14 to pass through the capacitor. The light-transmitting capacitor region 100 and the TFT region 200 are electrically connected. The first light-transmitting conductive layer 2 and the second light-transmitting conductive layer 5 on the TFT region 200 extend onto the light-transmitting capacitor region 100, and the first light-transmitting conductive layer 2 and the second light-transmitting layer form a capacitor in the light-transmitting capacitor region 100. The gate metal layer 3 can be made of a metal with excellent conductivity, such as aluminum, molybdenum, titanium, nickel, copper, silver, or chromium, and can also be an alloy. It should also be noted that, by performing exposure and development using a grayscale mask, the first insulating layer 17 located in the substrate area 300 is removed, and at the same time, the first insulating layer 17 located in the upper half of the light-transmitting capacitor area 100 is removed, that is, the first insulating layer 17 located on the light-transmitting capacitor area 100 is thinned; due to the difference in exposure amount, the first insulating layer 17 located in the light-transmitting capacitor area 100 can be removed by ashing treatment; and then etching is performed. During etching, the gate metal layer 3 of the TFT area 200 is protected by the first insulating layer 17 and will not be etched away. However, due to the thinning by etching, the gate metal layer 3 located on the light-transmitting capacitor area 100 will be etched away, revealing the first light-transmitting conductive layer 2. Similarly, the method for manufacturing the source and drain metal layer 6 and the second light-transmitting conductive layer 5 is the same; the second light-transmitting conductive layer 5, the source and drain metal layer 6 and the third insulating layer are sequentially manufactured in the TFT area 200 and the light-transmitting capacitor area 100, and the third insulating layer above the substrate area 300 and the middle part of the active layer 16 is removed by exposure and development through a grayscale mask; and the upper part of the third insulating layer on the light-transmitting capacitor area 100 is removed; the second light-transmitting conductive layer 5 and the source and drain metal layer 6 on the substrate area 300 and the middle part of the active layer 16 are etched away; the remaining third insulating layer on the second light-transmitting conductive layer 5 in the light-transmitting capacitor area 100 is removed by ashing treatment; the source and drain metal layer 6 on the light-transmitting capacitor area 100 is etched to form a source metal layer 61 and a drain metal layer 62 located on both sides of the active layer 16.

[0072] It should also be noted that the source and drain metal layer 6 etches away part of the source and drain metal layer 6 located on the middle part of the active layer 16 and the source and drain metal layer 6 located on the light-transmitting capacitor area 100, thereby obtaining a source metal layer 61 and a drain metal layer 62. Specifically, the source metal layer 61 and the drain metal layer 62 are placed in the TFT area 200 and are located on both sides of the active layer 16. It should also be noted that the light-emitting layer 14 is placed in the light-transmitting capacitor area 100, that is, above the first light-transmitting conductive layer 2 and the second light-transmitting conductive layer 5.

[0073] The material used for the second insulating layer 4 is SiO x 、SiN x , aluminum oxide or titanium oxide, etc.; the material of the active layer 16 can be polysilicon, oxide semiconductor, graphene, carbon nanotube or organic semiconductor, etc.;

[0074] Different from the existing technology, the above technical solution adds a light-transmitting capacitor area 100, so that the light-emitting layer 14 does not need to be provided with a blank avoidance area, that is, light can be emitted directly from the light-transmitting capacitor area 100, thereby reducing the area of ​​a single pixel and further improving the aperture ratio of the display area.

[0075] See also Figure 1 In traditional bottom-emitting panels, since thin-film transistors and storage capacitors are made of metal and cannot transmit light, a separate avoidance area (blank area) needs to be set up in the panel to allow the light-emitting layer 14 to pass through the panel normally. However, this will inevitably waste the limited panel area and reduce the aperture ratio. Figure 2 In this application, a transparent storage capacitor is prepared, which eliminates the need for a separate avoidance zone in the panel, narrows the occupied area of ​​a single pixel, and increases the pixel aperture ratio. More pixels can be placed under the same panel size, which is more conducive to the design of high-resolution panels.

[0076] See also Figure 17 In the left figure, in certain embodiments, a half-tone mask is used to expose and develop the first insulating layer 17 and the third insulating layer. The half-tone mask includes a first light-transmitting region, a second light-transmitting region, and a third light-transmitting region. The transmittance of the first light-transmitting region is 100%, the transmittance of the third light-transmitting region is 0%, and the transmittance of the second light-transmitting region is between the transmittances of the first light-transmitting region and the third light-transmitting region. It should be noted that the transmittance of the second light-transmitting region is 50%. That is, in this embodiment, the half-tone mask used is medium, divided into a first half-tone mask and a second half-tone mask. The first half-tone mask is used to expose and develop the first insulating layer 17; the second half-tone mask is used to expose and develop the third insulating layer. The first, second, and third light-transmitting regions are arranged in a different order on the first half-tone mask than on the second half-tone mask.

[0077] Specifically, in the first half-tone mask, a first light-transmitting region is provided on the substrate region 300, a second light-transmitting region is provided on the light-transmitting capacitor region 100, and a third light-transmitting region is provided on the TFT region 200. In the second half-tone mask, the substrate region 300 and the area above the middle portion of the active layer 16 constitute the first light-transmitting region, the light-transmitting capacitor region 100 constitutes the second light-transmitting region, and the area above the middle portion of the TFT region 200, excluding the area above the middle portion of the active layer 16, constitutes the third light-transmitting region. Of course, the transmittances of the third and first light-transmitting regions can be interchanged, i.e., using the opposite developer solution as in the above embodiment. The provision of the light-transmitting capacitor region 100 eliminates the need for a blank avoidance region in the light-emitting layer 14, allowing light to be emitted directly from the light-transmitting capacitor region 100. This reduces the area of ​​a single pixel and further improves the display area aperture ratio.

[0078] See also Figures 10 to 15 In some embodiments, the present invention further includes the following steps: forming a fourth insulating layer 7; forming a first through hole 8 on the fourth insulating layer 7, wherein the first through hole 8 has the source metal layer 61 or the drain metal layer 62 as a bottom; forming a planar layer 9, and forming a second through hole 10 on the planar layer 9, wherein the second through hole 10 is electrically connected to the first through hole 8; forming a light-transmitting anode 11, wherein the light-transmitting anode 11 is connected to the source metal layer 61 or the drain metal layer 62 through the first through hole 8 and the second through hole 10; forming a pixel definition layer 12, and exposing and developing the pixel definition layer 12 to form a third through hole 13 with the light-transmitting anode 11 as a bottom, wherein the third through hole 13 is located in the light-transmitting capacitor region 100; forming a light-emitting layer 14, wherein the light-emitting layer 14 is located in the second through hole 10; and forming a cathode 15 on the light-emitting layer 14 and the pixel definition layer 12.

[0079] It should be noted that, in this embodiment, the entire surface of the fourth insulating layer 7 covers the TFT region 200, the transparent capacitor region 100, and the substrate region 300, and the first through hole 8 is away from the transparent capacitor region 100; it should be further noted that the second through hole 10 is connected to the first through hole 8, and the two share a common bottom. The fourth insulating layer 7 is made of materials such as SiOx, SiNx, aluminum oxide, or titanium oxide; the flat layer 9 is an organic insulating layer, SiOx, SiNx, aluminum oxide, or titanium oxide. A transparent anode 11 is made on the flat layer 9. The material of the transparent anode 11 can be ITO, graphene, carbon nanotubes, etc. The anode is connected to the drain metal layer 62 through the first through hole 8 and the second through hole 10; that is, the drain metal layer 62 is away from the transparent capacitor region 100. The third through hole 13 is an RGB pattern opening, and exposes the upper surface of the transparent anode 11. The RGB organic light-emitting layer 14 is evaporated in the third through hole 13 , including a hole injection layer HIL, a hole transport layer HTL, an organic light-emitting layer 14EM, an electron transport layer ETL, and an electron injection layer EIL; and a highly reflective metal layer, i.e., a cathode 15 , is continuously evaporated.

[0080] See also Figures 4 and 5 In some embodiments, before the steps of sequentially manufacturing the first light-transmitting conductive layer 2 and the gate metal layer 3, the method further includes the steps of: manufacturing a touch structure; the touch structure may adopt a self-capacitive touch structure, a mutual-capacitive touch structure, a projected capacitive touch structure, a surface capacitive touch structure or an inductive capacitive touch structure, etc.

[0081] It should be further explained that in the self-capacitive touch structure, a plurality of first conductive film layers 20 are formed on the substrate 1, and the plurality of first conductive film layers 20 are arranged in an array on the substrate 1; a fifth insulating layer 21 is formed, and the fifth insulating layer 21 covers the plurality of first conductive film layers 20. The first conductive film layer 20 formed on the substrate 1 cooperates with the driver chip to realize the touch function. The first conductive film can be selected from oxide transparent conductive films such as ITO, ZnO, SnO2, or carbon-based transparent conductive films such as carbon nanotubes and graphene, or silver nanomaterials, metal grids, conductive polymers, etc. The entire fifth insulating layer 21 is covered on the first conductive film layer 20 to isolate the touch unit from the TFT unit above it to prevent parasitic capacitance from affecting each other. The material can be selected from organic insulating layers, SiOx, SiNx, aluminum oxide, titanium oxide, etc.

[0082] See also Figure 16In the mutual capacitive touch structure, before the steps of sequentially forming the first light-transmitting conductive layer 2 and the gate metal layer 3, the steps further include: forming a plurality of second conductive film layers 22 on the substrate 1, wherein the plurality of second conductive film layers 22 are arranged in an array on the substrate 1; forming a sixth insulating layer 23, and removing the sixth insulating layer 23 located between the second conductive film layers 22; forming a third conductive film layer 24, and forming a seventh insulating layer 25 on the third conductive film layer 24.

[0083] See also Figure 3 In the present application, a first light-transmitting conductive layer 2 and a gate metal layer 3 are sequentially provided on the substrate 1. The gate metal layer 3 is placed on one side of the first light-transmitting conductive layer 2. A TFT region 200 and a light-transmitting capacitor region 100 with the gate metal layer 3 are formed on the first light-transmitting conductive layer 2. The area outside the first light-transmitting conductive layer 2 is the substrate region 300. A second insulating layer 4 is provided on the TFT region 200, the light-transmitting capacitor region 100, and the substrate region 300. An active layer 16 is provided on the second insulating layer 4. The active layer 16 is located above the gate metal layer 3. A second light-transmitting conductive layer 5 is also disposed above the active layer 16. The second light-transmitting conductive layer 5 is positioned on both sides of the active layer 16, overlapping the active layer 16. The side of the second light-transmitting conductive layer 5 closest to the light-transmitting capacitor region 100 is positioned above the first light-transmitting conductive layer 2. A source metal layer 61 and a drain metal layer 62 are disposed on the second light-transmitting conductive layer 5. The source metal layer 61 and the drain metal layer 62 are positioned in the TFT region 200 and overlap the active layer 16 through the second light-transmitting conductive layer 5 on one side. The third through hole 13 is disposed above the second light-transmitting conductive layer 5.

[0084] It should be noted that the panel is an OLED panel. The first light-transmitting conductive layer 2 and the second light-transmitting conductive layer 5 are made of transparent conductive films such as ITO, ZnO, SnO2, or other oxides, carbon nanotubes, and graphene, and are primarily used to allow light in the light-emitting layer 14 to pass through the capacitor. The light-transmitting capacitor region 100 and the TFT region 200 are electrically connected. The first light-transmitting conductive layer 2 and the second light-transmitting conductive layer 5 on the TFT region 200 extend onto the light-transmitting capacitor region 100, and the first light-transmitting conductive layer 2 and the second light-transmitting layer form a capacitor in the light-transmitting capacitor region 100. The gate metal region is located only in the TFT region 200. The gate metal layer 3 can be made of a highly conductive metal such as aluminum, molybdenum, titanium, nickel, copper, silver, or chromium, and may also be an alloy.

[0085] It should also be noted that the source and drain metal layer 6 etches away part of the source and drain metal layer 6 located on the middle part of the active layer 16 and the source and drain metal layer 6 located on the light-transmitting capacitor area 100, thereby obtaining a source metal layer 61 and a drain metal layer 62. Specifically, the source metal layer 61 and the drain metal layer 62 are placed in the TFT area 200 and are located on both sides of the active layer 16. It should also be noted that the light-emitting layer 14 is placed in the light-transmitting capacitor area 100, that is, above the first light-transmitting conductive layer 2 and the second light-transmitting conductive layer 5.

[0086] The material used for the second insulating layer 4 is SiO x 、SiN x , aluminum oxide or titanium oxide, etc.; the material of the active layer 16 can be polysilicon, oxide semiconductor, graphene, carbon nanotube or organic semiconductor, etc.; different from the existing technology, the above technical solution adds a light-transmitting capacitor area 100, so that the light-emitting layer 14 does not need to be provided with a blank avoidance area, that is, light can be emitted directly from the light-transmitting capacitor area 100, thereby reducing the area of ​​a single pixel and further improving the aperture ratio of the display area.

[0087] See also Figures 1 to 2 In traditional bottom-emitting panels, thin-film transistors and storage capacitors are made of metal, which is not transparent. Therefore, a separate avoidance zone (blank area) is required in the panel to allow the light-emitting layer 14 to pass through the panel. However, this inevitably wastes the limited panel area and reduces the aperture ratio. However, the present application has fabricated a transparent storage capacitor, eliminating the need for a separate avoidance zone in the panel. This reduces the area occupied by a single pixel and increases the pixel aperture ratio. This allows for more pixels to be placed within the same panel size, further facilitating the design of high-resolution panels.

[0088] In some embodiments, the present invention further includes: a fourth insulating layer 7, a planar layer 9, a light-transmitting anode 11, a pixel definition layer 12, a light-emitting layer 14, and a cathode 15; the fourth insulating layer 7 is disposed on the second insulating layer 4, the second light-transmitting conductive layer 5, the active layer 16, the source metal layer 61, and the drain metal layer 62, and a first through hole 8 with the source metal layer 61 or the drain metal layer 62 as the bottom is further disposed on the fourth insulating layer 7; the planar layer 9 is disposed on the fourth insulating layer 7, and a second through hole 10 is further disposed on the planar layer 9. , the first through hole is connected to the second through hole 10; a transparent anode 11 is provided on the flat layer 9, and the transparent anode 11 is connected to the source metal layer 61 or the drain metal layer 62 through the first through hole 8 and the second through hole 10; a pixel definition layer 12 is provided on the transparent anode 11 and the flat layer 9, and a third through hole 13 is provided on the pixel definition layer 12 with the transparent anode 11 as the bottom; a light-emitting layer 14 is provided in the second through hole 10, and a cathode 15 is provided on the light-emitting layer 14 and the pixel definition layer 12.

[0089] It should be noted that, in this embodiment, the entire surface of the fourth insulating layer 7 is provided on the TFT region 200, the light-transmitting capacitor region 100, and the substrate region 300, and the first through hole 8 is away from the light-transmitting capacitor region 100; it should be further noted that the second through hole 10 is connected to the first through hole 8, and the two share a common bottom. The fourth insulating layer 7 is made of materials such as SiOx, SiNx, aluminum oxide, or titanium oxide; the flat layer 9 is an organic insulating layer, SiOx, SiNx, aluminum oxide, or titanium oxide. A light-transmitting anode 11 is provided on the flat layer 9. The material of the light-transmitting anode 11 can be ITO, graphene, carbon nanotubes, etc. The anode is connected to the drain metal layer 62 through the first through hole 8 and the second through hole 10; that is, the drain metal layer 62 is away from the light-transmitting capacitor region 100. The third through hole 13 is an RGB pattern opening, and exposes the upper surface of the light-transmitting anode 11. The RGB organic light-emitting layer 14 is evaporated in the third through hole 13 , including a hole injection layer HIL, a hole transport layer HTL, an organic light-emitting layer 14EM, an electron transport layer ETL, and an electron injection layer EIL; and a highly reflective metal layer, i.e., a cathode 15 , is continuously evaporated.

[0090] See also Figure 5 and Figure 16In some embodiments, it further includes: a touch structure; the touch structure is placed between the first light-transmitting conductive layer 2 and the substrate 1. It should be further explained that the touch structure can be a self-capacitive touch structure, a mutual-capacitive touch structure, a projected capacitive touch, a surface-capacitive touch or an inductive capacitive touch, etc. Specifically, in the self-capacitive touch structure: between the first light-transmitting conductive layer 2 and the substrate 1, it also includes: a first conductive film layer 20 and a fifth insulating layer 21; there are multiple first conductive film layers 20, and the multiple first conductive film layers 20 are arrayed on the substrate 1; the fifth insulating layer 21 covers the multiple first conductive film layers 20. The first conductive film layer 20 formed on the substrate 1 cooperates with the driver chip to realize the touch function. The first conductive film can be an oxide transparent conductive film such as ITO, ZnO, SnO2, or a carbon-based transparent conductive film such as carbon nanotubes, graphene, or a silver nanomaterial, a metal grid, a conductive polymer, etc. The entire surface of the fifth insulating layer 21 is covered on the first conductive film layer 20 to isolate the touch unit from the TFT unit thereon to avoid mutual influence of parasitic capacitance. The material can be organic insulating layer, SiOx, SiNx, aluminum oxide, titanium oxide, etc.

[0091] In the mutual capacitive touch structure: between the first light-transmitting conductive layer 2 and the substrate 1, there are also: a second conductive film 22 layer, a sixth insulating layer 23 and a seventh insulating layer 25; there are multiple second conductive film 22 layers, and multiple second conductive film 22 layers are arrayed on the substrate 1; the sixth insulating layer 23 is placed on the second conductive film 22 layer, and each second conductive film 22 layer is covered by the sixth insulating layer 23, and there is a gap between two adjacent sixth insulating layers 23; the third conductive film layer 24 is placed on the substrate and the sixth insulating layer 23, and the seventh insulating layer 25 is made on the third conductive film layer 24.

[0092] It should be noted that although the above embodiments have been described herein, this does not limit the scope of patent protection of the present invention. Therefore, based on the innovative concept of the present invention, changes and modifications to the embodiments described herein, or equivalent structural or equivalent process transformations made using the contents of the present invention's specification and drawings, and direct or indirect application of the above technical solutions to other related technical fields, are all included in the scope of patent protection of the present invention.

Claims

1. A method for manufacturing an embedded panel structure, characterized in that: Includes steps: The substrate is divided into a light-transmitting capacitor region, a TFT region and a substrate region; A first light-transmitting conductive layer and a gate metal layer are sequentially formed on the substrate, and a first insulating layer is formed on the gate metal layer; Exposing and developing to remove the first insulating layer on the substrate region, and removing an upper portion of the first insulating layer on the light-transmitting capacitor region; Etching and removing the first light-transmitting conductive layer and the gate metal layer on the substrate region; Removing the remaining first insulating layer on the light-transmitting capacitor region by ashing, and etching the gate metal layer on the light-transmitting capacitor region; removing the first insulating layer located on the TFT region; Manufacturing a second insulating layer; and manufacturing an active layer on the second insulating layer, wherein the active layer is located above the gate metal layer; A second light-transmitting conductive layer and a source-drain metal layer are sequentially formed, and a third insulating layer is formed on the source-drain metal layer; Exposing and developing to remove the substrate region and the third insulating layer above the middle portion of the active layer; and removing the upper portion of the third insulating layer on the light-transmitting capacitor region; Etching and removing the second light-transmitting conductive layer and the source-drain metal layer on the substrate region and the middle portion of the active layer; removing the remaining third insulating layer on the second light-transmitting conductive layer in the light-transmitting capacitor region by ashing; Etching the source and drain metal layers on the light-transmitting capacitor region to form a source metal layer and a drain metal layer located on both sides of the active layer; The third insulating layer located on the TFT region is removed.

2. The method for manufacturing an embedded panel structure according to claim 1, characterized in that: The light-transmitting capacitor area is connected to the TFT area.

3. The method for manufacturing an embedded panel structure according to claim 1, characterized in that: Using a half-color mask to expose and develop the first insulating layer and the third insulating layer; The half-color mask includes: a first light-transmitting area, a second light-transmitting area and a third light-transmitting area; the transmittance of the first light-transmitting area is 100%, the transmittance of the third light-transmitting area is 0%, and the transmittance of the second light-transmitting area is between the transmittance of the first light-transmitting area and the transmittance of the third light-transmitting area.

4. The method for manufacturing an embedded panel structure according to claim 1, characterized in that: Also includes the steps: Making a fourth insulating layer; and making a first through hole on the fourth insulating layer, wherein the first through hole has the source metal layer or the drain metal layer as a bottom; Making a flat layer, and making a second through hole on the flat layer, wherein the second through hole is conductively connected to the first through hole; Manufacturing a light-transmitting anode, wherein the light-transmitting anode is connected to the source metal layer or the drain metal layer through a first through hole and a second through hole; Manufacturing a pixel definition layer, and exposing and developing the pixel definition layer to form a third through hole with the light-transmitting anode as the bottom, wherein the third through hole is located in the light-transmitting capacitor area; A light-emitting layer is manufactured, and the light-emitting layer is placed in the second through hole; and a cathode is manufactured on the light-emitting layer and the pixel definition layer.

5. The method for manufacturing an embedded panel structure according to claim 1, characterized in that: Before the step of sequentially forming the first light-transmitting conductive layer and the gate metal layer, the step further includes: Manufacturing a plurality of first conductive film layers on a substrate, wherein a plurality of first conductive film layer arrays are arranged on the substrate; A fifth insulating layer is manufactured, wherein the fifth insulating layer covers the plurality of first conductive film layers.

6. The method for manufacturing an embedded panel structure according to claim 1, characterized in that: Before the step of sequentially forming the first light-transmitting conductive layer and the gate metal layer, the step further includes: Manufacturing a plurality of second conductive film layers on a substrate, wherein a plurality of second conductive film layer arrays are arranged on the substrate; forming a sixth insulating layer, and removing the sixth insulating layer located between the second conductive film layers; A third conductive film layer is manufactured, and a seventh insulating layer is manufactured on the third conductive film layer.

7. An embedded panel structure, characterized in that: The embedded panel structure is made by the manufacturing method of the embedded panel structure according to any one of claims 1 to 6, wherein a first light-transmitting conductive layer and a gate metal layer are sequentially arranged on a substrate, the gate metal layer is arranged on one side of the first light-transmitting conductive layer, a TFT region and a light-transmitting capacitor region with a gate metal layer are formed on the first light-transmitting conductive layer, and the region outside the first light-transmitting conductive layer is a substrate region; a second insulating layer is arranged on the TFT region, the light-transmitting capacitor region and the substrate region, and an active layer is arranged on the second insulating layer, and the active layer is located above the gate metal layer; A second light-transmitting conductive layer is also arranged above the active layer, and the second light-transmitting conductive layer is placed on both sides of the active layer, and the second light-transmitting conductive layer on both sides overlaps with the active layer, and the side of the second light-transmitting conductive layer close to the light-transmitting capacitor area is located above the first light-transmitting conductive layer; a source metal layer and a drain metal layer are arranged on the second light-transmitting conductive layer, and the source metal layer and the drain metal layer are placed in the TFT area, and overlap with the active layer through the second light-transmitting conductive layer on one side.

8. The embedded panel structure according to claim 7, characterized in that: Also includes: a fourth insulating layer, a planar layer, a light-transmitting anode, a pixel definition layer, a light-emitting layer and a cathode; The fourth insulating layer is disposed on the second insulating layer, the second light-transmitting conductive layer, the active layer source metal layer and the drain metal layer, and a first through hole with the source metal layer or the drain metal layer as the bottom is also disposed on the fourth insulating layer; the flat layer is disposed on the fourth insulating layer, and a second through hole is also disposed on the flat layer, and the first through hole is conductively connected to the second through hole; A light-transmitting anode is arranged on the flat layer, and the light-transmitting anode is connected to the source metal layer or the drain metal layer through a first through hole and a second through hole; a pixel definition layer is arranged on the light-transmitting anode and the flat layer, and a third through hole with the light-transmitting anode as a bottom is arranged on the pixel definition layer; a light-emitting layer is arranged in the second through hole, and a cathode is arranged on the light-emitting layer and the pixel definition layer.

9. The embedded panel structure according to claim 8, characterized in that: The third through hole is disposed above the second light-transmitting conductive layer.

10. The embedded panel structure according to claim 7, characterized in that: Also includes: Touch control structure; the touch control structure is placed between the first light-transmitting conductive layer and the substrate.

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