Pixel structure, infrared image sensor and electronic device

Abstract

The present application provides a pixel structure, an infrared image sensor and an electronic device. In the pixel structure, a first via hole opposite to the first well region is provided in the first insulating layer, graphene fills the first via hole and forms a heterojunction with the first well region, and the deep well region is connected to the lower end of the first well region and the lower end of the second well region; the first electrode is in electrical contact with the graphene, and the upper end of the second well region forms an ohmic contact with the second electrode; the first well region, the second well region and the deep well region have the same conductivity type, the second well region surrounds the first well region and an isolation groove is provided between the two. The pixel structure of the present application can respond to a very wide infrared spectrum range.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to patent application number CN202110244460.9 filed on March 5, 2021 and entitled “Pixel structure, infrared image sensor and electronic device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application belongs to the field of photoelectric detection technology, and specifically relates to a pixel structure, an image sensor and an electronic device. Background Art

[0004] In existing infrared image sensors, materials such as indium gallium arsenide (InGaAs) and mercury cadmium telluride (HgCdTe) are mostly used as photosensitive layers to respond to infrared rays, and the photosensitive layer is connected to a readout circuit (specifically, the photosensitive layer is made above the readout circuit), and the readout circuit reads out the electrical signal generated by the photosensitive layer being irradiated by infrared rays. Limited by the band structure of the photosensitive layer material, the wavelength range of infrared rays that the infrared image sensor responds to is relatively narrow. Summary of the invention

[0005] The purpose of the present application is to provide a pixel structure, an infrared image sensor and an electronic device to address the deficiencies of the prior art.

[0006] In order to solve the above technical problems, the present application adopts the following technical solutions: a pixel structure, comprising: a semiconductor substrate, a first well region formed in the semiconductor substrate, a second well region formed in the semiconductor substrate, a deep well region formed in the semiconductor substrate, a first insulating layer formed on the upper surface of the semiconductor substrate, and graphene, a first electrode and a second electrode;

[0007] A first via hole opposite to the first well region is formed in the first insulating layer, the graphene fills the first via hole and forms a Schottky heterojunction with the first well region, and the deep well region is connected to the lower end of the first well region and the lower end of the second well region;

[0008] The first electrode is in electrical contact with the graphene, and an upper end of the second well region forms an ohmic contact with the second electrode;

[0009] The first well region, the second well region and the deep well region have the same conductivity type, the second well region surrounds the first well region and an isolation trench is provided between the two.

[0010] In some embodiments, the pixel structure also includes a third well region formed in the semiconductor substrate, the third well region surrounds the first well region and is surrounded by an isolation groove inside the second well region, the upper end of the third well region forms an ohmic contact with the first electrode, and the conductivity type of the third well region is opposite to the conductivity type of the first well region.

[0011] In some embodiments, the third well region is adjacent to the first well region and forms a PN junction.

[0012] In some embodiments, the third well region is adjacent to the deep well region and forms a PN junction.

[0013] In some embodiments, a distance is left between the third well region and the first well region and between the third well region and the deep well region.

[0014] In some embodiments, the pixel structure further includes: a first adjustment electrode, a second adjustment electrode, and a second insulating layer covering the graphene, the first adjustment electrode and the second adjustment electrode are both located on the side of the second insulating layer facing away from the semiconductor substrate, the contact surface of the graphene with the first well region overlaps with the orthographic projection of the first adjustment electrode on the plane where the semiconductor substrate is located, and the contact surface of the graphene with the first well region overlaps with the orthographic projection of the second adjustment electrode on the plane where the semiconductor substrate is located.

[0015] In some embodiments, the first adjustment electrode and the second adjustment electrode are both in block shape.

[0016] In some embodiments, the orthographic projections of the first adjustment electrode and the second adjustment electrode on the plane where the semiconductor substrate is located overlap with different halves of the orthographic projections of the contact surface between the graphene and the first well region on the plane where the semiconductor substrate is located.

[0017] In some embodiments, the first electrode has a lapped portion, the lapped portion is located on the upper surface of the first insulating layer, and the height of the graphene exceeds the lapped portion and is in electrical contact with a portion of the upper surface of the lapped portion.

[0018] In some embodiments, the first well region, the second well region, and the deep well region are all N-type wells or all P-type wells.

[0019] In some embodiments, the semiconductor material of the semiconductor substrate is silicon, indium phosphide, silicon carbide, gallium arsenide or gallium nitride.

[0020] In some embodiments, the doping concentration of the deep well region is lower than the doping concentration of the first well region.

[0021] In some embodiments, an orthographic projection of the second electrode on the plane where the semiconductor substrate is located surrounds an orthographic projection of the first electrode on the plane where the semiconductor substrate is located.

[0022] In some embodiments, the graphene contacts the first well region to form a Schottky heterojunction.

[0023] In some embodiments, a first protective layer and a second protective layer are further included, wherein the first protective layer is disposed on the lower surface of the graphene, and the second protective layer is disposed on the upper surface of the graphene, the first protective layer can be tunneled so that the graphene forms a Schottky heterojunction with the first well region, and the first protective layer and the second protective layer are both two-dimensional lattice structures.

[0024] In some embodiments, the material of the first protective layer and the material of the second protective layer are both boron nitride.

[0025] In some embodiments, the thickness of the first protective layer is less than 3 nm.

[0026] In some embodiments, the thickness of the second protective layer is less than 3 nm.

[0027] To solve the above technical problems, the present application adopts the following technical solution: an infrared image sensor, comprising the aforementioned pixel structure, and a readout circuit corresponding one-to-one to the pixel structure, the readout circuit comprising a plurality of transistors, the readout circuit being electrically connected to the first electrode and the second electrode respectively, the active layer of the transistor in the readout circuit being formed in the semiconductor substrate, and the orthographic projection of the active layer of the transistor in the readout circuit on the plane where the semiconductor substrate is located has no overlap with the orthographic projection of the first well region on the plane where the semiconductor substrate is located.

[0028] In some embodiments, the first insulating layer serves as a gate insulating layer of the plurality of transistors.

[0029] In order to solve the above technical problems, the present application adopts the following technical solution: an electronic device, including the above-mentioned infrared image sensor.

[0030] Compared with the prior art, the beneficial effects of the present application are as follows: graphene forms a Schottky heterojunction with the first well region, the heterojunction works in a reverse bias state, the photogenerated carriers generated by infrared light irradiation in the graphene enter the first well region and produce an avalanche effect, the readout circuit outside the pixel structure can read the current between the first electrode and the second electrode, and the processing circuit connected to the readout circuit can realize imaging according to the current value. Since graphene is a zero-bandgap material, graphene can respond well to near-infrared, mid-infrared and far-infrared infrared light, so the spectral range of infrared light that can be detected by the pixel structure is very wide. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a structural schematic diagram of a pixel structure according to an embodiment of the present application.

[0032] Figure 2 yes Figure 1 The orthographic projection of a portion of the pixel structure shown is on the plane where the semiconductor substrate is located.

[0033] Figure 3 is a schematic structural diagram of a pixel structure according to another embodiment of the present application.

[0034] Figure 4 yes Figure 3 The orthographic projection of a portion of the pixel structure shown is on the plane where the semiconductor substrate is located.

[0035] Figure 5 is a schematic diagram of the structure of an infrared image sensor according to an embodiment of the present application.

[0036] Figure 6 is a schematic structural diagram of a pixel structure according to another embodiment of the present application.

[0037] Among them, 1, semiconductor substrate; 21, first well region; 22, second well region; 23, deep well region; 24, third well region; 25, fourth well region; 3, isolation groove; 4, first insulating layer; 5, second insulating layer; 6, passivation layer; 7, graphene; 81, first protective layer; 82, second protective layer; P1, first electrode; P11, overlapping part; P2, second electrode; P3, first adjustment electrode; P4, second adjustment electrode; S, source; G, gate; D, drain. DETAILED DESCRIPTION

[0038] In the present application, it should be understood that terms such as “including” or “having” are intended to indicate the presence of the disclosed features, numbers, steps, behaviors, components, parts or combinations thereof in the present specification, but do not exclude the possibility of the presence of one or more other features, numbers, steps, behaviors, components, parts or combinations thereof.

[0039] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0040] The present application will be further described below in conjunction with the embodiments shown in the accompanying drawings.

[0041] As attached Figure 1 , Figure 3 as well as Figure 6 , as shown, an embodiment of the present application provides a pixel structure, comprising: a semiconductor substrate 1, a first well region 21 formed in the semiconductor substrate 1, a second well region 22 formed in the semiconductor substrate 1, a deep well region 23 formed in the semiconductor substrate 1, a first insulating layer 4 formed on the upper surface of the semiconductor substrate 1, and graphene 7, a first electrode P1 and a second electrode P2; a first via hole opposite to the first well region 21 is opened in the first insulating layer 4, the graphene 7 fills the first via hole and forms a Schottky heterojunction with the first well region 21, the deep well region 23 is connected to the lower end of the first well region 21 and the lower end of the second well region 22; the first electrode P1 is electrically in contact with the graphene 7, and the upper end of the second well region 22 is heavily doped to form an ohmic contact with the second electrode P2; the first well region 21, the second well region 22 and the deep well region 23 have the same conductivity type, the second well region 22 surrounds the first well region 21 and an isolation groove 3 is provided between the two.

[0042] The present application does not limit the semiconductor material in the semiconductor substrate 1, such as semiconductor materials such as silicon (Si), indium phosphide (InP), silicon carbide (SiC), gallium arsenide (GaAs) or gallium nitride (GaN). The semiconductor substrate 1 is, for example, lightly doped P-type silicon, and the first well region 21, the second well region 22 and the deep well region 23 are, for example, N wells. The first electrode P1 and the second electrode P2 are for connecting the heterojunction formed by the graphene 7 and the first well region 21 to an external readout circuit. In the working state, the heterojunction works in a reverse bias state.

[0043] Of course, the semiconductor substrate 1 may also be a lightly doped N-type substrate.

[0044] Of course, the first well region 21 , the second well region 22 and the deep well region 23 may also be P wells.

[0045] It should be noted that the structure in which the upper end of each well region forms an ohmic contact with the corresponding electrode is not limited thereto. For example, a very thin lightly doped region may be formed above the heavily doped region of each well region.

[0046] Photogenerated carriers are generated in the graphene 7 , and the electrons or holes therein enter the first well region 21 under the action of the electric field, and an avalanche effect occurs in the first well region 21 .

[0047] The depletion layer region in the semiconductor substrate 1 should be as large as possible, so the doping concentration of the deep well region 23 can be lower than the doping concentration at the bottom of the first well region 21 , so that the depletion region enters the deep well region 23 .

[0048] Of course, the doping concentration of the deep well region 23 may also be equal to the doping concentration at the bottom of the first well region 21 .

[0049] The electrons or holes in the photogenerated carriers generated by the graphene 7 irradiated by infrared rays enter the first well region 21 and produce an avalanche effect. The readout circuit outside the pixel structure can read the current between the first electrode P1 and the second electrode P2, and then the processing circuit connected to the readout circuit can realize imaging according to the current value. Since graphene 7 is a zero-bandgap material, graphene 7 can have a good response to far-infrared, mid-infrared and near-infrared infrared rays, so the bandwidth (spectral range) of infrared rays that can be detected by the pixel structure is very wide.

[0050] Specifically, due to the scattering and multiplication of hot electrons generated in graphene 7, and the zero-bandgap energy band structure of graphene 7, graphene 7 can generate photogenerated carriers in response to infrared light. The infrared photosensitive materials of the prior art only respond to infrared light through their intrinsic bandgap size, while graphene 7 can increase the low-energy infrared photogenerated electrons to an energy intensity detectable by the device (i.e., it can form a photogenerated current) through the electron scattering effect, and the scattering of the photogenerated carriers generated in graphene 7 has a current enhancement effect.

[0051] Taking silicon substrate as a semiconductor substrate as an example, the energy of photogenerated carriers generated by high-energy near-infrared photons in graphene is high, and the energy of electrons in the generated photogenerated carriers is higher than the Schottky barrier between graphene 7 and silicon, so that the electrons in the photogenerated carriers can directly jump from graphene 7 to silicon. Mid-infrared photons with slightly lower energy generate photogenerated carriers, and the energy of electrons in the generated photogenerated carriers is lower than the Schottky barrier between graphene 7 and silicon. However, in this case, the scattering effect of hot electrons in graphene 7 can increase the energy of a part of the electrons in the photogenerated carriers, making the energy of these electrons higher than the Schottky barrier, so that these electrons can jump from graphene 7 to silicon. Far-infrared photons with lower energy can also generate photogenerated carriers, but even the energy of scattered electrons in the photogenerated carriers is lower than the Schottky barrier, resulting in that all electrons in the photogenerated carriers cannot jump from graphene 7 to silicon. In this case, the clustering effect caused by the accumulation of electrons at the depletion layer boundary can generate a corresponding negative current, thereby generating a detectable photocurrent.

[0052] In some embodiments, reference Figure 1 , Figure 3 as well as Figure 4The pixel structure also includes a third well region 24 formed in the semiconductor substrate 1. The third well region 24 surrounds the first well region 21 and is surrounded by the isolation groove 3 inside the second well region 22. The upper end of the third well region 24 is heavily doped to form an ohmic contact with the first electrode P1. The conductivity type of the third well region 24 is opposite to that of the first well region 21.

[0053] The heavily doped region at the upper end of the third well region 24 and the graphene 7 are both electrically connected to the first electrode P1 . The function of the third well region 24 is to prevent the first insulating layer under the first electrode from being broken down.

[0054] For example, refer to Figure 3 , the third well region 24 is adjacent to the first well region 21 and forms a PN junction.

[0055] For example, refer to Figure 3 , the third well region 24 is adjacent to the deep well region 23 and forms a PN junction.

[0056] For another example, a distance is reserved between the third well region 24 and the first well region 21 and between the third well region 24 and the deep well region 23 .

[0057] In some embodiments, reference Figure 1 , Figure 2 and Figure 3 The pixel structure further includes a first adjustment electrode P3, a second adjustment electrode P4, and a second insulating layer 5 covering the graphene 7. The first adjustment electrode P3 and the second adjustment electrode P4 are both located on the side of the second insulating layer 5 facing away from the semiconductor substrate 1. The orthographic projection of the contact surface between the graphene 7 and the first well region 21 on the plane where the semiconductor substrate 1 is located overlaps with the orthographic projection of the first adjustment electrode P3 on the plane where the semiconductor substrate 1 is located. The orthographic projection of the contact surface between the graphene 7 and the first well region 21 on the plane where the semiconductor substrate 1 is located overlaps with the orthographic projection of the second adjustment electrode P4 on the plane where the semiconductor substrate 1 is located.

[0058] Applying different voltages to the first adjustment electrode P3 and the second adjustment electrode P4 can make the corresponding regions of the graphene 7 below them present as P regions and N regions respectively, so that the PN junction structure of the graphene 7 itself can be realized and the dark current in the graphene 7 can be suppressed. In addition, the Schottky barrier formed by the graphene 7 and silicon can also suppress the dark current. Then, the electrons or holes in the photogenerated carriers can bring avalanche gain after being injected into the first well region 21, so that the structure as described above can achieve ultra-high sensitivity, for example, this structure can be used for single photon detection and imaging.

[0059] In addition, since the carrier mobility in graphene 7 is high and the Schottky structure is a multi-substrate device structure, combined with the avalanche effect, the device response speed can be improved, so this structure can also achieve ultra-high-speed imaging.

[0060] The first adjustment electrode P3 and the second adjustment electrode P4 can also adjust the Fermi level of the graphene 7 and the barrier height of the Schottky barrier in the heterojunction formed with the first well region 21, thereby adjusting the size of the photocurrent and selecting the wavelength to which the graphene 7 can respond.

[0061] The structure of graphene 7 can be a single layer or multiple layers, and the upper limit of the thickness is determined by the voltage of the first adjustment electrode P3 and the second adjustment electrode P4 being unable to adjust the photogenerated current. The infrared photosensitive material of the prior art cannot adjust its Fermi level in real time through voltage, and therefore cannot adjust the Schottky barrier formed between it and the silicon substrate, so it is difficult to adjust the photogenerated current in real time.

[0062] In some embodiments, the first adjustment electrode P3 and the second adjustment electrode P4 are both block-shaped.

[0063] In some embodiments, the orthographic projections of the first adjustment electrode P3 and the second adjustment electrode P4 on the plane where the semiconductor substrate 1 is located overlap with different halves of the orthographic projections of the contact surface between the graphene 7 and the first well region 21 on the plane where the semiconductor substrate 1 is located.

[0064] The overlapping area between the first adjustment electrode P3 and the second adjustment electrode P4 and the contact surface should be as large as possible, so as to better control different areas in the graphene 7 to present different polarities (ie, N-type and P-type).

[0065] refer to Figure 1 and Figure 3 The first electrode P1 has an overlapping portion, which is located on the upper surface of the first insulating layer 4. The height of the graphene 7 exceeds the overlapping portion and is in electrical contact with a portion of the upper surface of the overlapping portion.

[0066] In this way, the electrical connection between the first electrode P1 and the graphene 7 is achieved. Of course, the overlapping portion may also be located on the upper surface of the graphene 7.

[0067] In some embodiments, an orthographic projection of the second electrode P2 on the plane where the semiconductor substrate 1 is located surrounds an orthographic projection of the first electrode P1 on the plane where the semiconductor substrate 1 is located.

[0068] The first electrode structure P1 is, for example, ring-shaped, and its outer contour is, for example, circular, square, octagonal, etc.

[0069] Figure 1 and Figure 3 In the embodiment shown, the graphene 7 contacts the first well region 21 to form a Schottky heterojunction. Figure 6In the illustrated embodiment, the pixel structure further includes: a first protective layer 81 and a second protective layer 82, wherein the first protective layer 81 is disposed on the lower surface of the graphene 7, and the second protective layer 82 is disposed on the upper surface of the graphene 7, and the first protective layer 81 can be tunneled so that the graphene 7 forms a Schottky heterojunction with the first well region 21, and the first protective layer 81 and the second protective layer 82 are both two-dimensional lattice structures.

[0070] Since the graphene 7 is a two-dimensional lattice structure, the first protective layer 81 and the second protective layer 82 should also be a two-dimensional lattice structure, so as to form a stable connection with the graphene 7. The first protective layer 81 and the second protective layer 82 function to provide mechanical protection for the graphene 7.

[0071] The first protective layer 81 cannot affect the formation of the Schottky barrier between the graphene 7 and the first well region 21. Therefore, the first protective layer 81 should be as thin as possible. In some embodiments, the thickness of the first protective layer 81 is less than 3nm. Preferably, the thickness of the first protective layer 81 is 1nm to 2nm.

[0072] In some embodiments, the thickness of the second protective layer 82 is less than 3 nm. The second protective layer 82 is relatively thin, which is conducive to improving the adhesion and mechanical consistency between the second protective layer 82 and the graphene 7.

[0073] The area of ​​the graphene 7 covered by the first protective layer 81 and the second protective layer 82 should be as large as possible, so as to better protect the graphene 7.

[0074] In some embodiments, the material of the first protective layer 81 and the material of the second protective layer 82 are both boron nitride, and hexagonal boron nitride (h-BN) is preferred. This is because hexagonal boron nitride has a wide energy band gap, low dielectric constant, high thermal conductivity, and good mechanical strength, and is a two-dimensional lattice, which is easy to make into an ultra-thin structure.

[0075] An embodiment of the present application also provides an infrared image sensor, including the aforementioned pixel structure, and a readout circuit corresponding one-to-one to the pixel structure, the readout circuit including a plurality of transistors, the readout circuit being electrically connected to the first electrode P1 and the second electrode P2, respectively, the active layer of the transistor in the readout circuit being formed in the semiconductor substrate, the orthographic projection of the active layer of the transistor in the readout circuit on the plane where the semiconductor substrate 1 is located and the orthographic projection of the first well region on the plane where the semiconductor substrate 1 is located having no overlap.

[0076] The present application does not limit how the readout circuit reads the current between the first electrode P1 and the second electrode P2 , and reference may be made to existing designs.

[0077] Since the readout circuit and the corresponding pixel structure are arranged in the horizontal direction rather than in a vertical relationship, this greatly simplifies the manufacturing process of the infrared image sensor.

[0078] In some embodiments, the first insulating layer 4 serves as a gate insulating layer of a plurality of transistors.

[0079] Figure 5 The fourth well region 25 in the figure has source and drain regions of multiple transistors, wherein a set of source S, drain D and gate G is shown, representing one transistor. The area near the upper surface of the semiconductor substrate 1 below the gate G is an active layer.

[0080] The present application does not limit the number of layers of metal wiring in the infrared image sensor. Usually, a passivation layer 6 is provided on the upper part of the metal wiring.

[0081] The embodiment of the present application further provides an electronic device, comprising the aforementioned infrared image sensor. The electronic device is, for example, a device carrying an infrared image sensor, such as a drone, a three-dimensional depth camera, or a laser radar.

[0082] The various embodiments in the present application are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0083] The protection scope of this application is not limited to the above-mentioned embodiments. Obviously, those skilled in the art can make various changes and modifications to this application without departing from the scope and spirit of this application. If these changes and modifications fall within the scope of the claims of this application and their equivalents, the intention of this application also includes these changes and modifications.

Claims

1. A pixel structure, characterized in that: include: A semiconductor substrate (1), a first well region (21) formed in the semiconductor substrate (1), a second well region (22) formed in the semiconductor substrate (1), a deep well region (23) formed in the semiconductor substrate (1), a first insulating layer (4) formed on the upper surface of the semiconductor substrate (1), and comprising: graphene (7), a first electrode (P1) and a second electrode (P2); A first via hole opposite to the first well region (21) is provided in the first insulating layer (4); the graphene (7) fills the first via hole and forms a Schottky heterojunction with the first well region (21); the deep well region (23) is connected to the lower end of the first well region (21) and the lower end of the second well region (22); The first electrode (P1) is in electrical contact with the graphene (7), and the upper end of the second well region (22) forms an ohmic contact with the second electrode (P2); The first well region (21), the second well region (22) and the deep well region (23) have the same conductivity type; the second well region (22) surrounds the first well region (21) and an isolation groove (3) is provided between the two; The pixel structure further comprises a third well region (24) formed in the semiconductor substrate (1), the third well region (24) surrounding the first well region (21) and surrounded by an isolation groove (3) inside the second well region (22), an upper end of the third well region (24) forming an ohmic contact with the first electrode (P1), and a conductivity type of the third well region (24) being opposite to that of the first well region (21).

2. The pixel structure according to claim 1, characterized in that: The pixel structure further comprises: a first adjustment electrode (P3), a second adjustment electrode (P4), and a second insulating layer (5) covering the graphene (7); the first adjustment electrode (P3) and the second adjustment electrode (P4) are both located on the side of the second insulating layer (5) facing away from the semiconductor substrate (1); the orthographic projection of the contact surface between the graphene (7) and the first well region (21) on the plane where the semiconductor substrate (1) is located overlaps with the orthographic projection of the first adjustment electrode (P3) on the plane where the semiconductor substrate (1) is located; and the orthographic projection of the contact surface between the graphene (7) and the first well region (21) on the plane where the semiconductor substrate (1) is located overlaps with the orthographic projection of the second adjustment electrode (P4) on the plane where the semiconductor substrate (1) is located.

3. The pixel structure according to claim 1, characterized in that: The invention also comprises a first protective layer (81) and a second protective layer (82), wherein the first protective layer (81) is arranged on the lower surface of the graphene (7), and the second protective layer (82) is arranged on the upper surface of the graphene (7), the first protective layer (81) can be tunneled so that the graphene (7) and the first well region (21) form a Schottky heterojunction, and the first protective layer (81) and the second protective layer (82) are both two-dimensional lattice structures.

4. The pixel structure according to claim 3, characterized in that: The material of the first protective layer (81) and the material of the second protective layer are both boron nitride.

5. The pixel structure according to claim 3, characterized in that: The thickness of the first protective layer (81) is less than 3 nm.

6. An infrared image sensor, characterized in that: The invention comprises a pixel structure according to any one of claims 1 to 5, and a readout circuit corresponding to the pixel structure one by one, the readout circuit comprising a plurality of transistors, the readout circuit being electrically connected to the first electrode (P1) and the second electrode (P2) respectively, the active layers of the transistors in the readout circuit being formed in the semiconductor substrate (1), and the orthographic projection of the active layers of the transistors in the readout circuit on the plane where the semiconductor substrate (1) is located does not overlap with the orthographic projection of the first well region (21) on the plane where the semiconductor substrate (1) is located.

7. The image sensor according to claim 6, characterized in that: The first insulating layer (4) serves as a gate insulating layer of the plurality of transistors.

8. An electronic device, characterized in that: Comprising the infrared image sensor according to claim 6 or 7.

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