A comparator and control method thereof

Abstract

The invention discloses a comparator and a control method thereof, which can realize offset elimination and improve operation speed and accuracy. The comparator comprises an amplifier, a transmission gate switch, a dynamic latch comparator and a coupling capacitor. A first preamplifier, a second preamplifier and the dynamic latch comparator are connected in sequence, an output end of the dynamic latch comparator is connected to a SAR control logic circuit, a differential signal transmission gate switch is connected to the first preamplifier, and a reference signal transmission gate switch is respectively connected to the first preamplifier, the second preamplifier and the dynamic latch comparator. The comparator control method comprises: when a sampling circuit samples, switches S1 and S2 are disconnected, switches S3 to S8 are closed, differential input ends of the first preamplifier, the second preamplifier and the dynamic latch comparator are connected to a reference signal, when a comparison circuit compares, switches S1 and S2 are closed, switches S3 to S8 are disconnected, and the input of the first preamplifier is connected to a differential signal.

Description

Technical Field

[0001] The present invention relates to the technical field of comparators, and in particular to a high-precision low-offset comparator and a control method thereof. Background Art

[0002] At present, the commonly used analog-to-digital converter is SAR ADC (successive approximation register analog-to-digital converter), which occupies most of the medium to high-resolution ADC market. SAR ADC, as an interface circuit that converts analog signals into digital signals, mainly includes sampling and holding circuits, comparators, SAR control logic circuits, D / A conversion circuits, etc. The comparator is one of the important modules of SAR ADC, which is used to compare the size of an analog signal with another analog signal and output a binary digital signal. In short, a comparator is a one-bit ADC, and its accuracy, speed, offset and other indicators directly affect the performance of the entire SAR ADC. As the feature size of the CMOS process continues to decrease, the power supply voltage of the circuit continues to decrease, and other nonlinear factors such as process variables are affected, the noise of the transistor becomes larger, so the impact of the noise of the comparator on the ADC becomes more significant.

[0003] Comparators can be divided into op amp structure comparators and dynamic latch comparators according to their principles. Op amp structure comparators can distinguish smaller input voltage differences, but at a slow speed; dynamic latch comparators are fast, but can only distinguish larger voltage differences, and their input offset voltage and kickback noise are also large. Using the above two comparators alone is difficult to meet the requirements of distinguishing smaller input voltage differences at high speed. Summary of the invention

[0004] In view of the problems in the prior art that the comparator of the SAR ADC has a slow operating speed and poor resolution for a small input voltage difference, the present invention provides a comparator and a control method thereof, which can achieve offset elimination and improve operating speed and accuracy.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] A comparator, comprising an amplifier and a transmission gate switch, characterized in that it also includes a dynamic latch comparator, the amplifier comprises a first preamplifier and a second preamplifier, the first preamplifier, the second preamplifier and the dynamic latch comparator are connected in sequence, the transmission gate switch comprises a differential signal transmission gate switch and a reference signal transmission gate switch, the differential signal transmission gate switch is connected to the first preamplifier, the reference signal transmission gate switch is respectively connected to the first preamplifier, the second preamplifier and the dynamic latch comparator, the differential signal transmission gate switch and the reference signal transmission gate switch are respectively used for differential signal and reference signal The invention also includes a coupling capacitor, wherein the coupling capacitors are respectively connected between the first preamplifier and the second preamplifier, and between the second preamplifier and the dynamic latch comparator, the output terminal VOUT of the dynamic latch comparator is connected to the SAR control logic circuit, the first preamplifier, the second preamplifier, and the dynamic latch comparator are respectively connected to enable signals ENC and ENB, the first preamplifier and the second preamplifier are respectively connected to enable signals ENA, the dynamic latch comparator is connected to an enable signal END, and the enable signals ENC, ENB, ENA, and END are high or low.

[0007] It is further characterized in that

[0008] The transmission gate switch includes switches S1, S2, S3, S4, S5, S6, S7, and S8, wherein the differential signal transmission gate switch includes switches S1 and S2, and the reference signal transmission gate switch includes switches S3, S4, S5, S6, S7, and S8;

[0009] The coupling capacitors include capacitors C1 to C4;

[0010] The first preamplifier includes field effect transistors M1-M21, and the field effect transistors M1-M8 are divided into four groups as transmission gate switches of the first preamplifier, namely: a first transmission gate switch, a second transmission gate switch, a third transmission gate switch, and a fourth transmission gate switch. The first transmission gate switch includes field effect transistors M1 and M3, the second transmission gate switch includes field effect transistors M2 and M4, the third transmission gate switch includes field effect transistors M5 and M7, and the fourth transmission gate switch includes field effect transistors M6 and M8; the gates of the field effect transistors M1, M4, M6 and M7 are connected to an enable signal ENC, the gates of the field effect transistors M2, M3, M5 and M8 are connected to the enable signal ENB, and the gates of the field effect transistors M12 and M17 are connected to the enable signal ENA;

[0011] The field effect transistor M9 is a tail current transistor, and the gate is connected to the bias voltage Vb; the field effect transistors M10 and M11 form a differential pair of transistors;

[0012] The field effect transistors M13 to M16 are cross-coupled connection structures, the field effect transistors M13 and M16 are diode-connected loads, the transistors M14 and M15 are cross-coupled to form negative feedback, the transistors M12 and M17 are used as switch tubes, and the gates are connected to the enable signal ENA, the transistors M18, M19, M20, and M21 constitute a second-stage amplifier circuit, and the width-to-length ratio of the field effect transistors M13 and M16 is greater than the width-to-length ratio of the field effect transistors M14 and M15.

[0013] The structure of the second preamplifier is consistent with that of the first preamplifier;

[0014] The second preamplifier includes field effect transistors M22 to M38, and the field effect transistors M22 to M25 are divided into two groups as transmission gate switches of the second preamplifier, namely: a fifth transmission gate switch and a sixth transmission gate switch, the fifth transmission gate switch includes the field effect transistors M22 and M23, the sixth transmission gate switch includes the field effect transistors M24 and M25, the gates of the field effect transistors M22 and M24 are connected to the enable signal ENB, the gates of the field effect transistors M23 and M25 are connected to the enable signal ENC, and the gates of the field effect transistors M29 and M34 are connected to the enable signal ENA;

[0015] The transistor M26 is a tail current transistor, and its gate is connected to the bias voltage Vb. The transistors M27 and M28 form a differential pair of transistors.

[0016] The field effect transistors M30 to M33 are cross-coupled connection structures, the transistors M30 and M33 are diode-connected loads, the transistors M31 and M32 are cross-coupled to form negative feedback, the transistors M29 and M34 are switch transistors, and the gates are connected to the enable signal ENA, and the transistors M35, M36, M37, and M38 constitute a second-stage amplifier circuit; the width-to-length ratio of the field effect transistors M30 and M33 is greater than the width-to-length ratio of the field effect transistors M31 and M32;

[0017] The dynamic latch comparator includes field effect transistors M39 to M57, and the field effect transistors M39 to M42 are divided into two groups as transmission gate switches of the dynamic latch comparator, which are the seventh transmission gate switch and the eighth transmission gate switch, respectively. The seventh transmission gate switch includes field effect transistors M39 and M40, and the eighth transmission gate switch includes field effect transistors M41 and M42. The gates of the field effect transistors M39 and M41 are connected to the enable signal ENB, the gates of the field effect transistors M40 and M42 are connected to the enable signal ENC, and the gates of the field effect transistors M43, M46, M47, M52, and M53 are connected to the enable signal END;

[0018] The transistor M43 is a tail current tube;

[0019] The field effect transistors M49 to M51 are inverter cross-coupled structures, the transistors M46, M47, M52 and M53 are reset transistors, and their gates are connected to the enable signal END. The field effect transistors M49 and M51 are both NMOS transistors of cross-coupled inverters. The field effect transistors M48, M49, M50 and M51 form a cross-coupled inverter. The transistors M54, M55, M56 and M57 respectively form inverters, and the output terminal VOUT is connected to the SAR control logic circuit.

[0020] A comparator control method is applied to the comparator, and the comparator is connected to the SAR control logic circuit, which is a part of the SAR ADC. The method comprises: step 1, when the sampling circuit is sampling, the switches S1 and S2 are disconnected, the switches S3 to S8 are closed, and the differential input terminals of the first preamplifier, the second preamplifier, and the dynamic latch comparator are connected to the reference signal VCM;

[0021] The enable signal ENB is at a high level, and the enable signal ENC is at a low level;

[0022] Step 2: When the comparison circuit compares, the switches S1 and S2 are closed, the switches S3 to S8 are opened, and the input of the first preamplifier is connected to the differential signals VINN and VINP;

[0023] The enable signal ENB is at a low level, the enable signal ENC is at a high level, the enable signal ENA is at a high level, and the field effect transistors M12, M17, M29, and M34 are in a cut-off state;

[0024] When the comparison circuit compares, the dynamic latch comparator includes two working states: a reset stage and a regeneration stage. When in the reset stage, the enable signal END is a low level, and when in the regeneration stage, the enable signal END is a high level. At this time, if the differential signal VINN is greater than VINP, the output terminal VOUT outputs a low level, and if the differential signal VINN is less than VINP, the output terminal VOUT outputs a high level.

[0025] Step 3: When the comparison circuit stops working, the enable signal ENA is at a low level. At this time, the field effect transistors M18, M20, M29, and M34 are all in the cut-off region, and the output is in a high impedance state.

[0026] The following beneficial effects can be achieved by adopting the above structure and method of the present invention: 1. The high-precision low-offset comparator of the present application includes a first preamplifier, a second preamplifier, and a dynamic latch comparator. The first preamplifier, the second preamplifier, and the dynamic latch comparator constitute a three-stage comparator structure. The preamplifier amplifies the input signal step by step to an amplitude that the dynamic latch comparator can effectively identify. Then the dynamic latch comparator quickly amplifies the signal to an amplitude that the digital circuit can effectively identify through positive feedback. This structure not only improves the operating speed and accuracy of the comparator, but also achieves low offset, can basically accurately distinguish a voltage difference of 0.1mV, and achieves accurate distinction of smaller input voltage differences.

[0027] 2. The method of the present application controls the input signals of the comparator: differential signal, reference signal through the transmission gate switches S1 to S8, and makes the enable signals ENC, ENB, ENA, and END of the comparator work in a high level state or a low level state according to the SAR control logic circuit, thereby realizing effective control of the output voltage of the comparator. The use of the method of the present application to control the comparator not only improves the operating speed and accuracy of the comparator and reduces the offset, but also can basically accurately distinguish the voltage difference of 0.1mV, realizing accurate distinction of smaller input voltage differences. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A connection structure diagram of a first preamplifier, a second preamplifier, and a dynamic latch comparator in the comparator of the present invention;

[0029] Figure 2 is a circuit schematic diagram of the first preamplifier of the present invention;

[0030] Figure 3 is a circuit schematic diagram of the second preamplifier of the present invention;

[0031] Figure 4 is a circuit schematic diagram of a dynamic latch comparator of the present invention;

[0032] Figure 5 The following is a simulation waveform diagram for simulating the differential signal, reference signal, enable signal, and output signal of the output terminal VOUT of the comparator of the present invention. DETAILED DESCRIPTION

[0033] See Figure 1 A comparator includes an amplifier, a transmission gate switch, and a dynamic latch comparator. The amplifier includes a first preamplifier 1 and a second preamplifier 2. The first preamplifier 1, the second preamplifier 2, and the dynamic latch comparator 3 are connected in sequence. The transmission gate switch includes a differential signal transmission gate switch and a reference signal transmission gate switch. The differential signal transmission gate switch is connected to the first preamplifier 1. The reference signal transmission gate switch is respectively connected to the first preamplifier 1, the second preamplifier 2, and the dynamic latch comparator 3. The differential signal transmission gate switch and the reference signal transmission gate switch are respectively used for inputting differential signals VINP and VINN and a reference signal VCM. The comparator also includes a coupling capacitor. Coupling capacitors are respectively connected between the first preamplifier 1 and the second preamplifier 2, and between the second preamplifier 2 and the dynamic latch comparator 3. The output end VOUT of the dynamic latch comparator 3 is connected to a SAR control logic circuit. The first preamplifier 1, the second preamplifier 2, and the dynamic latch comparator 3 are connected to the enable signals ENC and ENB respectively. The first preamplifier 1 and the second preamplifier 2 are also connected to the enable signal ENA respectively. The dynamic latch comparator 3 is also connected to the enable signal END. The enable signals ENC, ENB, ENA, and END are high or low.

[0034] The transmission gate switch includes switches S1, S2, S3, S4, S5, S6, S7, and S8, wherein the input signal transmission gate switch includes switches S1 and S2, and the reference signal transmission gate switch includes switches S3, S4, S5, S6, S7, and S8; the coupling capacitor includes capacitors C1 to C4. When the sampling circuit is sampling, switches S1 and S2 are disconnected, and switches S3 to S8 are all in a closed state. At this time, the differential input terminals of the first preamplifier 1, the second preamplifier 2, and the dynamic latch comparator 3 are all connected to the reference signal VCM. At this time, the enable signal ENB is at a high level, and the enable signal ENC is at a low level; in the comparison stage, switches S1 and S2 are closed, switches S3 to S8 are disconnected, the input of the first preamplifier is connected to the differential signals VINN and VINP, the enable signal ENB is at a low level, the enable signal ENC is at a high level, the enable signal ENA is at a high level, and the field effect transistors M12, M17, M29, and M34 are in a cut-off state;

[0035] When the comparison circuit compares, the dynamic latch comparator includes two working states: reset stage and regeneration stage. When in the reset stage, the enable signal END is a low level, and when in the regeneration stage, the enable signal END is a high level. At this time, if the differential signal VINN is greater than VINP, the output terminal VOUT outputs a low level, and if the differential signal VINN is less than VINP, the output terminal VOUT outputs a high level.

[0036] The above three-stage high-speed, high-precision, low-offset comparator can distribute the gain to each operational amplifier. The gain of each operational amplifier does not need to be too large. At the same time, the input offset storage and output offset storage cascade method is used to eliminate the influence of the input offset voltage. Specifically, the input offset voltage is stored in the input-output coupling capacitors C1 to C4 connected between the first preamplifier, the second preamplifier and the dynamic latch comparator.

[0037] See Figure 2 The first preamplifier 1 includes field effect transistors M1 to M21, and the field effect transistors M1 to M8 are divided into four groups as transmission gate switches of the first preamplifier, namely: a first transmission gate switch, a second transmission gate switch, a third transmission gate switch, and a fourth transmission gate switch. The first transmission gate switch includes field effect transistors M1 and M3, the second transmission gate switch includes field effect transistors M2 and M4, the third transmission gate switch includes field effect transistors M5 and M7, and the fourth transmission gate switch includes field effect transistors M6 and M8; the gates of the field effect transistors M1, M4, M6, and M7 are connected to the enable signal ENC, and the gates of the field effect transistors M2, M3, M5, and M8 are connected to the enable signal E NB, the gates of field effect transistors M12 and M17 are connected to the enable signal ENA; field effect transistor M9 is a tail current tube, and the gate is connected to the bias voltage Vb; field effect transistors M10 and M11 form a differential pair; the source of transistor M1 and the drain of transistor M3 are connected to the differential signal VINP, the drain of transistor M6 and the source of transistor M8 are connected to the differential signal VINN, the drain of transistor M2, the source of transistor M4, the source of transistor M5, and the drain of transistor M7 are connected to the reference signal VCM. When the comparator starts to compare, the enable signal ENB is low level, the enable signal ENC is high level, and the differential pair of the comparator is respectively connected to the differential signals VINP and VINN voltages generated by the DAC;

[0038] Field effect transistors M13 to M16 are cross-coupled structures with diode-connected loads, field effect transistors M13 and M16 are diode-connected loads, transistors M14 and M15 are cross-coupled to form negative feedback, transistors M12 and M17 are used as switch tubes, and the gates are connected to enable signals ENA, and transistors M18, M19, M20, and M21 constitute a second-stage amplifier circuit. The width-to-length ratio of field effect transistors M13 and M16 is greater than the width-to-length ratio of field effect transistors M14 and M15, which can ensure the overall negative feedback and prevent hysteresis, otherwise it will constitute strong positive feedback; when the comparator compares, the enable signal ENA connected to transistors M12 and transistor M17 is at a high level, and the two transistors are in a cut-off state. When the comparator is not working, the enable signal ENA is at a low level, and at this time, transistors M18 and transistor M20 will be in a cut-off region, and the output is a high impedance state.

[0039] See Figure 3 The structure of the second preamplifier 2 is consistent with that of the first preamplifier 1. The second preamplifier 2 includes field effect transistors M22 to M38. The field effect transistors M22 to M25 are divided into two groups as transmission gate switches of the second preamplifier 2, namely: a fifth transmission gate switch and a sixth transmission gate switch. The fifth transmission gate switch includes field effect transistors M22 and M23. The sixth transmission gate switch includes field effect transistors M24 and M25. The gates of the field effect transistors M22 and M24 are connected to an enable signal ENB. The gates of the field effect transistors M23 and M25 are connected to an enable signal ENC. The gates of the field effect transistors M29 and M34 are connected to an enable signal ENA. The transistor M26 is a tail current tube, and the gate is connected to a bias voltage Vb. The transistors M27 and M28 form a differential pair tube.

[0040] See Figure 4, field effect transistors M30 to M33 are cross-coupled with gate-drain connection of diode-connected loads, transistors M30 and M33 are diode-connected loads (i.e., the gate and drain of field effect transistors M30 and M33 are short-circuited to play the role of small signal resistors), transistors M31 and M32 are cross-coupled to form negative feedback, transistors M29 and M34 are switch tubes, and the gate is connected to the enable signal ENA, and transistors M35, M36, M37, and M38 constitute the second-stage amplifier circuit; when the circuit is sampling, the enable signal ENB is high, and the enable signal ENC is low, so that the input end of the differential pair is connected to the reference signal VCM, and when the comparator starts During comparison, the enable signal ENB is at a low level, the enable signal ENC is at a high level, and the differential pair is respectively connected to the output of the first preamplifier 1; the width-to-length ratio of the field effect transistors M30 and M33 is greater than the width-to-length ratio of the field effect transistors M31 and M32, which can ensure the overall negative feedback and prevent hysteresis, otherwise it will constitute a strong positive feedback, and the kick-back noise for the first preamplifier 1 will be relatively large; when the comparator compares, the enable signal ENA of the gate of the switch tubes M29 and M34 is at a high level, and the two transistors are in the cut-off state. When the comparator is not working, the enable signal ENA is at a low level. At this time, the transistors M29 and M34 will be in the cut-off area, and the output will be in a high impedance state.

[0041] The dynamic latch comparator includes field effect transistors M39 to M57. The field effect transistors M39 to M42 are divided into two groups as transmission gate switches of the dynamic latch comparator, which are the seventh transmission gate switch and the eighth transmission gate switch. The seventh transmission gate switch includes field effect transistors M39 and M40. The eighth transmission gate switch includes field effect transistors M41 and M42. The gates of the field effect transistors M39 and M41 are connected to the enable signal ENB. The gates of the field effect transistors M40 and M42 are connected to the enable signal ENC. The gates of the field effect transistors M46 and M53 are connected to the enable signal END. The transistor M43 is a tail current tube.

[0042] Field effect transistors M49 to M57 are inverter cross-coupled structures, transistors M46, M47, M52 and M53 are reset transistors, and their gates are connected to the enable signal END. Field effect transistors M49 and M51 are NMOS transistors of cross-coupled inverters, field effect transistors M48, M49, M50, and M51 form a cross-coupled inverter, and transistors M54, M55, M56, and M57 form inverters respectively, and the output terminal VOUT is connected to the SAR control logic circuit. When the circuit is sampling, the enable signal ENB is high, the enable signal ENC is low, and the input of the differential pair is connected to the reference signal VCM. When the comparator starts to compare, the enable signal ENB is low, the enable signal ENC is high, and the differential pair is respectively connected to the output of the second preamplifier 2. The comparator has two working states, namely the reset stage and the regeneration stage. When in the reset stage, the enable signal END is low, the tail current tube M43 is disconnected, and the power supply voltage VDD straightens the gate and drain of the transistors M48 and M50 through the reset tubes M47 and M53 to the high level VDD, and charges the drain of the differential input pair tubes M44 and M45 to VDD through the reset tubes M46 and M53, thereby increasing the input pair tubes M44 and M45 in the regeneration stage. The time in the saturation region also shows that a greater gain can be obtained, thereby reducing the equivalent input offset voltage; in the regeneration stage, transistor M43 is turned on, and the input pair of tubes of the dynamic latch comparator begins to discharge the drains of the two pairs of tubes at different discharge speeds. When the drain of one of the tubes drops to VDD-VTH (M49 or M51), the NMOS tube M49 or M51 of the cross-coupled inverter begins to turn on, and then discharges the drain of the tube. The dynamic latch comparator enters the positive feedback stage. When the drain of the tube drops to VDD-VTH (M48 or M50), the cross-inverter PMOS tube M48 or M50 begins to turn on, and finally one end of the gate and drain of the PMOS tubes M48 and M50 is pulled to a low level through positive feedback, and the other end is kept at a high level.

[0043] The EDA software simulation verification is used to simulate the differential signal, reference signal, enable signal and output signal of the signal output terminal VOUT of the above comparator, see Figure 5, the differential signal VINN inputs a 2.5V voltage, and VINP inputs a sin waveform. The waveforms of VINN1 and VINP1 are affected by the two enable signals ENB and ENC. When ENB is high and ENC is low, VINN1 and VINP1 are equal to VCM. When ENB is low and ENC is high, the values ​​of VINN1 and VINP1 are equal to VINN and VINP respectively. When the dynamic latch comparator works normally, ENA remains high. When END is low, it is the reset stage of the dynamic latch comparator. When END is high, it is the regeneration stage. If VINN is greater than VINP at this time, VOUT outputs a low level. If VINN is less than VINP, VOUT outputs a high level.

[0044] The simulation software is used to perform Tran noise analysis (transmission noise analysis). Tran noise analysis is similar to traditional Tran analysis, except that random device noise signals are injected at each time step. In this embodiment, 50 groups of Tran noise analysis are performed when the difference between VINN and VINP is 0.1mV, that is, 50 groups of noise seeds of random number generators are added for analysis. Each group is compared 37 times, for a total of 1850 comparisons. There are 8 groups with errors, 12 errors in total, and the error rate is only 0.64%. The conclusion shows that the comparator of the present application can basically accurately distinguish a voltage difference of 0.1mV, and achieves accurate distinction of smaller voltage differences; the first preamplifier, the second preamplifier and the dynamic latch comparator are combined into a high-speed and high-precision comparator with low offset, thereby improving the operating speed and accuracy of the comparator.

[0045] The above are only preferred embodiments of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A comparator control method, comprising an amplifier and a transmission gate switch, characterized in that: It also includes a dynamic latch comparator, the amplifier includes a first preamplifier and a second preamplifier, the first preamplifier, the second preamplifier, and the dynamic latch comparator are connected in sequence, the transmission gate switch includes a differential signal transmission gate switch and a reference signal transmission gate switch, the differential signal transmission gate switch is connected to the first preamplifier, the reference signal transmission gate switch is respectively connected to the first preamplifier, the second preamplifier, and the dynamic latch comparator, the differential signal transmission gate switch and the reference signal transmission gate switch are respectively used for inputting differential signals VINN, VINP, and reference signals; it also includes a coupling capacitor, the first preamplifier The coupling capacitor is connected between the first preamplifier and the second preamplifier, and between the second preamplifier and the dynamic latch comparator respectively. The output end VOUT of the dynamic latch comparator is connected to the SAR control logic circuit. The first preamplifier, the second preamplifier, and the dynamic latch comparator are respectively connected to enable signals ENC and ENB. The first preamplifier and the second preamplifier are respectively connected to enable signals ENA. The dynamic latch comparator is connected to an enable signal END. The enable signals ENC, ENB, ENA, and END are high or low. The first preamplifier includes field effect transistors M1 to M21. The transmission gate switch includes switches S1, S2, S3, S4, S5, S6, S7, and S8, wherein the differential signal transmission gate switch includes switches S1 and S2, and the reference signal transmission gate switch includes switches S3, S4, S5, S6, S7, and S8; The field effect transistors M1-M8 are divided into four groups as transmission gate switches of the first preamplifier, namely: a first transmission gate switch, a second transmission gate switch, a third transmission gate switch, and a fourth transmission gate switch, wherein the first transmission gate switch includes field effect transistors M1 and M3, the second transmission gate switch includes field effect transistors M2 and M4, the third transmission gate switch includes field effect transistors M5 and M7, and the fourth transmission gate switch includes field effect transistors M6 and M8; the gates of the field effect transistors M1, M4, M6, and M7 are connected to an enable signal ENC, the gates of the field effect transistors M2, M3, M5, and M8 are connected to the enable signal ENB, and the gates of the field effect transistors M12 and M17 are connected to the enable signal ENA; The field effect transistor M9 is a tail current transistor, and the gate is connected to the bias voltage Vb; the field effect transistors M10 and M11 form a differential pair of transistors; The field effect transistors M13 to M16 are cross-coupled connection structures, the field effect transistors M13 and M16 are diode-connected loads, the field effect transistors M14 and M15 are cross-coupled connection to form negative feedback, the field effect transistors M12 and M17 are used as switch transistors, and the gates are connected to the enable signal ENA, the field effect transistors M18, M19, M20, and M21 constitute a second-stage amplifier circuit, and the width-to-length ratio of the field effect transistors M13 and M16 is greater than the width-to-length ratio of the field effect transistors M14 and M15; The comparator is connected to the SAR control logic circuit, and the method includes: Step 1: When the sampling circuit samples, the switches S1 and S2 are opened, the switches S3 to S8 are closed, and the differential input terminals of the first preamplifier, the second preamplifier, and the dynamic latch comparator are connected to the reference signal; The enable signal ENB is at a high level, and the enable signal ENC is at a low level; Step 2: When the comparator compares, the switches S1 and S2 are closed, the switches S3 to S8 are opened, and the input of the first preamplifier is connected to the differential signals VINN and VINP; The enable signal ENB is at a low level, the enable signal ENC is at a high level, the enable signal ENA is at a high level, and the field effect transistors M12, M17, M29, and M34 are in a cut-off state; When the comparator compares, the dynamic latch comparator includes two working states: a reset stage and a regeneration stage. When in the reset stage, the enable signal END is at a low level. When in the regeneration stage, the enable signal END is at a high level. At this time, if the differential signal VINN is greater than VINP, the output terminal VOUT outputs a low level. If the differential signal VINN is less than VINP, the output terminal VOUT outputs a high level. Step 3: When the comparator stops working, the enable signal ENA is at a low level. At this time, the field effect transistors M18, M20, M29, and M34 are all in the cut-off region, and the output is in a high impedance state.

2. A comparator control method according to claim 1, characterized in that: The structure of the second preamplifier is consistent with that of the first preamplifier.

3. A comparator control method according to claim 2, characterized in that: The dynamic latch comparator includes field effect transistors M39 to M57, and the field effect transistors M39 to M42 are divided into two groups as transmission gate switches of the dynamic latch comparator, which are the seventh transmission gate switch and the eighth transmission gate switch, respectively. The seventh transmission gate switch includes field effect transistors M39 and M40, and the eighth transmission gate switch includes field effect transistors M41 and M42. The gates of the field effect transistors M39 and M41 are connected to the enable signal ENB, the gates of the field effect transistors M40 and M42 are connected to the enable signal ENC, and the gates of the field effect transistors M43, M46, M47, M52, and M53 are connected to the enable signal END; the field effect transistor M43 is a tail current tube; The field effect transistors M49~M51 are inverter cross-coupled structures, the field effect transistors M46, M47, M52 and M53 are reset transistors, and the gates are all connected to the enable signal END, the field effect transistors M49 and M51 are both NMOS transistors of cross-coupled inverters, the field effect transistors M48, M49, M50, and M51 form a cross-coupled inverter, the field effect transistors M54, M55, M56, and M57 respectively form inverters, and the output end VOUT is connected to the SAR control logic circuit.

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