Semiconductor device using hard mask and method for manufacturing the same

Abstract

The technology relates to a semiconductor device using a hard mask and a method for manufacturing the same, wherein the semiconductor device includes a hard mask that is easy to strip and can realize a fine pattern with high etching selectivity. According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming an etching target layer; forming a hard mask layer on the etching target layer, the hard mask layer including a first boron-doped silicon layer and a second boron-doped silicon layer on the first boron-doped silicon layer; and etching the etching target layer using the hard mask layer as an etching barrier layer, wherein the second boron-doped silicon layer has a greater boron concentration than the first boron-doped silicon layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0065815, filed on Jun. 1, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same using a hard mask. Background Art

[0004] As semiconductor devices become more highly integrated, pattern lines become narrower. However, using only photoresist, patterning may not be successful due to the limited resolution of the exposure system. Therefore, there is a need for a technology that uses a hard mask formed of a high etch selectivity material. Summary of the invention

[0005] According to an embodiment of the present disclosure, a semiconductor device including a high-selectivity, easily stripped hard mask and a method of manufacturing the semiconductor device are provided.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming an etching target layer; forming a hard mask layer on the etching target layer, the hard mask layer including a first boron-doped silicon layer and a second boron-doped silicon layer on the first boron-doped silicon layer; and etching the etching target layer using the hard mask layer as an etching barrier layer, wherein the second boron-doped silicon layer has a greater boron concentration than the first boron-doped silicon layer.

[0007] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a mold stack on a substrate; forming a hard mask layer on the mold stack, the hard mask layer including a first boron-doped silicon layer and a second boron-doped silicon layer on the first boron-doped silicon layer; etching the mold stack by using the hard mask layer as an etch barrier layer to form an opening exposing the substrate; and forming a lower electrode in the opening, wherein the second boron-doped silicon layer has a greater boron concentration than the first boron-doped silicon layer.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming an alternating stack, wherein insulating layers and sacrificial layers are alternately stacked on a substrate; forming a hard mask layer on the alternating stack, wherein the hard mask layer includes a first boron-doped silicon layer and a second boron-doped silicon layer on the first boron-doped silicon layer; etching the alternating stack by using the hard mask layer as an etch barrier to form a stack hole exposing the substrate; and forming a channel structure in the stack hole, wherein the second boron-doped silicon layer has a greater boron concentration than the first boron-doped silicon layer.

[0009] The second boron-doped silicon layer has a greater boron concentration than the first boron-doped silicon layer.

[0010] According to an embodiment of the present disclosure, a semiconductor device includes an etching target layer and a hard mask layer formed on the etching target layer, wherein the hard mask layer includes: a first boron-doped silicon layer having a gradient concentration of boron; and a second boron-doped silicon layer having a non-gradient concentration of boron.

[0011] The present technology includes a hard mask with high etch selectivity and easy stripping. Therefore, the etch profile can be formed vertically, and thus process stability and reliability can be obtained.

[0012] These and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art to which the present invention pertains from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 2A and Figure 2B is a graph showing boron doping concentration according to an embodiment of the present disclosure.

[0015] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F and Figure 4G is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 5H and Fig.5I is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0018] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F and Figure 6G is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Example cross-sectional views, plan views, and block diagrams may be used herein to describe embodiments of the present disclosure, and may be modified according to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure are not limited to the specific examples shown and described herein, but may include changes or modifications that do not depart from the scope of the present invention, including any changes and modifications to the described examples caused by manufacturing processes. Note that the various zones or regions shown in the drawings are schematically shown, and their shapes shown are provided only as examples, rather than limiting the scope of the present invention. It should also be noted that for illustrative purposes, the elements shown in the drawings may be magnified due to their thickness and spacing. Well-known components or elements that are not related to the subject matter of the present disclosure may be omitted from the description. Throughout the specification and the drawings, the same or substantially the same reference numerals are used to represent the same or substantially the same elements.

[0020] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. For ease of description, the description mainly focuses on dynamic random access memory (DRAM), but the inventive concept is not limited thereto but may be applied to other memories or semiconductor devices.

[0021] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 2A and Figure 2B is a graph showing a difference in boron concentration depending on a hard mask level according to an embodiment of the present disclosure.

[0023] refer to Figure 1, an etching target layer 11 can be provided. The etching target layer 11 can be a single layer. Alternatively, the etching target layer 11 can be a multilayer structure having at least two layers or more layers. The etching target layer 11 can be any suitable semiconductor substrate. For example, the etching target layer 11 can be a silicon substrate. The etching target layer 11 can be or include an undoped silicon (Si) or an amorphous silicon layer. The etching target layer 11 can be or include an oxide, a nitride, an oxynitride, or a combination thereof. The etching target layer 11 can be or include an insulating material. The etching target layer 11 can be or include silicon oxide. The etching target layer 11 can be or include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or tetraethyl orthosilicate (TEOS). The etching target layer 11 can be or include a stack of silicon oxide and silicon nitride. The etching target layer 11 can be or include an alternating stack of a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked.

[0024] A hard mask layer HM may be formed on the etch target layer 11. The hard mask layer HM may be formed to be in direct contact with the etch target layer 11. The hard mask layer HM may be formed to define at least one or more openings (not shown) in the etch target layer 11. The at least one or more openings may include a contact hole, a recess, a trench, a gap, or a combination thereof. The hard mask layer HM may have a multi-layer structure. Figure 1 In the embodiment shown, the hard mask layer HM may have a double-layer structure. The hard mask layer HM may include a first doped silicon layer 12 and a second doped silicon layer 13. The dopant in the first doped silicon layer and the second doped silicon layer may be boron. The first doped silicon layer 12 and the second doped silicon layer 13 may include two independent hard mask layers. The first doped silicon layer 12 and the second doped silicon layer 13 may be layers into which one hard mask layer HM is divided according to a concentration gradient of boron. For example, the hard mask layer HM may include a single doped silicon layer, which may have a dopant (e.g., boron) concentration gradient along its thickness direction. The thickness direction may be a stacking direction.

[0025] The hard mask layer HM may be formed of, for example, any one of polysilicon, an oxide film, a nitride film, or a combination thereof. According to one embodiment, the hard mask layer HM may be formed of polysilicon. The hard mask layer HM may be doped with a dopant. The dopant may be, for example, boron. The etching selectivity of the hard mask layer HM for the etching target layer 11 may increase as the concentration of the dopant increases. The hard mask layer HM may be a boron-doped layer. According to one embodiment, the hard mask layer HM may be a boron-doped silicon (Si) layer formed by doping a polysilicon layer with boron. The hard mask layer HM may be formed using, for example, B2H6 gas and SiH4 gas. In a variation of this embodiment, the hard mask layer HM may include an additional dopant. The additional dopant may be, for example, at least one selected from tungsten (W), carbon (C), nitrogen (N), or a combination thereof. For example, the hard mask layer HM may be a silicon layer doped with tungsten and boron. According to one embodiment, the hard mask layer HM may be a silicon layer doped with carbon and boron. According to one embodiment, the hard mask layer HM may be a silicon layer doped with tungsten, carbon, and boron.

[0026] The first doped silicon layer 12 may be or include a silicon layer doped with low concentration boron, and the second doped silicon layer 13 may be or include a silicon layer doped with high concentration boron. The first doped silicon layer 12 may have a first boron concentration, at which the stripping is performed faster than the second doped silicon layer 13. The second doped silicon layer 13 may have a second boron concentration, at which the etching selectivity of the etching target layer 11 is greater than that of the first doped silicon layer 12. In a variation of this embodiment, any one of the first doped silicon layer 12 and the second doped silicon layer 13 may also include an additional dopant. The additional dopant may be, for example, at least one selected from tungsten, carbon, nitrogen, or a combination thereof. For example, any one of the first doped silicon layer 12 or the second doped silicon layer 13 may be or include a silicon layer doped with tungsten and boron. Alternatively, according to one embodiment, any one of the first doped silicon layer 12 or the second doped silicon layer 13 may be or include a silicon layer doped with carbon and boron. According to one embodiment, any one of the first doped silicon layer 12 or the second doped silicon layer 13 may be or include a silicon layer doped with tungsten, carbon, and boron.

[0027] The hard mask layer HM may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In order to improve the deposition effect, the hard mask layer HM may use plasma. For example, the hard mask layer HM may be formed, for example, by plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD). According to one embodiment, the hard mask layer HM may be formed by PECVD using SiH4 gas and B2H6 gas.

[0028] The first doped silicon layer 12 may be formed on the etch target layer 11. The first doped silicon layer 12 may be formed to be in direct contact with the etch target layer 11. The first doped silicon layer 12 may include a bottom surface B1 and a top surface B2. The boron concentration at the bottom surface B1 of the first doped silicon layer 12 may be different from the boron concentration at the top surface B2 of the first doped silicon layer 12.

[0029] An example of the boron concentration of the first doped silicon layer 12 is Figure 2A . The first doped silicon layer 12 may include a gradient concentration of boron. The first doped silicon layer 12 may include a vertical gradient concentration of boron. The boron concentration of the first doped silicon layer 12 may be lowest at the bottom surface B1 of the first doped silicon layer 12, and may have a gradient doping profile, wherein the boron concentration of the first doped silicon layer 12 gradually increases as it moves away from the bottom surface B1 of the first doped silicon layer 12. Note that Figure 2A is a schematic simplified diagram, and the ratio P1 of the boron concentration of the first doped silicon layer 12 to the vertical distance from the bottom surface B1 thereof is not limited to that illustrated but may be changed with a different slope.

[0030] exist Figure 2B Another example of the boron concentration of the first doped silicon layer 12 is shown in FIG. Figure 2B , the first doped silicon layer 12 may include a multilayer stack of boron doped silicon layers. The boron concentration of the first doped silicon layer 12 may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 12 gradually increases from the lowest level of the boron doped silicon layer to the highest level of the boron doped silicon layer. According to one embodiment, the first doped silicon layer 12 may be a multilayer stack, which includes: a bottom layer, which is at a lowest level; an intermediate layer, which is at an intermediate level higher than the bottom layer; and a top layer, which is at a highest level higher than the intermediate layer. The boron concentration of the first doped silicon layer 12 may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 12 gradually increases from the bottom layer to the top layer. The ratio PB of the boron concentration of the bottom layer to its height HB may be the same as or different from the ratio PM of the boron concentration of the intermediate layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. For example, the ratio PB of the boron concentration of the bottom layer to its height HB may be greater than the ratio PM of the boron concentration of the intermediate layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. The ratio PM of the boron concentration of the middle layer to its height HC may be smaller than the ratio PB of the boron concentration of the bottom layer to its height HB and the ratio PT of the boron concentration of the top layer to its height HT. The height HB of the bottom layer, the height HC of the middle layer, and the height HT of the top layer may be the same or different from each other. For example, the height HB of the bottom layer may be smaller than the height HC of the middle layer and the height HT of the top layer. The height HC of the middle layer may be greater than the height HB of the bottom layer and the height HT of the top layer. It should be noted that Figure 2B1 is a simplified schematic example, and the ratio PB of the boron concentration of the bottom layer to its height HB, the ratio PM of the boron concentration of the middle layer to its height HC, and the ratio PT of the boron concentration of the top layer to its height HT of the first doped silicon layer 12 are not limited to those shown in this document, but may include different values. The height HB of the bottom layer, the height HC of the middle layer, and the height HT of the top layer of the first doped silicon layer 12 are not limited to those shown in the drawings, but may include different values.

[0031] The first doped silicon layer 12 may further include at least one additional dopant selected from, for example, tungsten, carbon, nitrogen, or a combination thereof. Thus, the first doped silicon layer 12 may be a silicon layer doped with tungsten and boron. According to one embodiment, the first doped silicon layer 12 may be a silicon layer doped with carbon and boron. According to one embodiment, the first doped silicon layer 12 may be a silicon layer doped with tungsten, carbon, and boron.

[0032] The second doped silicon layer 13 may be formed on the first doped silicon layer 12. The second doped silicon layer 13 may be formed to directly contact the first doped silicon layer 12. The thickness H2 of the second doped silicon layer 13 may be greater than the thickness H1 of the first doped silicon layer 12. The second doped silicon layer 13 may include a single boron-doped silicon layer. The thickness H2 of the single boron-doped silicon layer of the second doped silicon layer 13 may be greater than the thickness H1 of the multilayer stack of boron-doped silicon layers of the first doped silicon layer 12. The second doped silicon layer 13 may include a bottom surface B2 and a top surface T2. The bottom surface B2 of the second doped silicon layer 13 may represent the same surface as the top surface B2 of the first doped silicon layer 12. The bottom surface B2 of the second doped silicon layer 13 may have the same boron concentration as the top surface T2.

[0033] The boron concentration of the second doped silicon layer 13 may be greater than the boron concentration of the first doped silicon layer 12. The second doped silicon layer 13 may have a non-gradient concentration of boron. The second doped silicon layer 13 may include a non-vertical gradient concentration of boron. The boron concentration of the second doped silicon layer 13 may have a profile in which the boron concentration of the second doped silicon layer 13 is uniform from the bottom surface B2 to the top surface T2 of the second doped silicon layer 13. Figure 2A , the ratio P2 of the boron concentration of the second doped silicon layer 13 to the vertical distance H2 from the bottom surface B2 thereof may be constant. The boron concentration of the second doped silicon layer 13 may be continuous with the boron concentration of the first doped silicon layer 12. Therefore, the boron concentration at the bottom surface B2 of the second doped silicon layer 13 may be the same as the boron concentration at the highest level of the first doped silicon layer 12.

[0034] The second doped silicon layer 13 may further include at least one additional dopant selected from, for example, tungsten, carbon, nitrogen, or a combination thereof. Therefore, the second doped silicon layer 13 may be a silicon layer doped with tungsten and boron. According to one embodiment, the second doped silicon layer 13 may be a silicon layer doped with carbon and boron. According to one embodiment, the second doped silicon layer 13 may be a silicon layer doped with tungsten, carbon, and boron.

[0035] In the present embodiment, the second doped silicon layer 13 can be uniformly doped with a high concentration of boron, thereby increasing the etching selectivity for the etching target layer 11. Further, since the boron concentration of the first doped silicon layer 12 gradually increases with the increase of the distance from its bottom surface B1, the hard mask stripping can be easily performed. In other words, a hard mask layer HM with high etching selectivity and easy stripping can be formed by forming the second doped silicon layer 13 and the first doped silicon layer 12. Therefore, the etching profile of the etching target layer 11 can be formed vertically. When the etching profile is formed vertically, the process stability and reliability of the semiconductor device can be ensured.

[0036] FIG. 3A to FIG. 3E is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. According to one embodiment, a semiconductor device may include a semiconductor element having a contact plug.

[0037] refer to Figure 3A , a substrate 101 may be prepared. The substrate 101 may be made of or include any material suitable for a semiconductor process. The substrate 101 may include a semiconductor substrate. The substrate 101 may be formed of, for example, a silicon-containing material. The substrate 101 may be or include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof, and may be a single-layer or multi-layer structure thereof. The substrate 101 may be or include other semiconductor materials, such as germanium. The substrate 101 may be or include a compound semiconductor substrate, such as a IIIV semiconductor substrate, such as GaAs. The substrate 101 may be or include a silicon-on-insulator (SOI) substrate.

[0038] An interlayer insulating layer 102 may be formed on the substrate 101. The interlayer insulating layer 102 may be formed to directly contact the substrate 101. The interlayer insulating layer 102 may be or include an insulating material. The interlayer insulating layer 102 may be or include silicon oxide, silicon nitride, a low-k material, or a combination thereof. The interlayer insulating layer 102 may be or include a spin-on dielectric (SOD) material.

[0039] A hard mask layer 103 may be formed on the interlayer insulating layer 102. The hard mask layer 103 may be formed to directly contact the interlayer insulating layer 102. The hard mask layer 103 may be formed to define at least one or more openings in the interlayer insulating layer 102. The hard mask layer 103 may have a multi-layer structure. According to one embodiment, the hard mask layer 103 may have a double-layer structure. The hard mask layer 103 may include a first doped silicon layer 103G' and a second doped silicon layer 103S'. According to one embodiment, the first doped silicon layer 103G' and the second doped silicon layer 103S' may be defined in a single hard mask layer 103 according to their different doping concentrations. Alternatively, the first doped silicon layer 103G' and the second doped silicon layer 103S' may be two independent hard mask layers, that is, two hard mask layers that are formed separately and then doped with different amounts of boron.

[0040] The hard mask layer 103 may be formed of, for example, any one of polysilicon, an oxide film, a nitride film, or a combination thereof. According to one embodiment, the hard mask layer 103 may be formed of polysilicon. The hard mask layer 103 may be doped with a dopant. The etching selectivity of the hard mask layer 103 for the interlayer insulating layer 102 may increase as the concentration of the dopant increases. The hard mask layer 103 may be a boron-doped layer. According to one embodiment, the hard mask layer 103 may be a boron-doped silicon (Si) layer formed by doping a polysilicon layer with boron. The hard mask layer 103 may be formed using, for example, B2H6 gas and SiH4 gas. In a variation of this embodiment, the hard mask layer 103 may also include additional dopants. The additional dopant may be, for example, at least any one selected from tungsten (W), carbon (C), nitrogen (N), or a combination thereof. For example, the hard mask layer 103 may be a silicon layer doped with tungsten and boron. According to one embodiment, the hard mask layer 103 may be a silicon layer doped with carbon and boron. According to one embodiment, the hard mask layer 103 may be a silicon layer doped with tungsten, carbon, and boron.

[0041] The first doped silicon layer 103G' may be or include a silicon layer doped with low concentration boron, and the second doped silicon layer 103S' may be or include a silicon layer doped with high concentration boron. The first doped silicon layer 103G' may have a first boron concentration, at which the stripping is performed faster than the second doped silicon layer 103S'. The second doped silicon layer 103S' may have a second boron concentration, at which the etching selectivity of the interlayer insulating layer 102 is greater than that of the first doped silicon layer 103G'. In a variation of the present embodiment, any one of the first doped silicon layer 103G' and the second doped silicon layer 103S' may also include an additional dopant. The additional dopant may be, for example, at least one selected from tungsten, carbon, nitrogen, or a combination thereof. For example, any one of the first doped silicon layer 103G' or the second doped silicon layer 103S' may be or include a silicon layer doped with tungsten and boron. Alternatively, according to one embodiment, any one of the first doped silicon layer 103G' or the second doped silicon layer 103S' may be or include a silicon layer doped with carbon and boron. According to one embodiment, any one of the first doped silicon layer 103G' or the second doped silicon layer 103S' may be or include a silicon layer doped with tungsten, carbon, and boron.

[0042] The hard mask layer 103 may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In order to improve the deposition effect, the hard mask layer 103 may use plasma. For example, the hard mask layer 103 may be formed, for example, by plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD). According to one embodiment, the hard mask layer 103 may be formed by PECVD using SiH4 gas and B2H6 gas.

[0043] The first doped silicon layer 103G' may be formed on the interlayer insulating layer 102. The first doped silicon layer 103G' may include a bottom surface 103GB and a top surface 103SB. The boron concentration at the bottom surface 103GB of the first doped silicon layer 103G' may be different from the boron concentration at the top surface 103SB of the first doped silicon layer 103G'.

[0044] exist Figure 2A 103G'. The first doped silicon layer 103G' may include a gradient concentration of boron. The first doped silicon layer 103G' may include a vertical gradient concentration of boron. The boron concentration of the first doped silicon layer 103G' may be lowest at the bottom surface 103GB of the first doped silicon layer 103G' and may have a gradient doping profile, wherein the boron concentration of the first doped silicon layer 103G' gradually increases as it moves away from the bottom surface 103GB of the first doped silicon layer 103G'. Figure 2Ais a schematic simplified diagram, and the ratio P1 of the boron concentration of the first doped silicon layer 103G′ to the vertical distance from the bottom surface 103GB thereof is not limited to that shown in the figure but may be changed with a different slope.

[0045] exist Figure 2B . The first doped silicon layer 103G' may include a multilayer stack of boron-doped silicon layers. The boron concentration of the first doped silicon layer 103G' may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 103G' gradually increases from the lowest level of the boron-doped silicon layer to the highest level of the boron-doped silicon layer. According to one embodiment, the first doped silicon layer 103G' may be a multilayer stack, which includes: a bottom layer at a lowest level; an intermediate layer at an intermediate level higher than the bottom layer; and a top layer at a highest level higher than the intermediate layer. The boron concentration of the first doped silicon layer 103G' may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 103G' gradually increases from the bottom layer to the top layer. The ratio PB of the boron concentration of the bottom layer to its height HB may be equal to or different from the ratio PM of the boron concentration of the intermediate layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. For example, the ratio PB of the boron concentration of the bottom layer to its height HB may be greater than the ratio PM of the boron concentration of the middle layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. The ratio PM of the boron concentration of the middle layer to its height HC may be less than the ratio PB of the boron concentration of the bottom layer to its height HB and the ratio PT of the boron concentration of the top layer to its height HT. The height HB of the bottom layer, the height HC of the middle layer and the height HT of the top layer may be the same as or different from each other. For example, the height HB of the bottom layer may be less than the height HC of the middle layer and the height HT of the top layer. The height HC of the middle layer may be greater than the height HB of the bottom layer and the height HT of the top layer. It should be noted that Figure 2B 103G' is a simplified schematic example, and the ratio PB of the boron concentration of the bottom layer to its height HB, the ratio PM of the boron concentration of the middle layer to its height HC, and the ratio PT of the boron concentration of the top layer to its height HT of the first doped silicon layer 103G' are not limited to those illustrated therein, but may include different values. The height HB of the bottom layer, the height HC of the middle layer, and the height HT of the top layer of the first doped silicon layer 103G' are not limited to those illustrated in the drawings, but may include different values.

[0046] The first doped silicon layer 103G' may further include at least one additional dopant selected from tungsten, carbon, nitrogen or a combination thereof. Thus, the first doped silicon layer 103G' may be a silicon layer doped with tungsten and boron. According to one embodiment, the first doped silicon layer 103G' may be a silicon layer doped with carbon and boron. According to one embodiment, the first doped silicon layer 103G' may be a silicon layer doped with tungsten, carbon and boron.

[0047] The second doped silicon layer 103S' may be formed on the first doped silicon layer 103G' and may directly contact the first doped silicon layer 103G'. The thickness 103SH of the second doped silicon layer 103S' may be greater than the thickness 103GH of the first doped silicon layer 103G'. The second doped silicon layer 103S' may include a single boron-doped silicon layer. The thickness 103SH of the single boron-doped silicon layer of the second doped silicon layer 103S' may be greater than the thickness 103GH of the multilayer stack of boron-doped silicon layers of the first doped silicon layer 103G'. The second doped silicon layer 103S' may include a bottom surface 103SB and a top surface 103ST, and the bottom surface 103SB of the second doped silicon layer 103S' may represent the same surface as the top surface 103SB of the first doped silicon layer 103G'. The bottom surface 103SB of the second doped silicon layer 103S' may have the same boron concentration as the top surface 103ST.

[0048] The boron concentration of the second doped silicon layer 103S' may be greater than the boron concentration of the first doped silicon layer 103G'. The second doped silicon layer 103S' may have a non-gradient concentration of boron. The second doped silicon layer 103S' may include a non-vertical gradient concentration of boron. The boron concentration of the second doped silicon layer 103S' may have a profile in which the boron concentration of the second doped silicon layer 103S' is uniform from the bottom surface 103SB to the top surface 103ST of the second doped silicon layer 103S'. Reference Figure 2A , the ratio P2 of the boron concentration of the second doped silicon layer 103S' to the vertical distance 103SH from its bottom surface 103SB may be constant. The boron concentration of the second doped silicon layer 103S' may be continuous with the boron concentration of the first doped silicon layer 103G'. Therefore, the boron concentration at the bottom surface 103SB of the second doped silicon layer 103S' may be the same as the boron concentration at the highest level of the first doped silicon layer 103G'.

[0049] The second doped silicon layer 103S' may further include at least one additional dopant selected from tungsten, carbon, nitrogen or a combination thereof. Therefore, the second doped silicon layer 103S' may be a silicon layer doped with tungsten and boron. According to one embodiment, the second doped silicon layer 103S' may be a silicon layer doped with carbon and boron. According to one embodiment, the second doped silicon layer 103S' may be a silicon layer doped with tungsten, carbon and boron.

[0050] The contact mask 104 may be formed on the second doped silicon layer 103S' and may directly contact the second doped silicon layer 103S'. The contact mask 104 may include a photoresist pattern.

[0051] like Figure 3BAs shown, the contact mask 104 may be used as an etching mask to selectively remove the second doped silicon layer 103S' and the first doped silicon layer 103G'. Therefore, the second doped silicon layer 103S' may become a second boron-doped silicon pattern 103S. The first doped silicon layer 103G' may become a first boron-doped silicon pattern 103G. Through the etching process, a portion of the interlayer insulating layer 102 may be exposed.

[0052] like Figure 3C As shown, the contact mask 104 may be removed. The second boron-doped silicon pattern 103S may be thinned while the contact mask 104 is removed. In other words, the thickness of the second boron-doped silicon pattern 103S after the contact mask 104 is removed may be less than the thickness of the second boron-doped silicon pattern 103S before the contact mask 104 is removed.

[0053] like Figure 3D As shown, a contact hole 104H may be formed in the interlayer insulating layer 102. To form the contact hole 104H, the second boron-doped silicon pattern 103S and the first boron-doped silicon pattern 103G may be used as etching masks. While the contact hole 104H is formed, the second boron-doped silicon pattern 103S may be removed. The thickness of the first boron-doped silicon pattern 103G after the contact hole 104H is formed may be less than the thickness of the first boron-doped silicon pattern 103G before the contact hole 104H is formed.

[0054] Through the above-mentioned etching process, a plurality of contact holes 104H can be formed. Different contact holes 104H can be formed according to the difficulty of the etching process. For example, when the boron concentration of the first doped silicon layer 103G' is reduced, the stripping of the first doped silicon layer 103G' can be easier. Therefore, the sidewall 103W of the first boron-doped silicon pattern 103G can be formed vertically. When the sidewall 103W of the first boron-doped silicon pattern 103G is formed vertically, the sidewall of the contact hole 104H can be formed vertically. Since the sidewall of the contact hole 104H is formed vertically, poor contact of the contact plug can be prevented, and the gap can be increased. In order to form the contact hole 104H, dry etching, wet etching or a combination thereof can be used. The contact hole 104H can have a high aspect ratio. The contact hole 104H can have an aspect ratio of at least 1:1 or more.

[0055] like Figure 3E As shown, the first boron-doped silicon pattern 103G may be removed. Subsequently, a contact plug layer (not shown) may be formed to cover the contact hole 104H and the interlayer insulating layer 102. The contact plug layer (not shown) may be polished until the top surface of the interlayer insulating layer 102 is exposed, thereby forming a contact plug 105 in the contact hole 104H.

[0056] In the present embodiment, the second doped silicon layer 103S' can be uniformly doped with a high concentration of boron, thereby increasing its etching selectivity for the interlayer insulating layer 102. Further, since the boron concentration gradually increases with the distance from the bottom surface 103GB of the first doped silicon layer 103G', hard mask stripping can be easily performed. In other words, a hard mask layer with high etching selectivity and easy stripping can be formed by forming the second doped silicon layer 103S' and the first doped silicon layer 103G'. Therefore, the etching profile of the interlayer insulating layer 102 can be formed vertically. Since the etching profile is formed vertically, the process stability and reliability of the semiconductor device can be ensured.

[0057] FIG. 4A to FIG. 4G is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. According to one embodiment, a semiconductor device may include a semiconductor element having a capacitor.

[0058] refer to Figure 4A , an interlayer insulating layer 202 may be formed on the substrate 201. A contact plug 203 may be formed to pass through the interlayer insulating layer 202. The contact plug 203 may pass through the interlayer insulating layer 202 and be connected to the substrate 201. Although not shown, before forming the contact plug 203, a cell transistor, a bit line contact plug, and a bit line may also be formed.

[0059] The substrate 201 may include any material suitable for semiconductor processes. The substrate 201 may include a semiconductor substrate. The substrate 201 may be formed of, for example, a silicon-containing material. The substrate 201 may be or include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, and may be a single layer or multilayer structure thereof. The substrate 201 may be or include other semiconductor materials, such as germanium. The substrate 201 may be or include a compound semiconductor substrate, such as a II-IV semiconductor substrate, such as GaAs. The substrate 201 may be or include a silicon-on-insulator (SOI) substrate.

[0060] The interlayer insulating layer 202 may be or include silicon oxide, silicon nitride, or a combination thereof. The interlayer insulating layer 202 may be or include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS), undoped silicate glass (USG), or spin-on glass (SOG).

[0061] In order to form the contact plug 203, the interlayer insulating layer 202 may be etched to form a contact hole (reference numerals omitted), and the contact hole may be filled with a conductive material. The contact plug 203 may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. For example, polysilicon, metal silicide, and metal may be stacked in sequence for the contact plug 203.

[0062] An etch stop layer 204 may be formed on the contact plug 203 and the interlayer insulating layer 202. The etch stop layer 204 may be formed of a material having an etching selectivity to the mold layer 205. The etch stop layer 204 may be or include silicon nitride. When etching the mold layer 205, the etch stop layer 204 may be used as an etching endpoint. The etch stop layer 204 may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In order to improve the deposition effect, the etch stop layer 204 may use plasma. In other words, the etch stop layer 204 may be formed, for example, by PECVD or PEALD.

[0063] A mold layer 205 may be formed on the etch stop layer 204. The mold layer 205 may be or include an insulating material. The mold layer 205 may be or include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or tetraethyl orthosilicate (TEOS). The mold layer 205 may be a single layer. Alternatively, the mold layer 205 may have a multilayer structure having at least two or more layers. For example, a BPSG layer and a TEOS layer may be stacked. In another embodiment, the mold layer 205 may be or include an undoped silicon layer or an amorphous silicon layer.

[0064] A hard mask layer 206 may be formed on the mold layer 205. The hard mask layer 206 may be formed to define at least one or more openings in the mold layer 205. The hard mask layer 206 may have a multi-layer structure. According to one embodiment, the hard mask layer 206 may have a double-layer structure. The hard mask layer 206 may include a first doped silicon layer 206G' and a second doped silicon layer 206S'. The dopant in the first doped silicon layer and the second doped silicon layer may be boron. According to one embodiment, although the first doped silicon layer 206G' and the second doped silicon layer 206S' are separated from each other for the purpose of describing the hard mask layer 206, the first doped silicon layer 206G' and the second doped silicon layer 206S' may be layers into which one hard mask layer 206 is divided according to a concentration gradient of boron. Alternatively, the first doped silicon layer 206G' and the second doped silicon layer 206S' may include two independent hard mask layers.

[0065] The hard mask layer 206 may be formed of, for example, any one of polysilicon, an oxide film, a nitride film, or a combination thereof. According to one embodiment, the hard mask layer 206 may be formed of polysilicon. The hard mask layer 206 may be doped with a dopant. The etching selectivity of the hard mask layer 206 for the mold layer 205 may increase as the dopant concentration increases. The hard mask layer 206 may be a boron-doped layer. According to one embodiment, the hard mask layer 206 may be a boron-doped silicon (Si) layer formed by doping a polysilicon layer with boron. The hard mask layer 206 may be formed using, for example, B2H6 gas and SiH4 gas. In a variation of this embodiment, the hard mask layer 206 may further include additional dopants. The additional dopant may be, for example, at least any one selected from tungsten (W), carbon (C), nitrogen (N), or a combination thereof. For example, the hard mask layer 206 may be a silicon layer doped with tungsten and boron. According to one embodiment, the hard mask layer 206 may be a silicon layer doped with carbon and boron. According to one embodiment, the hard mask layer 206 may be a silicon layer doped with tungsten, carbon, and boron.

[0066] The first doped silicon layer 206G' may be or include a silicon layer doped with low concentration boron, and the second doped silicon layer 206S' may be or include a silicon layer doped with high concentration boron. The first doped silicon layer 206G' may have a first boron concentration, at which the stripping is performed faster than the second doped silicon layer 206S'. The second doped silicon layer 206S' may have a second boron concentration, at which the etching selectivity for the mold layer 205 is greater than that of the first doped silicon layer 206G'. In a variation of this embodiment, any one of the first doped silicon layer 206G' and the second doped silicon layer 206S' may further include an additional dopant. The additional dopant may be, for example, at least any one selected from tungsten, carbon, nitrogen, or a combination thereof. For example, any one of the first doped silicon layer 206G' or the second doped silicon layer 206S' may be or include a silicon layer doped with tungsten and boron. Alternatively, according to one embodiment, any one of the first doped silicon layer 206G' or the second doped silicon layer 206S' may be or include a silicon layer doped with carbon and boron. According to one embodiment, any one of the first doped silicon layer 206G' or the second doped silicon layer 206S' may be or include a silicon layer doped with tungsten, carbon, and boron.

[0067] The hard mask layer 206 may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In order to improve the deposition effect, the hard mask layer 206 may use plasma. For example, the hard mask layer 206 may be formed, for example, by plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD). According to one embodiment, the hard mask layer 206 may be formed by PECVD using SiH4 gas and B2H6 gas.

[0068] The first doped silicon layer 206G' may be formed on the mold layer 205. The first doped silicon layer 206G' may include a bottom surface 206GB and a top surface 206SB. The boron concentration at the bottom surface 206GB of the first doped silicon layer 206G' may be different from the boron concentration at the top surface 206SB of the first doped silicon layer 206G'.

[0069] exist Figure 2A 206G'. The first doped silicon layer 206G' may include a gradient concentration of boron. The first doped silicon layer 206G' may include a vertical gradient concentration of boron. The boron concentration of the first doped silicon layer 206G' may be lowest at the bottom surface 206GB of the first doped silicon layer 206G' and may have a gradient doping profile, wherein the boron concentration of the first doped silicon layer 206G' gradually increases as it moves away from the bottom surface 206GB of the first doped silicon layer 206G'. Figure 2A 2 is a schematic simplified diagram, and the ratio P1 of the boron concentration of the first doped silicon layer 206G′ to the vertical distance from the bottom surface 206GB thereof is not limited to that shown, but may be changed with a different slope.

[0070] exist Figure 2B. The first doped silicon layer 206G' may include a multilayer stack of boron-doped silicon layers. The boron concentration of the first doped silicon layer 206G' may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 206G' gradually increases from the lowest level of the boron-doped silicon layer to the highest level of the boron-doped silicon layer. According to one embodiment, the first doped silicon layer 206G' may be a multilayer stack, which includes: a bottom layer at a lowest level; an intermediate layer at an intermediate level higher than the bottom layer; and a top layer at a highest level higher than the intermediate layer. The boron concentration of the first doped silicon layer 206G' may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 206G' gradually increases from the bottom layer to the top layer. The ratio PB of the boron concentration of the bottom layer to its height HB may be equal to or different from the ratio PM of the boron concentration of the intermediate layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. For example, the ratio PB of the boron concentration of the bottom layer to its height HB may be greater than the ratio PM of the boron concentration of the middle layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. The ratio PM of the boron concentration of the middle layer to its height HC may be less than the ratio PB of the boron concentration of the bottom layer to its height HB and the ratio PT of the boron concentration of the top layer to its height HT. The height HB of the bottom layer, the height HC of the middle layer and the height HT of the top layer may be the same as or different from each other. For example, the height HB of the bottom layer may be less than the height HC of the middle layer and the height HT of the top layer. The height HC of the middle layer may be greater than the height HB of the bottom layer and the height HT of the top layer. It should be noted that Figure 2B 206G' is a simplified schematic example, and the height HB of the bottom layer, the height HC of the middle layer, and the height HT of the top layer of the first doped silicon layer 206G' are not limited to those illustrated in the drawings, but may include different values. The ratio PB of the boron concentration of the bottom layer to its height HB, the ratio PM of the boron concentration of the middle layer to its height HC, and the ratio PT of the boron concentration of the top layer to its height HT of the first doped silicon layer 206G' are not limited to those illustrated therein, but may include different values.

[0071] The first doped silicon layer 206G' may further include at least one additional dopant selected from tungsten, carbon, nitrogen, or a combination thereof. Thus, the first doped silicon layer 206G' may be a silicon layer doped with tungsten and boron. According to one embodiment, the first doped silicon layer 206G' may be a silicon layer doped with carbon and boron. According to one embodiment, the first doped silicon layer 206G' may be a silicon layer doped with tungsten, carbon, and boron.

[0072] The second doped silicon layer 206S' may be formed on the first doped silicon layer 206G'. The thickness 206SH of the second doped silicon layer 206S' may be greater than the thickness 206GH of the first doped silicon layer 206G'. The second doped silicon layer 206S' may include a single boron-doped silicon layer. The thickness 206SH of the single boron-doped silicon layer of the second doped silicon layer 206S' may be greater than the thickness 206GH of the multilayer stack of boron-doped silicon layers of the first doped silicon layer 206G'. The second doped silicon layer 206S' may include a bottom surface 206SB and a top surface 206ST, and the bottom surface 206SB of the second doped silicon layer 206S' may represent the same surface as the top surface 206SB of the first doped silicon layer 206G'. The bottom surface 206SB of the second doped silicon layer 206S' may have the same boron concentration as the top surface 206ST.

[0073] The boron concentration of the second doped silicon layer 206S' may be greater than the boron concentration of the first doped silicon layer 206G'. The second doped silicon layer 206S' may have a non-gradient concentration of boron. The second doped silicon layer 206S' may include a non-vertical gradient concentration of boron. The boron concentration of the second doped silicon layer 206S' may have a profile in which the boron concentration of the second doped silicon layer 206S' is uniform from the bottom surface 206SB to the top surface 206ST of the second doped silicon layer 206S'. Figure 2A , the ratio P2 of the boron concentration of the second doped silicon layer 206S' to the vertical distance 206SH from its bottom surface 206SB can be constant. The boron concentration of the second doped silicon layer 206S' can be continuous with the boron concentration of the first doped silicon layer 206G'. Therefore, the boron concentration at the bottom surface 206SB of the second doped silicon layer 206S' can be the same as the boron concentration at the highest level of the first doped silicon layer 206G'.

[0074] The second doped silicon layer 206S' may further include at least one additional dopant selected from tungsten, carbon, nitrogen or a combination thereof. Thus, the second doped silicon layer 206S' may be a silicon layer doped with tungsten and boron. According to one embodiment, the second doped silicon layer 206S' may be a silicon layer doped with carbon and boron. According to one embodiment, the second doped silicon layer 206S' may be a silicon layer doped with tungsten, carbon and boron.

[0075] An opening mask 207 may be formed on the second doped silicon layer 206S'. The opening mask 207 may include a photoresist pattern.

[0076] like Figure 4BAs shown in , the opening mask 207 can be used as an etching mask to selectively remove the second doped silicon layer 206S' and the first doped silicon layer 206G'. Therefore, the second doped silicon layer 206S' can become a second boron-doped silicon pattern 206S. The first doped silicon layer 206G' can become a first boron-doped silicon pattern 206G. Through the etching process, a portion of the mold layer 205 can be exposed.

[0077] like Figure 4C As shown, the opening mask 207 may be removed. The second boron-doped silicon pattern 206S may be thinned while the opening mask 207 is removed. In other words, the thickness of the second boron-doped silicon pattern 206S after the opening mask 207 is removed may be less than the thickness of the second boron-doped silicon pattern 206S before the opening mask 207 is removed.

[0078] refer to Figure 4D , an opening 208 may be formed in the mold layer 205. The opening 208 may be formed by etching the mold layer 205 using the second boron-doped silicon pattern 206S and the first boron-doped silicon pattern 206G as an etching mask. While the opening 208 is formed, the second boron-doped silicon pattern 206S may be removed. The thickness of the first boron-doped silicon pattern 206G after the opening 208 is formed may be less than the thickness of the first boron-doped silicon pattern 206G before the opening 208 is formed. The opening 208 may be formed on the contact plug 203. The opening 208 may be referred to as a hole where a lower electrode (or storage node) is to be formed. The etching process for forming the opening 208 may stop at the etch stop layer 204. Subsequently, the etch stop layer 204 may be etched to expose the top surface of the contact plug 203 below the opening 208.

[0079] Through the above-mentioned etching process, a plurality of openings 208 may be formed. Various openings 208 may be formed according to the difficulty of the etching process. For example, when the boron concentration of the first doped silicon layer 206G' is reduced, the stripping of the first doped silicon layer 206G' may be easier. Therefore, the sidewall 206W of the first boron-doped silicon pattern 206G may be formed vertically. When the sidewall 206W of the first boron-doped silicon pattern 206G is formed vertically, the sidewall of the opening 208 may be formed vertically. Since the sidewall of the opening 208 may be formed vertically, the poor contact with the contact plug 203 may be alleviated, and the capacitance of the capacitor may be increased. In order to form the opening 208, dry etching, wet etching, or a combination thereof may be used. The opening 208 may have a high aspect ratio. The opening 208 may have an aspect ratio of at least 1:1 or greater. For example, the opening 208 may have a high aspect ratio of 10:1 or greater.

[0080] like Figure 4EAs shown, the first boron-doped silicon pattern 206G may be removed. Subsequently, a lower electrode layer (not shown) may be formed to cover the opening 208 and the mold layer 205. The lower electrode layer (not shown) may be formed on the contact plug 203. Therefore, the lower electrode layer (not shown) may be electrically connected to the contact plug 203. The lower electrode layer (not shown) may include a metal, a metal nitride, or a combination thereof. The lower electrode layer (not shown) may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum, titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and at least one of a combination thereof. According to one embodiment, the lower electrode layer (not shown) may include titanium nitride (TiN). The lower electrode layer (not shown) may include titanium nitride (ALD-TiN) formed by ALD.

[0081] Subsequently, a lower electrode separation process may be performed. For example, in order to form the lower electrode 209 in the opening 208, a portion of the lower electrode layer (not shown) may be selectively removed. The lower electrode separation process may be performed by polishing. For example, the lower electrode 209 may be formed by performing chemical mechanical polishing (CMP) or etching back on the lower electrode layer (not shown). After the lower electrode 209 is formed, the top surface of the mold layer 205 may be exposed. Therefore, the lower electrode 209 may be formed in the opening 208. The lower electrode 209 may include any of the shapes of a column, a cylindrical column, or a composite column (pylinder). In the present embodiment, the lower electrode 209 may be columnar. The lower electrode 209 may have a high aspect ratio. The lower electrode 209 may have an aspect ratio of 10:1 or greater.

[0082] like Figure 4F As shown, the mold layer 205 may be removed. For example, the mold layer 205 may be removed by a wet deep-out process. To remove the mold layer 205, one or more of HF, NH4F / NH4OH, H2O2, HCl, HNO3, H2SO4, or such chemical substances may be used. When removing the mold layer 205, the etch stop layer 204 having an etch selectivity to the mold layer 205 may not be removed. When the mold layer 205 is removed, the outer wall of the lower electrode 209 may be exposed.

[0083] like Figure 4GAs shown in , a dielectric layer 210 may be formed on the lower electrode 209 and the etch stop layer 204. The dielectric layer 210 may be or include a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) or strontium titanium oxide (SrTiO3). Alternatively, the dielectric layer 210 may be formed of a composite layer including two or more layers of the above-mentioned high-k materials. According to one embodiment, the dielectric layer 210 may be formed of a zirconium oxide-based material, which may substantially reduce the equivalent oxide thickness (EOT) while providing good leakage current characteristics. For example, the dielectric layer 210 may include any one of the following: ZAZ (ZrO2 / Al2O3 / ZrO2), TZAZ (TiO2 / ZrO2 / Al2O3 / ZrO2), TZAZT (TiO2 / ZrO2 / Al2O3 / ZrO2 / TiO2), ZAZT (ZrO2 / Al2O3 / ZrO2 / TiO2), TZ (TiO2 / ZrO2), or ZAZAT (ZrO2 / Al2O3 / ZrO2 / Al2O3 / TiO2). In a dielectric layer stack such as TZAZ, TZAZT, ZAZT, TZ, or ZAZAT, Ta2O5 may be used instead of TiO2. The dielectric layer 210 may be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD) with excellent step coverage.

[0084] The upper electrode 211 may be formed on the dielectric layer 210. The upper electrode 211 may include a metal-based material. For example, the upper electrode 211 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and combinations thereof. The upper electrode 211 may be formed using low pressure CVD (LPCVD), PECVD, or ALD. According to one embodiment, the upper electrode 211 may include titanium nitride (ALD-TIN) formed by ALD.

[0085] Alternatively, the upper electrode 211 may have a multilayer structure. The upper electrode 211 may also be formed by sequentially stacking a lower metal-containing layer, a silicon germanium layer, and an upper metal-containing layer. The lower metal-containing layer and the upper metal-containing layer may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and a combination thereof. For example, the lower metal-containing layer may be a titanium nitride layer, and the upper metal-containing layer may be a WN / W stack of tungsten nitride and tungsten. The silicon germanium layer may be doped with boron. In order to form the upper electrode 211, an upper electrode layer (not shown) deposition and an upper electrode patterning may be performed.

[0086] In the present embodiment, the second doped silicon layer 206S' can be uniformly doped with a high concentration of boron, thereby increasing its etching selectivity for the mold layer 205. Further, since the boron concentration of the first doped silicon layer 206G' gradually increases with the increase of the distance from its bottom surface 206GB, hard mask stripping can be easily performed. In other words, a hard mask layer with high etching selectivity and easy stripping can be formed by forming the second doped silicon layer 206S' and the first doped silicon layer 206G'. Therefore, the etching profile of the mold layer 205 can be formed vertically. When the etching profile is formed vertically, process stability and reliability for the semiconductor device can be ensured.

[0087] FIG. 5A to FIG. 5I is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. According to one embodiment, a semiconductor device may include a semiconductor element including a capacitor and a support member.

[0088] refer to Figure 5A , an interlayer insulating layer 202 may be formed on the substrate 201. A contact plug 203 may be formed to pass through the interlayer insulating layer 202. The contact plug 203 may pass through the interlayer insulating layer 202 and be connected to the substrate 201.

[0089] An etch stop layer 204 may be formed on the contact plug 203 and the interlayer insulating layer 202. The etch stop layer 204 may be or include silicon nitride. The etch stop layer 204 may be used as an etching endpoint. The etch stop layer 204 may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In order to improve the deposition effect, the etch stop layer 204 may use plasma. For example, the etch stop layer 204 may be formed by, for example, plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD).

[0090] A mold stack layer ML may be formed on the contact plug 203 and the interlayer insulating layer 202. The mold stack ML may include one or more support member layers. According to one embodiment, the mold stack ML may include two support member layers. However, the embodiments of the present disclosure are not limited thereto. For example, the mold stack ML may include only one support member layer or include three or more support member layers. According to one embodiment, the mold stack ML may include an etch stop layer 204, a lower mold layer 221, a lower support member layer 222', an upper mold layer 223, and an upper support member layer 224'. The height of the lower electrode may vary according to the thickness of the mold stack ML. The capacitance of the capacitor may vary according to the height of the lower electrode. For example, when the height of the mold stack ML increases, the capacitance of the capacitor may increase.

[0091] The lower mold layer 221 may be formed on the etch stop layer 204. The lower mold layer 221 may be or include an insulating material. The lower mold layer 221 may be or include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or tetraethyl orthosilicate (TEOS). The lower mold layer 221 may be a single layer. Alternatively, the lower mold layer 221 may have a multilayer structure having at least two layers or more layers. For example, a BPSG layer and a TEOS layer may be stacked.

[0092] The lower-level support member layer 222' may be formed on the lower-level mold layer 221. The thickness of the lower-level support member layer 222' may be less than the thickness of the lower-level mold layer 221. The difficulty of the etching process may be reduced according to the thickness of the lower-level support member layer 222'. For example, when the thickness of the lower-level support member layer 222' is reduced, the difficulty of the etching process may be reduced. When the difficulty of the etching process is reduced, the capacitance of the capacitor may increase. The lower-level support member layer 222' may be formed of a material having an etching selectivity to the lower-level mold layer 221. The lower-level support member layer 222' may include a nitrogen-containing material. The lower-level support member layer 222' may be or include silicon nitride, silicon carbonitride (SiCN), or a combination thereof.

[0093] The upper mold layer 223 may be formed on the lower support member layer 222'. The upper mold layer 223 may be or include an insulating material. The upper mold layer 223 may be or include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or tetraethyl orthosilicate (TEOS). The upper mold layer 223 may include the same or different material as the lower mold layer 221. The upper mold layer 223 may be a single layer. Alternatively, the upper mold layer 223 may have a multilayer structure having at least two layers or more layers. For example, a BPSG layer and a TEOS layer may be stacked. The thickness of the upper mold layer 223 may be the same as or different from the thickness of the lower mold layer 221. For example, the thickness of the upper mold layer 223 may be equal to or less than the thickness of the lower mold layer 221.

[0094] The upper support member layer 224' may be formed on the upper mold layer 223. The thickness of the upper support member layer 224' may be less than the thickness of the upper mold layer 223. The thickness of the upper support member layer 224' may be the same as or different from the thickness of the lower support member layer 222'. For example, the thickness of the upper support member layer 224' may be greater than the thickness of the lower support member layer 222'. The upper support member layer 224' may be formed of a material having an etching selectivity to the upper mold layer 223. The upper support member layer 224' may include a nitrogen-containing material. The upper support member layer 224' may be or include silicon nitride, silicon carbonitride (SiCN), silicon boron nitride (SiBN), or a combination thereof. The upper support member layer 224' may include a material that is the same as or different from the lower support member layer 222'.

[0095] A hard mask layer 225 may be formed on the upper support member layer 224'. The hard mask layer 225 may be formed to define at least one or more openings in the mold stack ML. The hard mask layer 225 may have a multi-layer structure. According to one embodiment, the hard mask layer 225 may have a double-layer structure. The hard mask layer 225 may include a first doped silicon layer 225G' and a second doped silicon layer 225S'. The dopant in the first doped silicon layer 225G' and the second doped silicon layer 225S' may be boron. According to one embodiment, the first doped silicon layer 225G' and the second doped silicon layer 225S' may be layers into which one hard mask layer 225 is divided according to a concentration gradient of boron. Alternatively, the first doped silicon layer 225G' and the second doped silicon layer 225S' may include two independent hard mask layers.

[0096] The hard mask layer 225 may be formed of, for example, any one of polysilicon, an oxide film, a nitride film, or a combination thereof. According to one embodiment, the hard mask layer 225 may be formed of polysilicon. The hard mask layer 225 may be doped with a dopant. The etching selectivity of the hard mask layer 225 for the mold stack ML may increase as the concentration of the dopant increases. The hard mask layer 225 may be a boron-doped layer. According to one embodiment, the hard mask layer 225 may be a boron-doped silicon (Si) layer formed by doping a polysilicon layer with boron. The hard mask layer 225 may be formed using, for example, B2H6 gas and SiH4 gas. In a variation of this embodiment, the hard mask layer 225 may further include additional dopants. The additional dopant may be, for example, at least any one selected from tungsten (W), carbon (C), nitrogen (N), or a combination thereof. For example, the hard mask layer 225 may be a silicon layer doped with tungsten and boron. According to one embodiment, the hard mask layer 225 may be a silicon layer doped with carbon and boron. According to one embodiment, the hard mask layer 225 may be a silicon layer doped with tungsten, carbon, and boron.

[0097] The first doped silicon layer 225G' may be or include a silicon layer doped with low concentration boron, and the second doped silicon layer 225S' may be or include a silicon layer doped with high concentration boron. The first doped silicon layer 225G' may have a first boron concentration at which stripping is performed faster than the second doped silicon layer 225S'. The second doped silicon layer 225S' may have a second boron concentration at which its etching selectivity for the mold stack ML is greater than that of the first doped silicon layer 225G'. In a variation of this embodiment, any one of the first doped silicon layer 225G' and the second doped silicon layer 225S' may further include an additional dopant. The additional dopant may be, for example, at least any one selected from tungsten, carbon, nitrogen, or a combination thereof. For example, any one of the first doped silicon layer 225G' or the second doped silicon layer 225S' may be or include a silicon layer doped with tungsten and boron. Alternatively, according to one embodiment, any one of the first doped silicon layer 225G' or the second doped silicon layer 225S' may be or include a silicon layer doped with carbon and boron. According to one embodiment, any one of the first doped silicon layer 225G' or the second doped silicon layer 225S' may be or include a silicon layer doped with tungsten, carbon, and boron.

[0098] The hard mask layer 225 may be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In order to improve the deposition effect, the hard mask layer 225 may use plasma. For example, the hard mask layer 225 may be formed by, for example, plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD). According to one embodiment, the hard mask layer 225 may be formed by PECVD using SiH4 gas and B2H6 gas.

[0099] The first doped silicon layer 225G' may be formed on the upper support layer 224'. The first doped silicon layer 225G' may include a bottom surface 225GB and a top surface 225SB. The boron concentration at the bottom surface 225GB of the first doped silicon layer 225G' may be different from the boron concentration at the top surface 225SB of the first doped silicon layer 225G'.

[0100] exist Figure 2A 2. The boron concentration of the first doped silicon layer 225G' is shown in FIG. The first doped silicon layer 225G' may include a gradient concentration of boron. The first doped silicon layer 225G' may include a vertical gradient concentration of boron. The boron concentration of the first doped silicon layer 225G' may be lowest at the bottom surface 225GB of the first doped silicon layer 225G' and may have a gradient doping profile, wherein the boron concentration of the first doped silicon layer 225G' gradually increases as it moves away from the bottom surface 225GB of the first doped silicon layer 225G'. Figure 2A 2 is a schematic simplified diagram, and the ratio P1 of the boron concentration of the first doped silicon layer 225G′ to the vertical distance from the bottom surface 225GB thereof is not limited to that shown, but may be changed with a different slope.

[0101] exist Figure 2B. The first doped silicon layer 225G' may include a multilayer stack of boron-doped silicon layers. The boron concentration of the first doped silicon layer 225G' may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 225G' gradually increases from the lowest level of the boron-doped silicon layer to the highest level of the boron-doped silicon layer. According to one embodiment, the first doped silicon layer 225G' may be a multilayer stack, which includes: a bottom layer at a lowest level; an intermediate layer at an intermediate level higher than the bottom layer; and a top layer at a highest level higher than the intermediate layer. The boron concentration of the first doped silicon layer 225G' may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 225G' gradually increases from the bottom layer to the top layer. The ratio PB of the boron concentration of the bottom layer to its height HB may be the same as or different from the ratio PM of the boron concentration of the intermediate layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. For example, the ratio PB of the boron concentration of the bottom layer to its height HB may be greater than the ratio PM of the boron concentration of the middle layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. The ratio PM of the boron concentration of the middle layer to its height HC may be less than the ratio PB of the boron concentration of the bottom layer to its height HB and the ratio PT of the boron concentration of the top layer to its height HT. The height HB of the bottom layer, the height HC of the middle layer and the height HT of the top layer may be the same as or different from each other. For example, the height HB of the bottom layer may be less than the height HC of the middle layer and the height HT of the top layer. The height HC of the middle layer may be greater than the height HB of the bottom layer and the height HT of the top layer. It should be noted that Figure 2B 2 is a simplified schematic example, and the height HB of the bottom layer, the height HC of the middle layer, and the height HT of the top layer of the first doped silicon layer 225G' are not limited to those shown in the drawings, but may include different values. The ratio PB of the boron concentration of the bottom layer to its height HB, the ratio PM of the boron concentration of the middle layer to its height HC, and the ratio PT of the boron concentration of the top layer to its height HT of the first doped silicon layer 225G' are not limited to those shown therein, but may include different values.

[0102] The first doped silicon layer 225G' may further include at least one additional dopant selected from tungsten, carbon, nitrogen, or a combination thereof. Thus, the first doped silicon layer 225G' may be a silicon layer doped with tungsten and boron. According to one embodiment, the first doped silicon layer 225G' may be a silicon layer doped with carbon and boron. According to one embodiment, the first doped silicon layer 225G' may be a silicon layer doped with tungsten, carbon, and boron.

[0103] The second doped silicon layer 225S' may be formed on the first doped silicon layer 225G'. The thickness 225SH of the second doped silicon layer 225S' may be greater than the thickness 225GH of the first doped silicon layer 225G'. The second doped silicon layer 225S' may include a single boron-doped silicon layer. The thickness 225SH of the single boron-doped silicon layer of the second doped silicon layer 225S' may be greater than the thickness 225GH of the multilayer stack of boron-doped silicon layers of the first doped silicon layer 225G'. The second doped silicon layer 225S' may include a bottom surface 225SB and a top surface 225ST, and the bottom surface 225SB of the second doped silicon layer 225S' may represent the same surface as the top surface 225SB of the first doped silicon layer 225G'. The bottom surface 225SB of the second doped silicon layer 225S' may have the same boron concentration as the top surface 225ST.

[0104] The boron concentration of the second doped silicon layer 225S' may be greater than the boron concentration of the first doped silicon layer 225G'. The second doped silicon layer 225S' may have a non-gradient concentration of boron. The second doped silicon layer 225S' may include a non-vertical gradient concentration of boron. The boron concentration of the second doped silicon layer 225S' may have a profile in which the boron concentration of the second doped silicon layer 225S' is uniform from the bottom surface 225SB to the top surface 225ST of the second doped silicon layer 225S'. Figure 2A , the ratio P2 of the boron concentration of the second doped silicon layer 225S' to the vertical distance 225SH from its bottom surface 225SB can be constant. The boron concentration of the second doped silicon layer 225S' can be continuous with the boron concentration of the first doped silicon layer 225G'. Therefore, the boron concentration at the bottom surface 225SB of the second doped silicon layer 225S' can be the same as the boron concentration at the highest level of the first doped silicon layer 225G'.

[0105] The second doped silicon layer 225S' may further include at least one additional dopant selected from tungsten, carbon, nitrogen, or a combination thereof. Therefore, the second doped silicon layer 225S' may be a silicon layer doped with tungsten and boron. According to one embodiment, the second doped silicon layer 225S' may be a silicon layer doped with carbon and boron. According to one embodiment, the second doped silicon layer 225S' may be a silicon layer doped with tungsten, carbon, and boron.

[0106] An opening mask 226 may be formed on the second doped silicon layer 225S'. The opening mask 226 may include a photoresist pattern.

[0107] like Figure 5BAs shown, the opening mask 226 can be used as an etching mask to selectively remove the second doped silicon layer 225S' and the first doped silicon layer 225G'. Therefore, the second doped silicon layer 225S' can become a second boron-doped silicon pattern 225S. The first doped silicon layer 225G' can become a first boron-doped silicon pattern 225G. Through the etching process, a portion of the upper support layer 224' can be exposed.

[0108] like Figure 5C As shown, the opening mask 226 may be removed. The second boron-doped silicon pattern 225S may be thinned while the opening mask 226 is removed. In other words, the thickness of the second boron-doped silicon pattern 225S after the opening mask 226 is removed may be less than the thickness of the second boron-doped silicon pattern 225S before the opening mask 226 is removed.

[0109] refer to Figure 5D , an opening 227 may be formed in the mold stack ML. The opening 227 may be formed by etching the mold stack ML using the second boron-doped silicon pattern 225S and the first boron-doped silicon pattern 225G as an etching mask. In order to form the opening 227, the second boron-doped silicon pattern 225S and the first boron-doped silicon pattern 225G may be used as an etching mask to sequentially etch the upper support member layer 224', the upper mold layer 223, the lower support member layer 222', and the lower mold layer 221. The etching process for forming the opening 227 may stop at the etch stop layer 204. Subsequently, the etch stop layer 204 may be etched to expose the top surface of the contact plug 203 below the opening 227. While the opening 227 is formed, the second boron-doped silicon pattern 225S may be removed. The thickness of the first boron-doped silicon pattern 225G after the opening 227 is formed may be less than the thickness of the first boron-doped silicon pattern 225G before the opening 227 is formed. An opening 227 may be formed on the contact plug 203. The opening 227 may be referred to as a hole where a lower electrode (or storage node) is to be formed.

[0110] Through the above-mentioned etching process, a mold stack pattern MP including a plurality of openings 227 may be formed. In this case, various openings 227 may be formed according to the difficulty of the etching process. For example, when the boron concentration of the first doped silicon layer 225G' is reduced, the stripping of the first doped silicon layer 225G' may be easier. Therefore, the sidewall 225W of the first boron-doped silicon pattern 225G may be formed vertically. When the sidewall 225W of the first boron-doped silicon pattern 225G is formed vertically, the sidewall of the opening 227 may be formed vertically. Since the sidewall of the opening 227 may be formed vertically, the poor contact with the contact plug 203 may be alleviated, and the capacitance of the capacitor may be increased. In order to form the opening 227, dry etching, wet etching, or a combination thereof may be used. The opening 227 may have a high aspect ratio. The opening 227 may have an aspect ratio of at least 1:1 or more. For example, the opening 227 may have a high aspect ratio of 10:1 or more.

[0111] like Figure 5E As shown, the first boron-doped silicon pattern 225G may be removed. Subsequently, a lower electrode layer (not shown) may be formed to cover the opening 227 and the mold stack pattern MP. The lower electrode layer (not shown) may be formed on the contact plug 203. Therefore, the lower electrode layer (not shown) may be electrically connected to the contact plug 203. The lower electrode layer (not shown) may include a metal, a metal nitride, or a combination thereof. The lower electrode layer (not shown) may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum, titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and at least one of a combination thereof. According to one embodiment, the lower electrode layer (not shown) may include titanium nitride (TiN). The lower electrode layer (not shown) may include titanium nitride (ALD-TiN) formed by ALD.

[0112] Subsequently, a lower electrode separation process may be performed. For example, in order to form a lower electrode 228 in the opening 227, a portion of the lower electrode layer (not shown) may be selectively removed. The lower electrode separation process may be performed by polishing. For example, the lower electrode 228 may be formed by performing chemical mechanical polishing (CMP) or etching back on the lower electrode layer (not shown). Therefore, the lower electrode 228 may be formed in the opening 227. After the lower electrode 228 is formed, the top surface of the upper support layer 224' may be exposed. Therefore, the lower electrode 228 may be formed in the opening 227. The lower electrode 228 may include any one of a column, a cylindrical column, or a composite column. In the present embodiment, the lower electrode 228 may be columnar. The lower electrode 228 may have a high aspect ratio. The lower electrode 228 may have an aspect ratio of 10:1 or greater.

[0113] refer to Fig. 5F , an upper support member 224 may be formed to support the upper outer wall of the lower electrode 228. In order to form the upper support member 224, an upper support member layer 224' may be etched using an opening mask 229. The opening mask 229 may include a photoresist pattern or a hard mask pattern. The upper support member layer 224' exposed by the opening mask 229 may be selectively etched. An upper opening 230 may be formed by etching the upper support member layer 224'. The upper support member 224 may include a plurality of upper openings 230. Through the upper openings 230, some surfaces of the upper mold layer 223 may be exposed.

[0114] like Figure 5G As shown, the upper mold layer 223 can be removed. For example, the upper mold layer 223 can be removed by a wet deep process. A wet chemical for removing the upper mold layer 223 can be supplied via the upper opening 230. One or more of HF, NH4F / NH4OH, H2O2, HCl, HNO3, H2SO4 or such chemicals can be used as the wet chemical. When removing the upper mold layer 223, the upper support member 224 and the lower support member layer 222' having etching selectivity for the upper mold layer 223 may not be removed. When the upper mold layer 223 is removed, the upper outer wall of the lower electrode 228 can be exposed. In this case, the upper outer wall of the lower electrode 228 can be supported by the upper support member 224. Therefore, the lower electrode 228 can be prevented from collapsing.

[0115] Subsequently, a lower-level support member 222 may be formed. To form the lower-level support member 222, the lower-level support member layer 222' may be selectively etched using an opening mask 229. The lower-level support member layer 222' may be selectively etched to be self-aligned with the upper-level support member 224. Lower-level openings 231 may be formed by etching the lower-level support member layer 222'. The lower-level support member layer 222' may include a plurality of lower-level openings 231. Through the lower-level openings 231, some surfaces of the lower-level mold layer 221 may be exposed.

[0116] like Figure 5HAs shown, the lower mold layer 221 can be removed. For example, the lower mold layer 221 can be removed by a wet deep process. A wet chemical for removing the lower mold layer 221 can be supplied via the lower opening 231. One or more of HF, NH4F / NH4OH, H2O2, HCl, HNO3, and H2SO4 can be used as the wet chemical. When removing the lower mold layer 221, the upper support member 224 and the lower support member 222 having etching selectivity for the lower mold layer 221 may not be removed. When removing the lower mold layer 221, the etch stop layer 204 can prevent damage to the interlayer insulating layer 202 and the contact plug 203. When the lower mold layer 221 is removed, the outer wall of the lower electrode 228 can be exposed. In this case, the middle portion of the lower electrode 228 can be supported by the lower support member 222.

[0117] refer to Fig.5I , a dielectric layer 232 may be formed. The dielectric layer 232 may be formed on the top and sidewalls of the lower electrode 228, the top and bottom of the lower support 222, and the top and bottom of the upper support 224. A portion of the dielectric layer 232 may cover the etch stop layer 204. The dielectric layer 232 may cover the lower support 222 and the upper support 224.

[0118] An upper electrode 233 may be formed on the dielectric layer 232. The dielectric layer 232 may be formed on the lower electrode 228 and the etch stop layer 204. The dielectric layer 232 may be or include a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) or strontium titanium oxide (SrTiO3). Alternatively, the dielectric layer 232 may be formed of a composite layer including two or more layers of the above-mentioned high-k materials. According to one embodiment, the dielectric layer 232 may be formed of a zirconium oxide-based material that can substantially reduce the equivalent oxide thickness (EOT) while providing good leakage current characteristics. For example, the dielectric layer 232 may include any one of ZAZ (ZrO2 / Al2O3 / ZrO2), TZAZ (TiO2 / ZrO2 / Al2O3 / ZrO2), TZAZT (TiO2 / ZrO2 / Al2O3 / ZrO2 / TiO2), ZAZT (ZrO2 / Al2O3 / ZrO2 / TiO2), TZ (TiO2 / ZrO2), or ZAZAT (ZrO2 / Al2O3 / ZrO2 / Al2O3 / TiO2). In a dielectric layer stack such as TZAZ, TZAZT, ZAZT, TZ, or ZAZAT, TiO2 may be replaced with Ta2O5. The dielectric layer 232 may be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD) having excellent step coverage.

[0119] The upper electrode 233 may be formed on the dielectric layer 232. The upper electrode 233 may include a metal-based material. For example, the upper electrode 233 may include at least one of titanium (Ti), titanium nitride (TN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and combinations thereof. The upper electrode 233 may be formed using low pressure CVD (LPCVD), PECVD, or ALD. According to one embodiment, the upper electrode 233 may include titanium nitride (ALD-TiN) formed by ALD.

[0120] Alternatively, the upper electrode 233 may have a multilayer structure. The upper electrode 233 may also be formed by sequentially stacking a lower metal-containing layer, a silicon germanium layer, and an upper metal-containing layer. The lower metal-containing layer and the upper metal-containing layer may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and a combination thereof. For example, the lower metal-containing layer may be a titanium nitride layer, and the upper metal-containing layer may be a WN / W stack of tungsten nitride and tungsten. The silicon germanium layer may be doped with boron. In order to form the upper electrode 233, an upper electrode layer (not shown) deposition and an upper electrode patterning may be performed.

[0121] In the present embodiment, the second doped silicon layer 225S' can be uniformly doped with a high concentration of boron, thereby increasing its etching selectivity for the mold stack ML. In addition, since the boron concentration of the first doped silicon layer 225G' gradually increases with the distance from its bottom surface 225GB, hard mask stripping can be easily performed. In other words, a hard mask layer with high etching selectivity and easy stripping can be formed by forming the second doped silicon layer 225S' and the first doped silicon layer 225G'. Therefore, the etching profile of the mold stack ML can be formed vertically. When the etching profile is formed vertically, process stability and reliability for the semiconductor device can be ensured.

[0122] FIG. 6A to FIG. 6G is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. According to one embodiment, the semiconductor device may include a nonvolatile memory device. According to one embodiment, the semiconductor device may include a semiconductor element having a vertical channel.

[0123] refer to Fig. 6A , a substrate 301 may be prepared. The substrate 301 may include any material suitable for semiconductor processes. The substrate 301 may include a semiconductor substrate. The substrate 301 may be formed of, for example, a silicon-containing material. The substrate 301 may be or include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof, and may be a single layer or multilayer structure thereof. The substrate 301 may be or include other semiconductor materials, such as germanium. The substrate 301 may be or include a compound semiconductor substrate, such as a IIIV semiconductor substrate, such as GaAs. The substrate 301 may be or include a silicon-on-insulator (SOI) substrate.

[0124] The insulating layer 302 and the sacrificial layer 303 may be alternately and repeatedly stacked on the substrate 301, thereby forming an alternating stack ST. According to one embodiment, the insulating layer 302 may include four layers, and the sacrificial layer 303 may include four layers. However, the embodiments of the present disclosure are not limited thereto. For example, the alternating stack may include different numbers of insulating layers 302 and different numbers of sacrificial layers 303. The sacrificial layer 303 may have an etching selectivity to the insulating layer 302. For example, the insulating layer 302 may be an oxide layer, and the sacrificial layer 303 may be a nitride layer. The insulating layer 302 may be a silicon oxide layer, and the sacrificial layer 303 may be a silicon nitride layer. The alternating stack ST may be a stack of multiple silicon oxide layers and multiple silicon nitride layers alternately and repeatedly stacked.

[0125] A capping layer 304 may be formed on the alternating stack ST. The capping layer 304 may be or include an insulating material. For example, the capping layer 304 may be or include silicon oxide (SiO2).

[0126] A hard mask layer 305 may be formed on the capping layer 304. The hard mask layer 305 may be formed to define at least one or more openings in the alternating stack ST. The hard mask layer 305 may have a multi-layer structure. According to one embodiment, the hard mask layer 305 may have a double-layer structure. The hard mask layer 305 may include a first doped silicon layer 305G' and a second doped silicon layer 305S'. The dopant in the first doped silicon layer 305G' and the second doped silicon layer 305S' may be boron. According to one embodiment, although the first doped silicon layer 305G' and the second doped silicon layer 305S' are separated from each other for the purpose of describing the hard mask layer 305, the first doped silicon layer 305G' and the second doped silicon layer 305S' may be layers into which one hard mask layer 305 is divided according to a concentration gradient of boron. Alternatively, the first doped silicon layer 305G' and the second doped silicon layer 305S' may include two independent hard mask layers.

[0127] The hard mask layer 305 may be formed of, for example, any one of polysilicon, an oxide film, a nitride film, or a combination thereof. According to one embodiment, the hard mask layer 305 may be formed of polysilicon. The hard mask layer 305 may be doped with a dopant. The etching selectivity of the hard mask layer 305 for the alternating stack ST may increase as the concentration of the dopant increases. The hard mask layer 305 may be a boron-doped layer. According to one embodiment, the hard mask layer 305 may be a boron-doped silicon (Si) layer formed by doping a polysilicon layer with boron. The hard mask layer 305 may be formed using, for example, B2H6 gas and SiH4 gas. In a variation of this embodiment, the hard mask layer 305 may further include additional dopants. The additional dopant may be, for example, at least any one selected from tungsten (W), carbon (C), nitrogen (N), or a combination thereof. For example, the hard mask layer 305 may be a silicon layer doped with tungsten and boron. According to one embodiment, the hard mask layer 305 may be a silicon layer doped with carbon and boron. According to one embodiment, the hard mask layer 305 may be a silicon layer doped with tungsten, carbon, and boron.

[0128] The first doped silicon layer 305G' may be or include a silicon layer doped with low concentration boron, and the second doped silicon layer 305S' may be or include a silicon layer doped with high concentration boron. The first doped silicon layer 305G' may have a first boron concentration, at which the stripping is performed faster than the second doped silicon layer 305S'. The second doped silicon layer 305S' may have a second boron concentration, at which the etching selectivity for the alternating stack ST is greater than that of the first doped silicon layer 305G'. In a variation of this embodiment, any one of the first doped silicon layer 305G' and the second doped silicon layer 305S' may further include an additional dopant. The additional dopant may be, for example, at least any one selected from tungsten, carbon, nitrogen, or a combination thereof. For example, any one of the first doped silicon layer 305G' or the second doped silicon layer 305S' may be or include a silicon layer doped with tungsten and boron. Alternatively, according to one embodiment, any one of the first doped silicon layer 305G' or the second doped silicon layer 305S' may be or include a silicon layer doped with carbon and boron. According to one embodiment, any one of the first doped silicon layer 305G' or the second doped silicon layer 305S' may be or include a silicon layer doped with tungsten, carbon, and boron.

[0129] For example, the hard mask layer 305 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In order to improve the deposition effect, the hard mask layer 305 may use plasma. For example, the hard mask layer 305 may be formed by, for example, plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD). According to one embodiment, the hard mask layer 305 may be formed by PECVD using SiH4 gas and B2H6 gas.

[0130] The first doped silicon layer 305G' may be formed on the alternating stack ST. The first doped silicon layer 305G' may include a bottom surface 305GB and a top surface 305SB. The boron concentration at the bottom surface 305GB of the first doped silicon layer 305G' may be different from the boron concentration at the top surface 305SB of the first doped silicon layer 305G'.

[0131] exist Figure 2A 305G'. The first doped silicon layer 305G' may include a gradient concentration of boron. The first doped silicon layer 305G' may include a vertical gradient concentration of boron. The boron concentration of the first doped silicon layer 305G' may be lowest at the bottom surface 305GB of the first doped silicon layer 305G' and may have a gradient doping profile, wherein the boron concentration of the first doped silicon layer 305G' gradually increases as it moves away from the bottom surface 305GB of the first doped silicon layer 305G'. Figure 2A 3 is a schematic simplified diagram, and the ratio P1 of the boron concentration of the first doped silicon layer 305G′ to the vertical distance from the bottom surface 305GB thereof is not limited to that shown, but may be changed with a different slope.

[0132] exist Figure 2B. The first doped silicon layer 305G' may include a multilayer stack of boron-doped silicon layers. The boron concentration of the first doped silicon layer 305G' may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 305G' gradually increases from the lowest level of the boron-doped silicon layer to the highest level of the boron-doped silicon layer. According to one embodiment, the first doped silicon layer 305G' may be a multilayer stack, which includes: a bottom layer at a lowest level; an intermediate layer at an intermediate level higher than the bottom layer; and a top layer at a highest level higher than the intermediate layer. The boron concentration of the first doped silicon layer 305G' may include a gradient doping profile, wherein the boron concentration of the first doped silicon layer 305G' gradually increases from the bottom layer to the top layer. The ratio PB of the boron concentration of the bottom layer to its height HB may be the same as or different from the ratio PM of the boron concentration of the intermediate layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. For example, the ratio PB of the boron concentration of the bottom layer to its height HB may be greater than the ratio PM of the boron concentration of the middle layer to its height HC and the ratio PT of the boron concentration of the top layer to its height HT. The ratio PM of the boron concentration of the middle layer to its height HC may be less than the ratio PB of the boron concentration of the bottom layer to its height HB and the ratio PT of the boron concentration of the top layer to its height HT. The height HB of the bottom layer, the height HC of the middle layer and the height HT of the top layer may be the same as or different from each other. For example, the height HB of the bottom layer may be less than the height HC of the middle layer and the height HT of the top layer. The height HC of the middle layer may be greater than the height HB of the bottom layer and the height HT of the top layer. It should be noted that Figure 2B 305G' is a simplified schematic example, and the height HB of the bottom layer, the height HC of the middle layer, and the height HT of the top layer of the first doped silicon layer 305G' are not limited to those shown in the drawings, but may include different values. The ratio PB of the boron concentration of the bottom layer to its height HB, the ratio PM of the boron concentration of the middle layer to its height HC, and the ratio PT of the boron concentration of the top layer to its height HT of the first doped silicon layer 305G' are not limited to those shown therein, but may include different values.

[0133] The first doped silicon layer 305G' may further include at least one additional dopant selected from tungsten, carbon, nitrogen or a combination thereof. Thus, the first doped silicon layer 305G' may be a silicon layer doped with tungsten and boron. According to one embodiment, the first doped silicon layer 305G' may be a silicon layer doped with carbon and boron. According to one embodiment, the first doped silicon layer 305G' may be a silicon layer doped with tungsten, carbon and boron.

[0134] The second doped silicon layer 305S' may be formed on the first doped silicon layer 305G'. The thickness 305SH of the second doped silicon layer 305S' may be greater than the thickness 305GH of the first doped silicon layer 305G'. The second doped silicon layer 305S' may include a single boron-doped silicon layer. The thickness 305SH of the single boron-doped silicon layer of the second doped silicon layer 305S' may be greater than the thickness 305GH of the multilayer stack of boron-doped silicon layers of the first doped silicon layer 305G'. The second doped silicon layer 305S' may include a bottom surface 305SB and a top surface 305ST, and the bottom surface 305SB of the second doped silicon layer 305S' may represent the same surface as the top surface 305SB of the first doped silicon layer 305G'. The bottom surface 305SB of the second doped silicon layer 305S' may have the same boron concentration as the top surface 305ST.

[0135] The boron concentration of the second doped silicon layer 305S' may be greater than the boron concentration of the first doped silicon layer 305G'. The second doped silicon layer 305S' may have a non-gradient concentration of boron. The second doped silicon layer 305S' may include a non-vertical gradient concentration of boron. The boron concentration of the second doped silicon layer 305S' may have a profile in which the boron concentration of the second doped silicon layer 305S' is uniform from the bottom surface 305SB to the top surface 305ST of the second doped silicon layer 305S'. Figure 2A , the ratio P2 of the boron concentration of the second doped silicon layer 305S' to the vertical distance 305SH from its bottom surface 305SB can be constant. The boron concentration of the second doped silicon layer 305S' can be continuous with the boron concentration of the first doped silicon layer 305G'. Therefore, the boron concentration at the bottom surface 305SB of the second doped silicon layer 305S' can be the same as the boron concentration at the highest level of the first doped silicon layer 305G'.

[0136] The second doped silicon layer 305S' may further include at least one additional dopant selected from tungsten, carbon, nitrogen or a combination thereof. Thus, the second doped silicon layer 305S' may be a silicon layer doped with tungsten and boron. According to one embodiment, the second doped silicon layer 305S' may be a silicon layer doped with carbon and boron. According to one embodiment, the second doped silicon layer 305S' may be a silicon layer doped with tungsten, carbon and boron.

[0137] An opening mask 306 may be formed on the second doped silicon layer 305S'. The opening mask 306 may include a photoresist pattern.

[0138] like Figure 6BAs shown, the opening mask 306 can be used as an etching mask to selectively remove the second doped silicon layer 305S' and the first doped silicon layer 305G'. Therefore, the second doped silicon layer 305S' can become a second boron-doped silicon pattern 305S. The first doped silicon layer 305G' can become a first boron-doped silicon pattern 305G. Therefore, a portion of the capping layer 304 can be exposed.

[0139] like Figure 6C As shown, the opening mask 306 may be removed. The second boron-doped silicon pattern 305S may be thinned while the opening mask 306 is removed. In other words, the thickness of the second boron-doped silicon pattern 305S after the opening mask 306 is removed may be less than the thickness of the second boron-doped silicon pattern 305S before the opening mask 306 is removed.

[0140] refer to Fig.6D , a stack hole 307 may be formed in the capping layer 304 and the alternating stack ST. The stack hole 307 may be formed by etching the capping layer 304 and the alternating stack ST using the second boron-doped silicon pattern 305S and the first boron-doped silicon pattern 305G as an etching mask. In order to form the stack hole 307, the second boron-doped silicon pattern 305S and the first boron-doped silicon pattern 305G may be used as an etching mask to sequentially etch the capping layer 304 and the alternating stack ST. The etching process for forming the stack hole 307 may be stopped at the substrate 301. Therefore, the top surface of the substrate 301 may be partially exposed. During the etching process, the second boron-doped silicon pattern 305S may be removed. The height of the first boron-doped silicon pattern 305G after the stack hole 307 is formed may be less than the height of the first boron-doped silicon pattern 305G before the stack hole 307 is formed.

[0141] Through the above-mentioned etching process, an alternating stack pattern SP including a plurality of stack holes 307 may be formed. Various stack holes 307 may be formed according to the difficulty of the etching process. For example, when the boron concentration of the first doped silicon layer 305G' is reduced, the stripping of the first doped silicon layer 305G' may be easier. Therefore, the sidewall 305W of the first boron-doped silicon pattern 305G may be formed vertically. When the sidewall 305W of the first boron-doped silicon pattern 305G is formed vertically, the sidewall of the stack hole 307 may be formed vertically. In order to form the stack hole 307, dry etching, wet etching, or a combination thereof may be used. The stack hole 307 may have a high aspect ratio. The stack hole 307 may have an aspect ratio of at least 1:1 or more. For example, the stack hole 307 may have a high aspect ratio of 10:1 or more.

[0142] like Fig. 6EAs shown, the first boron-doped silicon pattern 305G may be removed. Subsequently, a channel structure CH may be formed in the stack hole 307. The stack hole 307 may include a dielectric layer 308, a channel active layer 309, a channel core layer 310, and a channel pad layer 311. Therefore, the dielectric layer 308, the channel active layer 309, the channel core layer 310, and the channel pad layer 311 may be formed in the stack hole 307. The dielectric layer 308 may be formed in the stack hole 307. In order to form the dielectric layer 308, a dielectric layer may be formed inside the stack hole 307. The dielectric layer 308 may be conformally formed on the surface of the stack hole 307. The dielectric layer 308 may be conformally formed. The dielectric layer 308 may be formed only inside the stack hole 307. The dielectric layer 308 may have a multilayer structure.

[0143] Then, an etch-back process may be performed to remove the dielectric layer 308 from the bottom of the stack hole 307, thereby exposing the surface of the substrate 301. Therefore, the dielectric layer 308 may be conformally formed on the sidewall surface of the stack hole 307. A channel active layer 309 may be formed on the dielectric layer 308, and the channel active layer 309 may be in direct contact with the dielectric layer 308. In order to form the channel active layer 309, polycrystalline silicon or single crystal silicon may be formed in the stack hole 307. The channel active layer 309 may be conformally formed. A channel core layer 310 may be formed on the channel active layer 309 and may be in direct contact with the channel active layer 309. In order to form the channel core layer 310, silicon oxide may be formed in the stack hole 307. The channel core layer 310 may fill the inside of the stack hole 307. In order to form the channel core layer 310, planarization may be performed. Therefore, the top surface of the capping layer 304 may be exposed. Subsequently, the top portion of the channel core layer 310 may be recessed. A channel pad layer 311 in contact with the channel active layer 309 may be formed in the stack hole 307. The channel pad layer 311 may fill the recess of the channel core layer 310. The channel pad layer 311 may include polycrystalline silicon or single crystal silicon. The bottom surface of the channel pad layer 311 may be in direct contact with the top surface of the channel core layer 310, and the sidewall of the channel pad layer 311 may be in direct contact with the uppermost sidewall of the channel active layer 309.

[0144] refer to Fig. 6F , a channel cover layer 312 may be formed on the cover layer 304 and the channel structure CH. The channel cover layer 312 may directly contact the cover layer 304, the dielectric layer 308, the channel active layer 309, and the channel pad layer 311. The channel cover layer 312 may be or include silicon oxide.

[0145] Then, if Fig. 6FAs shown, the alternating stack pattern SP, the capping layer 304, and the channel capping layer 312 may be etched to form a trench T. The trench T may contact the substrate 301. The sacrificial layer 303 may be removed through the trench T.

[0146] refer to Figure 6G , a memory film 313 may be formed in the space formed by removing the sacrificial layer 303. The memory film 313 may be formed conformally. The memory film 313 may include a plurality of films. For example, the memory film 313 may be formed by sequentially depositing a tunnel insulating film, a charge trapping film, and a charge blocking film. The tunnel insulating film may be provided for charge tunneling and may be formed of an oxide film. The charge trapping film may be provided for capturing charges and thus storing data, and may be formed of a nitride film. The charge blocking film may be provided for preventing charges in the charge trapping film from moving to the outside, and may be formed of an oxide film. In other words, the memory film 313 may have a three-layer structure of oxide-nitride-oxide (ONO). A gate electrode 314 may be formed on the memory film 313 to fill the space created by removing the sacrificial layer 303. The gate electrode 314 may include a metal or a metal oxide, which may be conformally deposited by CVD or ALD. The gate electrode 314 may include tungsten (W). In order to form the storage film 313 and the gate electrode 314, the storage film 313 and the gate electrode 314 exposed in the trench T can be removed. In the present embodiment, the storage film 313 is located between the channel structure CH and the gate electrode 314 and between the insulating layer 302 and the gate electrode 314. However, the embodiments of the present disclosure are not limited thereto. For example, an insulating film other than the storage film 313 may also be located between the insulating layer 302 and the gate electrode 314. For example, a single oxide or nitride film may be located between the insulating layer 302 and the gate electrode 314. In the present embodiment, the second doped silicon layer 305S' may be uniformly doped with a high concentration of boron, thereby increasing its etching selectivity for the alternating stack ST. In addition, since the boron concentration of the first doped silicon layer 305G' gradually increases with the increase of the distance from its bottom surface 305GB, it is possible to easily perform hard mask stripping. In other words, a hard mask layer with high etching selectivity and easy stripping can be formed by forming the second doped silicon layer 305S' and the first doped silicon layer 305G'. Therefore, the etching profile of the alternating stack ST can be formed vertically. Since the etching profile is formed vertically, the process stability and reliability of the memory device can be ensured.

[0147] It is obvious to those skilled in the art that the various embodiments of the present invention described above are not limited to those shown in the above embodiments and the accompanying drawings, and various changes, modifications or substitutions may be made thereto without departing from the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming an etching target layer on a substrate; forming a first boron-doped silicon layer on the etching target layer, wherein the first boron-doped silicon layer has a first boron concentration; forming a second boron-doped silicon layer on the first boron-doped silicon layer, wherein the second boron-doped silicon layer has a second boron concentration; and using the first boron-doped silicon layer and the second boron-doped silicon layer as etching barrier layers to etch the etching target layer, wherein the second boron concentration of the second boron-doped silicon layer is greater than the first boron concentration of the first boron-doped silicon layer, wherein, at a first boron concentration of the first boron-doped silicon layer, stripping proceeds faster than the second boron-doped silicon layer, and At a second boron concentration in the second boron-doped silicon layer, an etching selectivity for the etching target layer is greater than that for the first boron-doped silicon layer.

2. The method according to claim 1, in, Forming the first boron-doped silicon layer includes forming a first silicon layer and doping boron into the first silicon layer; Forming the second boron-doped silicon layer includes forming a second silicon layer and doping boron into the second silicon layer.

3. The method according to claim 2, in, A first boron concentration of the first boron-doped silicon layer gradually increases from a bottom surface of the first silicon layer to a top surface of the first silicon layer.

4. The method according to claim 2, in, The second boron concentration of the second boron-doped silicon layer is uniform from a bottom surface of the second silicon layer to a top surface of the second silicon layer.

5. The method according to claim 1, in, The first boron concentration of the first boron-doped silicon layer has a vertical gradient concentration, and the second boron concentration of the second boron-doped silicon layer has a non-vertical gradient concentration.

6. The method according to claim 1, in, The first boron-doped silicon layer is thinner than the second boron-doped silicon layer.

7. A method for manufacturing a semiconductor device, the method comprising: forming an etching target layer on a substrate; forming a first boron-doped silicon layer on the etching target layer; forming a second boron-doped silicon layer on the first boron-doped silicon layer; using the first boron-doped silicon layer and the second boron-doped silicon layer as etching barrier layers to etch the etching target layer, wherein the first boron-doped silicon layer comprises a multi-layer stack of boron-doped silicon layers, and wherein the boron concentration of the multilayer stack has a gradient doping profile, wherein the boron concentration of the multilayer stack gradually increases from the lowest level of boron-doped silicon layer to the highest level of boron-doped silicon layer, wherein the boron concentration of the second boron-doped silicon layer is greater than the boron concentration of the first boron-doped silicon layer, wherein, at a first boron concentration of the first boron-doped silicon layer, stripping proceeds faster than the second boron-doped silicon layer, and At a second boron concentration in the second boron-doped silicon layer, an etching selectivity for the etching target layer is greater than that for the first boron-doped silicon layer.

8. A method for manufacturing a semiconductor device, the method comprising: forming an etching target layer; forming a first boron-doped silicon layer on the etching target layer; forming a second boron-doped silicon layer on the first boron-doped silicon layer; using the first boron-doped silicon layer and the second boron-doped silicon layer as etching barrier layers to etch the etching target layer, wherein the first boron-doped silicon layer comprises a multi-layer stack of boron-doped silicon layers, wherein the second boron-doped silicon layer comprises a single boron-doped silicon layer, and wherein the second boron-doped silicon layer is thicker than the multilayer stack of boron-doped silicon layers, wherein, at a first boron concentration of the first boron-doped silicon layer, stripping proceeds faster than the second boron-doped silicon layer, and At a second boron concentration in the second boron-doped silicon layer, an etching selectivity for the etching target layer is greater than that for the first boron-doped silicon layer.

9. The method according to claim 1, in, One of the first boron-doped silicon layer and the second boron-doped silicon layer further includes an additional dopant.

10. The method according to claim 9, in, The additional dopant includes at least any one selected from tungsten, carbon, nitrogen, or a combination thereof.

11. The method according to claim 1, in, The first boron-doped silicon layer and the second boron-doped silicon layer include: a silicon layer doped with tungsten and boron, a silicon layer doped with carbon and boron, or a silicon layer doped with tungsten, carbon, and boron.

12. The method according to claim 1, in, The first boron-doped silicon layer and the second boron-doped silicon layer are formed using SiH 4 gas and B 2 H 6 gas in a plasma enhanced chemical vapor deposition scheme.

13. The method according to claim 1, in, The etching target layer includes silicon oxide.

14. The method according to claim 1, in, The etch target layer includes a stack of a plurality of silicon oxide layers and a plurality of silicon nitride layers which are alternately stacked.

15. A semiconductor device comprising: a silicon oxide layer on a substrate; a first boron-doped silicon layer located on the silicon oxide layer, wherein the first boron-doped silicon layer has a gradient concentration of boron; and a second boron-doped silicon layer located on the first boron-doped silicon layer, wherein the second boron-doped silicon layer has a non-gradient concentration of boron, wherein, at a first boron concentration of the first boron-doped silicon layer, stripping proceeds faster than the second boron-doped silicon layer, and At the second boron concentration of the second boron-doped silicon layer, the etching selectivity for the etching target layer is greater than that for the first boron-doped silicon layer.

16. The semiconductor device according to claim 15, in, The first boron-doped silicon layer and the second boron-doped silicon layer are each formed by doping a polysilicon layer with boron.

17. The semiconductor device according to claim 16, in, The boron concentration of the first boron-doped silicon layer is lowest at the bottom surface of the polysilicon layer and has a gradient doping distribution, wherein the boron concentration of the first boron-doped silicon layer gradually increases from the bottom surface of the polysilicon layer to the top surface of the polysilicon layer.

18. The semiconductor device according to claim 16, in, The boron concentration of the second boron-doped silicon layer has a profile in which the boron concentration of the second boron-doped silicon layer is uniform from a bottom surface of the polysilicon layer to a top surface of the polysilicon layer.

19. The semiconductor device according to claim 15, in, The first boron-doped silicon layer has a vertical gradient concentration of boron, and The second boron-doped silicon layer has a non-vertical gradient concentration of boron.

20. The semiconductor device according to claim 15, in, The first boron-doped silicon layer is thinner than the second boron-doped silicon layer.

21. The semiconductor device according to claim 15, in, The first boron-doped silicon layer and the second boron-doped silicon layer include at least one additional dopant selected from tungsten, carbon, nitrogen, or a combination thereof.

22. A method for manufacturing a semiconductor device, the method comprising: forming a mold stack on a substrate; forming a first boron-doped silicon layer on the mold stack; forming a second boron-doped silicon layer on the first boron-doped silicon layer; etching the mold stack to form an opening exposing the substrate by using the first boron-doped silicon layer and the second boron-doped silicon layer as etch barriers; as well as forming a lower electrode in the opening, wherein the second boron-doped silicon layer has a greater boron concentration than the first boron-doped silicon layer, wherein the first boron-doped silicon layer has a first boron concentration at which stripping proceeds faster than stripping of the second boron-doped silicon layer, wherein the second boron-doped silicon layer has a second boron concentration, at which the etching selectivity of the second boron-doped silicon layer to the etching target layer is greater than that of the first boron-doped silicon layer, and Wherein, the second boron concentration is greater than the first boron concentration.

23. The method according to claim 22, in, The boron concentration of the first boron-doped silicon layer has a gradient doping profile in the thickness direction, and The boron concentration of the second boron-doped silicon layer has a uniform distribution in the thickness direction.

24. The method according to claim 22, in, The first boron-doped silicon layer is thinner than the second boron-doped silicon layer.

25. The method according to claim 22, in, At least one of the first boron-doped silicon layer and the second boron-doped silicon layer further includes tungsten, carbon, nitrogen, or a combination thereof.

26. A method for manufacturing a semiconductor device, the method comprising: forming an alternating stack, wherein insulating layers and sacrificial layers are alternately stacked on a substrate; forming a first boron-doped silicon layer on the alternating stack; forming a second boron-doped silicon layer on the first boron-doped silicon layer; forming a stack hole exposing the substrate by etching the alternating stack using the hard mask layer as an etch barrier; and forming a channel structure in the stacked holes, wherein the second boron-doped silicon layer has a greater boron concentration than the first boron-doped silicon layer, wherein the first boron-doped silicon layer has a first boron concentration at which stripping proceeds faster than stripping of the second boron-doped silicon layer, wherein the second boron-doped silicon layer has a second boron concentration, at which the etching selectivity of the second boron-doped silicon layer to the etching target layer is greater than that of the first boron-doped silicon layer, and Wherein, the second boron concentration is greater than the first boron concentration.

27. The method according to claim 26, in, The boron concentration of the first boron-doped silicon layer has a gradient doping profile in the thickness direction, and The boron concentration of the second boron-doped silicon layer has a uniform distribution in the thickness direction.

28. The method according to claim 26, in, The first boron-doped silicon layer is thinner than the second boron-doped silicon layer.

29. The method according to claim 26, in, At least one of the first boron-doped silicon layer and the second boron-doped silicon layer further includes tungsten, carbon, nitrogen, or a combination thereof.

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