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Automatic layout and wiring method

An automatic layout and wiring method technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of tedious development cycle of automatic verification technical documents, and achieve the effect of improving design efficiency and coverage

Pending Publication Date: 2022-01-14
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an automatic layout and routing

Method used

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Embodiment Construction

[0026] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] see figure 1 , the present invention provides an automatic layout and wiring method, comprising:

[0028] Step 1, obtain the test layout data, and use the test layout data as reference data;

[0029] In a possible implementation, the test layout data in step 1 is the test layout data drawn during the pre-physical design rule check and development, and the test layout data includes the correct test layout graphics and wrong te...

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Abstract

The invention provides an automatic layout and wiring method. The method comprises the steps of obtaining test layout data; inserting an input pin label and an output pin label at a target metal layer at a top layer in the test layout data; extracting physical library information from the test layout data, wherein the physical library information comprises all levels of layout wiring at the rear end of the layout; making a netlist file according to the test layout data, wherein the netlist file comprises a name of a target metal layer at a top layer, input pin information and output pin information; importing the physical library information file, the netlist file and the design layout file into automatic layout and wiring software; and performing result check on the design layout by utilizing automatic wiring software. According to the method, the physical design rule coverage rate is increased, and the design efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an automatic layout and wiring method. Background technique [0002] Electronic Design Automation (EDA) refers to the use of computer-aided design (CAD) software to complete the functional design, synthesis, verification, and physical design of VLSI chips (including layout, wiring, layout, and design rule checking, etc.) and other process design methods. [0003] At present, the development and verification methods of existing verification technical documents, such as figure 2 As shown, although this method is accurate, it is cumbersome and has a long development cycle. The main disadvantages are: [0004] 1) It takes a long time to develop, debug, verify, and correct; [0005] 2) It is necessary to draw the test pattern of each physical design rule in the automatic layout and routing software; [0006] 3) Unable to draw some complex physical design rules in the automa...

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Application Information

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IPC IPC(8): G06F30/392G06F30/394G06F30/398
CPCG06F30/392G06F30/394G06F30/398
Inventor 许烨东薛芳琦
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD