A sub-circuit matching method for analog integrated circuits

Abstract

The present invention proposes a subcircuit matching method for analog integrated circuits, including: reading a circuit netlist file, defining node labels for component nodes in the circuit to distinguish; topologically analyzing the components respectively, generating a directed circuit topology diagram; sorting the node search order of the subcircuit, and dynamically selecting several nodes of the analog integrated circuit accordingly, thereby forming multiple node pairs and organizing them into a search tree, wherein a tree node of the search tree represents a subgraph state; adding the node pair to the tree node to form a new subgraph state, and when adding node pairs composed of nodes of the same subcircuit and nodes of different analog integrated circuits, the search tree forms different branches; pruning invalid branches in the search tree, thereby quickly matching the subcircuit and the nodes of the analog integrated circuit. The present invention has the effect of being able to achieve circuit matching with high accuracy and low computational complexity.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuit design, and in particular to a sub-circuit matching method for analog integrated circuits. Background Art

[0002] With the development of semiconductor process technology, especially the development of system on chip (SoC), the number of transistors integrated in the chip is getting larger and larger, which makes the circuit structure on the chip more and more complex, especially increasing the challenge of analog integrated circuit design. Traditional analog integrated circuit design is completed by relevant personnel purely manually, and the layout is drawn manually, resulting in a long cycle and low efficiency of analog integrated circuit design. Therefore, analog circuit design should use analog circuit CAD (Computer Aided Design) software to assist in design and realize the automation process of analog integrated circuit. However, due to the poor anti-interference ability of analog circuits, high circuit structure flexibility, and cumbersome performance indicators, compared with digital circuit CAD tools, traditional analog circuit design is more based on the designer's experience and knowledge, and a heuristic design process. At present, there is still no mature commercial CAD tool that can fully support the automation process of analog circuit design and layout design. The design automation of analog integrated circuits has become a bottleneck in integrated circuit design.

[0003] With the development of analog integrated circuits and the continuous reduction of circuit feature process size, matching circuit identification problems often occur in circuit design. Circuit mismatch will affect circuit common mode rejection ratio, offset, linearity and other performance parameters, resulting in a sharp deterioration in circuit performance. The matching circuit identification problem considers whether there is a template circuit with a specified function or structure in a target circuit. It is widely used in layout and principle. Figure 1It plays an important role in the design simulation of CAD tools, such as consistency checking (LVS), logic synthesis of sequential circuit design and reverse engineering. At present, many experts and scholars have proposed research methods for extracting subcircuits in large-scale circuits. The SubGemini algorithm is a classic algorithm for solving the problem of subgraph isomorphism on circuits. First, through the partitioning algorithm, all positions that meet the subgraph isomorphism relationship with the subcircuit are found in the main circuit diagram. The specific operation is to find a key node in the subcircuit diagram, and correspondingly find all nodes that match it in the main circuit diagram to form a candidate set. In the candidate set, it is judged whether it meets the subgraph isomorphism relationship. The SA (Self annealing) algorithm corrects the objective function related to circuit identification based on SubGemini. The SA algorithm is usually used for inaccurate graph matching. In the subgraph isomorphism algorithm, most of the recently proposed algorithms follow three different ways: tree search, constraint propation and Graph Indexing. The tree search-based algorithm expresses the problem as a search space, which is usually visited in depth-first order and uses heuristics to avoid useless parts of the space. The Ullmann and RI algorithms proposed based on this method can effectively solve the subgraph isomorphism problem.

[0004] However, through investigation and comparison of the above methods, it is found that the above methods have high computational costs, are slow and inefficient in identifying large-scale mixed element circuits, and have low accuracy.

[0005] In view of this, it is particularly important to design a sub-circuit matching method with high accuracy and low computational complexity. Summary of the invention

[0006] In order to solve the technical problems of low accuracy and high computational complexity of matching circuit identification methods in the prior art, the present invention proposes a sub-circuit matching method for analog integrated circuits, which is used to solve the above technical problems and achieve circuit matching with high accuracy and low computational complexity.

[0007] The present application proposes a sub-circuit matching method for an analog integrated circuit, comprising the following steps:

[0008] S1, reading a circuit netlist file, and defining node labels for the component nodes in the subcircuit and the analog integrated circuit to distinguish different types of components;

[0009] S2, topologically analyze the components in the sub-circuit and the analog integrated circuit respectively, and generate directed circuit topological graphs of the sub-circuit and the analog integrated circuit;

[0010] S3, sorting the node search order of the subcircuit, dynamically selecting a plurality of nodes of the analog integrated circuit according to the node search order of the subcircuit, and organizing the nodes of the subcircuit and the plurality of nodes of the analog integrated circuit into a plurality of node pairs respectively, and organizing the node pairs into a search tree, wherein a tree node in the search tree represents a subgraph state;

[0011] S4, adding the node pair to the tree node to form a new subgraph state, wherein when the node pair consisting of the node of the same subcircuit and the node of different analog integrated circuits is added, the search tree forms different branches; and

[0012] S5. Prune invalid branches in the search tree, thereby quickly matching and identifying nodes of the subcircuit and the analog integrated circuit.

[0013] By setting node labels for components in the circuit to distinguish different types of components, and then using different graph topology forms for different types of components, the circuit structure topology feature expression is optimized, and then by establishing a search tree, using the tree search scheme to sequentially add node pairs for search and adopt appropriate pruning rules, while ensuring high-efficiency search, it has good pruning quality, making the time complexity far less than exponential growth. This application can correctly find matching results in analog integrated circuits of small, medium, large and multiple mixed components, and the detection time is short.

[0014] Preferably, defining node labels for component nodes in the subcircuit and the analog integrated circuit in step S1 specifically includes:

[0015] defining signal terminal node labels, defining the node labels of the power node and the ground node as 0 and N respectively; and

[0016] Define component node labels to give unique node labels to specific ports of the component.

[0017] By setting node labels for signal terminals and component nodes, signal terminals and different components in the circuit can be distinguished.

[0018] Preferably, the topology of the components in the subcircuit and the integrated circuit in step S2 specifically includes: taking the ports of the components as nodes and the connection relationship between the ports of the components as edges to establish the topological structure of the components. By performing directed graph topology on the components, the circuit structure topological feature expression is further optimized and the matching accuracy is improved.

[0019] Further preferably, the step of establishing the topological structure of the component specifically includes:

[0020] Establishing an active device topology structure, wherein each port of the active device is connected to each other in a unilateral directed manner, and each port of the active device is connected to the ports of other components in a bilateral directed manner; and

[0021] A passive device topology structure is established, wherein ports of the passive devices are connected in a bilaterally directed manner.

[0022] By adopting different topologies for active devices and passive devices, it is possible to avoid generating multiple sets of matching results that are inconsistent with the actual circuit during the circuit matching process.

[0023] Preferably, the directed circuit topology diagram of the subcircuit and the analog integrated circuit generated in step S2 is specifically manifested as: the port nodes of each component are sorted and labeled in an ascending manner. According to the topological structure of the component, the port nodes of each component are labeled in an ascending manner, thereby generating a directed circuit topology diagram.

[0024] Further preferably, after step S2 and before step S3, the method further includes: classifying and labeling the port nodes of the components of different types, and using the same label for the same port nodes of the components of the same type, and generating a circuit topology label diagram of the subcircuit and the analog integrated circuit. Classifying and labeling the port nodes of the components of different types, and using the same label for the same port nodes of the components of the same type, facilitates the subsequent algorithm to identify all components.

[0025] Preferably, in step S3, sorting the node matching order of the subcircuit in the search tree specifically includes:

[0026] Probability calculation, calculating the number of corresponding nodes with the same node label as the node of the subcircuit found in the analog integrated circuit, the smaller the number of corresponding nodes in the analog integrated circuit, the greater the probability of finding the corresponding node that meets the subgraph isomorphism requirement, and the higher the search priority of the node corresponding to the subcircuit; and

[0027] Compare the node degrees, calculate the out-degree and in-degree of the subcircuit nodes, the higher the out-degree and in-degree are, the higher the node search priority corresponding to the subcircuit is;

[0028] The priority of the probability calculation is greater than the priority of the node degree comparison.

[0029] By determining the node matching order of the subcircuit through probability calculation and comparison of node degrees, the redundancy of the search can be reduced, thereby reducing the computational complexity and shortening the matching time.

[0030] Further preferably, the step S3 of dynamically selecting several nodes of the analog integrated circuit according to the node search order of the subcircuit specifically includes: according to the node search order of the subcircuit, identifying the last searched node as the parent node of the current searched node, thereby selecting the candidate node of the current search in the node search process of the analog integrated circuit, wherein the selection principle of the candidate node is:

[0031] The order relationship between the current search node of the subcircuit and its parent node is the same as the order relationship between the candidate node and its parent node.

[0032] In the process of searching for nodes of analog integrated circuits, by constraining candidate nodes, the range of nodes of analog integrated circuits that need to be matched can be greatly narrowed, thereby reducing computational complexity.

[0033] Preferably, the pruning of invalid branches of the search tree in step S5 specifically includes: determining whether the subgraph state of the tree node currently being searched satisfies a feasibility rule, and if not, determining that the tree node is an invalid node and abandoning the search for the tree node branch. By pruning the branches of the tree node, the range of nodes in the analog integrated circuit that need to be matched is further reduced, thereby improving the matching efficiency.

[0034] Further preferably, the feasibility rules specifically include:

[0035] After the new node pair is added to the tree node of the search tree, the node labels of the corresponding nodes in the analog integrated circuit and the subcircuit are all the same, and the search tree is kept in a consistent state in the current subgraph state, the subgraph state of the next step, and the subgraph state of the next two steps, wherein the consistent state is specifically manifested as:

[0036] After the new node pair is added to the tree node of the search tree, all the node pairs in the current subgraph state satisfy the subgraph isomorphism relationship.

[0037] After adding a new node pair to each tree node of the search tree, this method predicts whether the branch can find a matching result, cuts off the branch with low possibility, and abandons the search for the branch, thereby improving the matching search efficiency.

[0038] The present application proposes a sub-circuit matching method for analog integrated circuits, which sets node labels for the nodes of components in the circuit to distinguish different types of components, then uses different graph topology forms for different types of components, and classifies and labels the port nodes of different types of components to generate a circuit topology label graph, which optimizes the expression of circuit structure topological features and can perform more accurate symmetrical matching of different types of components. Then, by establishing a search tree, using a tree search scheme to sequentially add node pairs for search and using appropriate pruning rules, the circuit matching problem is converted into a sub-graph isomorphism problem, while ensuring efficient search, making the time complexity much less than exponential growth. The present application can correctly find matching results in analog integrated circuits of small, medium, large and multiple mixed components, and the detection time is short. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and are used together with the description to explain the principles of the present invention. It will be easy to recognize other embodiments and many expected advantages of the embodiments because they become better understood by reference to the following detailed description. The elements of the accompanying drawings are not necessarily to scale with each other. The same reference numerals refer to corresponding similar parts.

[0040] Figure 1 is a flow chart of a sub-circuit matching method for analog integrated circuits according to an embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of a circuit netlist file according to a specific embodiment of the present invention;

[0042] Figure 3 is a circuit structure diagram of a differential amplifier circuit according to a specific embodiment of the present invention;

[0043] FIG4( a ) is a device structure diagram of a MOS tube according to a specific embodiment of the present invention;

[0044] FIG4( b ) is a diagram showing the internal topological structure of a MOS tube according to a specific embodiment of the present invention;

[0045] FIG. 5( a ) is a device structure diagram of a resistor according to a specific embodiment of the present invention.

[0046] FIG5( b ) is a diagram showing the internal topological structure of a resistor according to a specific embodiment of the present invention;

[0047] Figure 6 is a circuit topology diagram of a differential amplifier circuit according to a specific embodiment of the present invention;

[0048] Figure 7is a circuit topology label diagram of a differential amplifier circuit according to a specific embodiment of the present invention;

[0049] Figure 8 is a flowchart of a tree search according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0050] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention.

[0051] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0052] Figure 1 FIG. 4 shows a flow chart of a sub-circuit matching method for analog integrated circuits according to an embodiment of the present invention. Figure 1 As shown, the matching method includes the following steps:

[0053] S1. Read the circuit netlist file and define node labels for component nodes in the subcircuit and analog integrated circuit to distinguish different types of components.

[0054] In a specific embodiment, reading the circuit netlist file includes reading two types of circuit information: circuit signal terminals and circuit components, that is, defining node labels includes defining signal terminal node labels and defining component node labels. In the signal terminal node label definition part, the node labels of the power node and the ground node are defined as 0 and N respectively; in the component node label definition part, a unique node label is given to a specific port of the component. The specific description is as follows:

[0055] Figure 2 FIG. 4 shows a schematic diagram of a circuit netlist file according to a specific embodiment of the present invention. Figure 2 As shown, the second line in the circuit netlist file shows the port names and attributes in the circuit. Among them, I represents the input port, O represents the output port, and B represents the input and output port. In the subsequent circuit topology diagram structure process, if the input end node and the output end node are extracted, the expected matching result will not be obtained due to the conflict of node labels when solving the subgraph isomorphism problem. Therefore, in this embodiment, only the two signal terminals, the power node and the ground node, are extracted, and the node labels of the power node and the ground node are set to 0 and N respectively (N is a label different from all types of component ports in the circuit, and N=99 is taken in this embodiment) to ensure that there will be no duplication with the node labels of other components.

[0056] Continue to refer Figure 2 , the circuit netlist file fully expresses the connection topology and attribute information of the entire circuit components. When designing a circuit, the model of the components is determined while the process is determined. Therefore, the circuit netlist information can be used to determine whether the components belong to active devices such as P-type field effect tube PMOS, N-type field effect tube NMOS, triode BJT or passive devices such as capacitors, resistors, inductors, etc. There are two methods to distinguish the types of components: the first is to judge by the name of the components in the first column of the circuit netlist file. Generally, the names of components begin with the letters of the component types, such as MOS active devices mostly begin with M, and resistor passive devices mostly begin with R; the second is to confirm according to the process type names of various components in the circuit netlist information. In this embodiment, ND in the circuit netlist file indicates that this component is an NMOS tube, and PD indicates that this component is a PMOS tube. In this embodiment, the first method is specifically used to judge the type of components, and the process type and process parameters of the components are used as its parameter information, and matching circuit identification is performed based on whether the corresponding component parameters are considered.

[0057] S2. Topologically analyze the components in the sub-circuit and the analog integrated circuit respectively, and generate directed circuit topological diagrams of the sub-circuit and the analog integrated circuit.

[0058] In a specific embodiment, the ports of the components are taken as nodes, and the connection relationship between the ports of the components is taken as an edge, so as to topologically organize the components, establish the topological structure of the components, and then combine the topological structures of multiple components into a directed circuit topological graph of the corresponding subcircuit and analog integrated circuit. The components in the circuit include active components and passive components, so the topological structure of the components includes the active device topological structure and the passive device topological structure. The active device topological structure and the passive device topological structure will be described below with a specific circuit.

[0059] Figure 3FIG. 4 shows a circuit structure diagram of a differential amplifier circuit according to a specific embodiment of the present invention, as shown in FIG. Figure 3 As shown, the differential amplifier circuit is composed of two PMOS tubes M1, M2 and three NMOS tubes M3, M4, M5, and also contains a power signal port VDD, a ground signal port GND, three input signal ports Vin, Vip, Vb1 and an output signal port VDD. The MOS tube has four ports, namely D, G, S, and B, and in circuit identification, only the connection status of the D, G, and S terminals of the MOS tube is concerned, and the substrate terminal is ignored. Therefore, in this embodiment, the MOS tube is represented as a three-port device for topological representation of the figure. However, considering the diversity of port connections of active components and passive components in actual circuits, a topological representation of node clusters is established in this embodiment.

[0060] The definitions for active device topology and passive device topology are as follows:

[0061] FIG4(a) shows a device structure diagram of a MOS tube according to a specific embodiment of the present invention, and FIG4(b) shows a device internal topology diagram of a MOS tube according to a specific embodiment of the present invention. As shown in FIG4(a) and FIG4(b), the MOS tube is expanded into a node cluster structure with three nodes connected, wherein each node represents its three ports D, G and S, and the three ports are connected to other components in the circuit in a bilateral directed manner; and if the active device is also connected in an undirected edge manner, multiple sets of matching results that are inconsistent with the actual circuit will be generated, so the connection inside the active device needs to be redefined, and the connection between the internal ports of the MOS tube is connected in a unilateral directed manner. Among them, the MOS tube is mapped according to the internal connection mode of the G end pointing to the D end and the G end pointing to the S end. It should be noted that for the NPN and PNP components in the triode BJT, their definitions are similar to those of the MOS tube, and will not be repeated here.

[0062] FIG5(a) shows a device structure diagram of a resistor according to a specific embodiment of the present invention, and FIG5(b) shows a device internal topology diagram of a resistor according to a specific embodiment of the present invention. As shown in FIG5(a) and FIG5(b), if a unilateral directed connection method is used inside a passive component, it will violate its bidirectionality in the circuit structure. Therefore, a bilateral directed connection method is used between the internal ports of capacitors, resistors, and inductors. For a diode, which is also a two-port component, its positive and negative ends cannot be replaced. Therefore, unlike the internal mapping of a resistor, a unilateral directed connection method is used between the two ports of a diode.

[0063] According to the above-mentioned method of component internal connection mapping and external port connection mapping, Figure 6FIG. 4 shows a circuit topology diagram of a differential amplifier circuit according to a specific embodiment of the present invention, as shown in FIG. Figure 6 As shown, node 0 represents the power signal port node, node 16 represents the ground signal port node, nodes 1, 2, 3, 4, 5, and 6 represent the port nodes of the PMOS tube, and nodes 7, 8, 9, 10, 11, 12, 13, 14, and 15 represent the port nodes of the NMOS tube. The number corresponding to each node in the figure represents the node serial number. In this embodiment, according to the device information in the circuit netlist file, the port nodes of each component are sorted and labeled in ascending order. If the device is a MOS tube, the device port information is arranged in the order of D, G, and S in the netlist, and the serial number is incremented to give the device three consecutive serial numbers; if the device is a resistor, the device port information is arranged in the order of Min and Plus in the netlist, and the serial number is numbered. By analogy, the numbering of all components in the circuit is completed.

[0064] In a preferred embodiment, the port nodes of different types of components in the circuit are classified and labeled, and the same port nodes of the same type of components use the same label. For details, refer to Table 1:

[0065]

[0066] Table 1

[0067] According to Table 1, Figure 7 FIG. 4 shows a circuit topology label diagram of a differential amplifier circuit according to a specific embodiment of the present invention, as shown in FIG. Figure 7 As shown in the figure, in the process of circuit topology, different component nodes can be classified and distinguished, which is also an important basis for judging whether the two graphs are subgraph isomorphic. If the labels of the corresponding nodes in the two matched graphs are the same, the matching result satisfies one of the constraints of subgraph isomorphism. Therefore, according to the properties of the components in the circuit, such as the different ports of MOS tubes cannot be replaced, while the positive and negative ports of resistors can be replaced, it is beneficial for the subsequent algorithm to identify all components.

[0068] S3. Sort the node search order of the subcircuit, dynamically select several nodes of the analog integrated circuit according to the node search order of the subcircuit, and organize the nodes of the subcircuit and several nodes of the analog integrated circuit into multiple node pairs respectively, and organize them into a search tree according to the node pairs, wherein a tree node in the search tree represents a subgraph state.

[0069] By determining the node search order of the sub-circuit and the analog integrated circuit, and organizing a search tree according to multiple node pairs, the nodes of the sub-circuit and the analog integrated circuit are subsequently searched by tree search. Figure 8 FIG. 4 shows a flowchart of a tree search according to a specific embodiment of the present invention. Figure 8As shown, step S3 specifically includes the following steps:

[0070] S31a, determining the node search order of the subcircuit through probability calculation.

[0071] In the probability calculation, the number of corresponding nodes with the same node labels as the nodes of the sub-circuit found in the analog integrated circuit is calculated. If the number of corresponding nodes found in the analog integrated circuit is smaller, the probability of finding the corresponding nodes that meet the subgraph isomorphism requirements among these corresponding nodes with the same node labels is greater. Therefore, the search priority of the node corresponding to the sub-circuit is higher, which can reduce the redundancy of the search, thereby reducing the calculation complexity and shortening the matching time.

[0072] S31b, determining the node search order of the subcircuit by comparing the node degrees.

[0073] If you want to find a node in the analog integrated circuit that matches the node in the subcircuit, three conditions must be met: 1. The node labels of the analog integrated circuit node and the subcircuit node are the same; 2. The in-degree of the analog integrated circuit node is not less than the in-degree of the subcircuit node; 3. The out-degree of the analog integrated circuit node is not less than the out-degree of the subcircuit node. Among them, the in-degree of a node refers to the number of arcs (edges) that end at the node with the node as the arc head; the out-degree of a node refers to the number of arcs (edges) that start at the node with the node as the arc tail. Therefore, in comparing the node degree, by calculating the out-degree and in-degree of the subcircuit node, the higher the out-degree and in-degree of the subcircuit node, the greater the possibility of finding a node corresponding to the subcircuit in the analog integrated circuit that meets the subgraph isomorphism requirement, so the corresponding subcircuit node has a higher search priority. In this embodiment, in the process of determining the node search order of the subcircuit, the priority of probability calculation is higher than the priority of comparing node degrees. Therefore, if the node search order of the subcircuit has been determined in step S31a, step S31b is not required.

[0074] S32. According to the node search order of the sub-circuit, the last search node is identified as the parent node of the current search node, thereby selecting the candidate node of the current search in the node search process of the analog integrated circuit.

[0075] By introducing the concept of parent node, when the order relationship between the current search node of the subcircuit and its parent node is the same as the order relationship between the candidate node and its parent node, the node is searched as a candidate node. This can greatly narrow the scope of matching search in the nodes of the analog integrated circuit, thereby reducing the computational complexity.

[0076] S33, organizing the nodes of the sub-circuit and several nodes of the analog integrated circuit into a plurality of node pairs respectively, and organizing the node pairs into a search tree.

[0077] In the process of dynamically selecting the nodes of the analog integrated circuit according to the node search order of the sub-circuit, one node of the sub-circuit corresponds to several nodes of multiple analog integrated circuits, so multiple node pairs can be organized between the two, and the node pairs are organized into a search tree. Subsequently, the nodes of the sub-circuit and the analog integrated circuit can be searched in the search tree.

[0078] S4. Add the node pair to the tree node to form a new subgraph state, wherein when the node pair consisting of the nodes of the same subcircuit and the nodes of different analog integrated circuits is added, the search tree forms different branches.

[0079] As mentioned in step S32, in the process of dynamically selecting nodes of analog integrated circuits according to the node search order of sub-circuit, one node of the sub-circuit corresponds to several nodes of multiple analog integrated circuits. Therefore, as node pairs are gradually added, the search tree continues to grow and form multiple branches.

[0080] S5. Prune invalid branches in the search tree, so as to quickly match and identify nodes of sub-circuits and analog integrated circuits.

[0081] During the matching process, each selected node pair is added to the tree node to form a new subgraph state which may not be appropriate. Therefore, some invalid branches need to be pruned to further narrow the scope of matching search in the nodes of the analog integrated circuit, thereby improving the matching efficiency.

[0082] Continue to refer to Figure 8 Specifically, step S5 includes the following steps:

[0083] S51. Determine whether the subgraph state corresponding to the currently searched tree node satisfies the feasibility rule. If so, proceed to step S52; if not, proceed to step S53.

[0084] S52. Keep searching for the tree node branch.

[0085] S53: Perform a pruning operation on the tree node branch and abandon the search for the tree node branch.

[0086] For step S51, in order to better describe the definition of subgraph isomorphism, this embodiment explains it in detail through mathematical set relations. Assume that the subcircuit and the analog integrated circuit are G1 = (V1, E1) and G2 = (V2, E2), respectively, where V1 and V2 are the sets of nodes in the subcircuit and the analog integrated circuit, respectively, and E1 and E2 are the sets of edges in the subcircuit and the analog integrated circuit, respectively. The corresponding relationship between the nodes in graph G1 and the nodes in graph G2 is represented by set M, that is, If node u∈V1, then μ(vu)∈V2 represents the node in G2 corresponding to node u; if node v∈V2, then μ -1 (u)∈V1 represents the node in G1 corresponding to the node v. Where μ: is a single mapping function. When graphs G1 and G2 meet the following six constraints, the two graphs are considered to be in a subgraph isomorphic relationship. The six constraints are as follows:

[0087] (1) (u,μ(u))∈M; that is, for each node in G1, there must be a corresponding node in G2, and these pairs of nodes constitute the set M.

[0088] (2) That is, any two different nodes in G1 cannot correspond to the same node in G2.

[0089] (3) That is, for every edge in G1, there is an edge corresponding to it in G2, and the nodes at both ends of them correspond one to one.

[0090] (4) That is, for any two nodes in G1, if there is an edge between their corresponding nodes in G2, then there must also be an edge between the two nodes in G1.

[0091] (5) That is, the node labels of each pair of corresponding nodes must be the same.

[0092] (6) That is, the node labels of each pair of corresponding edges must be the same.

[0093] In the process of pruning invalid branches in the search tree, this embodiment defines the following two states for each node of the tree search according to the subgraph isomorphism constraint: (a) target state, the current subgraph state contains all nodes in the subcircuit, which means that a substructure in an analog integrated circuit is isomorphic to the subcircuit; (b) consistent state, the number of nodes in the current subgraph state has not yet reached the total number of nodes in the subcircuit, but the node pairs it has meet the 6 constraints of subgraph isomorphism. In the consistent state, it is determined whether the node pair is suitable to be added to the tree node to form a new subgraph state according to the feasibility rule, so as to decide whether to prune the tree node branch.

[0094] The feasibility rule contains the following four conditions:

[0095] 1. After adding a new node pair to the tree nodes of the search tree, the node labels of the corresponding nodes in the analog integrated circuit and the subcircuit are all the same;

[0096] 2. After adding a new node pair to the tree node of the search tree, the search tree is in a consistent state in the current subgraph state;

[0097] 3. After a new node pair is added to the tree node of the search tree, the subgraph state of the search tree in the next step is consistent;

[0098] 4. After a new node pair is added to the tree node of the search tree, the subgraph state of the search tree in the next two steps of search is consistent.

[0099] The feasibility rule predicts the possibility of successful matching by judging the subgraph status of the current search and the subgraph status of the future one-step search and two-step search, and prunes some tree node branches that are basically impossible to match successfully. This greatly reduces the computational complexity of the matching process while ensuring the quality of pruning (i.e., improving matching accuracy) and shortens the matching cycle.

[0100] S6. Based on the node matching output results of the sub-circuit and the analog integrated circuit, the output results of the nodes of the matched components that do not belong to the same component are screened out.

[0101] In the output matching results, there may be a situation where the matched component nodes do not belong to the same device. At this time, it is necessary to make a judgment to eliminate this error situation, so as to more accurately screen out the accurate output results.

[0102] The present invention proposes a subcircuit matching method for analog integrated circuits, which sets node labels for nodes of components in subcircuits and analog integrated circuits to distinguish different types of components, then adopts different graph topology forms for different types of components, and classifies and labels the port nodes of different types of components, generates circuit topology label graphs for subcircuits and analog integrated circuits, optimizes the circuit structure topology feature expression, and can perform more accurate symmetrical matching of different types of components. Then, by establishing a search tree, using a tree search scheme to sequentially add node pairs for search and adopting appropriate pruning rules, the circuit matching problem is converted into a subgraph isomorphism problem, while ensuring efficient search, making the time complexity much less than exponential growth. The present application can correctly find matching results in analog integrated circuits of small, medium, large and multiple mixed components, and the detection time is short.

[0103] In the embodiments of the present application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device / system / method embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0104] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0105] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0106] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0107] Obviously, those skilled in the art can make various modifications and changes to the embodiments of the present invention without departing from the spirit and scope of the present invention. In this way, if these modifications and changes are within the scope of the claims of the present invention and their equivalents, the present invention is also intended to cover these modifications and changes. The word "comprising" does not exclude the presence of other elements or steps not listed in the claims. The simple fact that certain measures are recorded in mutually different dependent claims does not indicate that the combination of these measures cannot be used to profit. Any reference numerals in the claims should not be considered to limit the scope.

Claims

1. A sub-circuit matching method for analog integrated circuits, characterized in that: The following steps are involved: S1. Read the circuit netlist file and define node labels for the component nodes in the subcircuit and the analog integrated circuit to distinguish different types of components; S2, topologically analyze the components in the sub-circuit and the analog integrated circuit respectively, and generate directed circuit topological graphs of the sub-circuit and the analog integrated circuit; S3, sorting the node search order of the subcircuit, including probability calculation and comparison of node degrees, the priority of the probability calculation is greater than the priority of the comparison of node degrees; dynamically selecting several nodes of the analog integrated circuit according to the node search order of the subcircuit, and organizing the nodes of the subcircuit and several nodes of the analog integrated circuit into multiple node pairs respectively, and organizing them into a search tree according to the node pairs, wherein a tree node in the search tree represents a subgraph state; dynamically selecting several nodes of the analog integrated circuit according to the node search order of the subcircuit includes identifying the previous search node as the parent node of the current search node according to the node search order of the subcircuit, thereby selecting the candidate node of the current search in the node search process of the analog integrated circuit; S4, adding the node pair to the tree node to form a new subgraph state, wherein when the node pair consisting of the node of the same subcircuit and the node of different analog integrated circuits is added, the search tree forms different branches; as well as S5. Prune invalid branches in the search tree, thereby quickly matching and identifying nodes of the subcircuit and the analog integrated circuit.

2. The method according to claim 1, characterized in that Defining node labels for the component nodes in the subcircuit and the analog integrated circuit in step S1 specifically includes: Define the signal terminal node labels, define the node labels of the power node and the ground node as 0 and N respectively; and Define component node labels to give unique node labels to specific ports of the component.

3. The method according to claim 1, characterized in that The topological analysis of the components in the subcircuit and the analog integrated circuit in step S2 specifically includes: taking the ports of the components as nodes and the connection relationships between the ports of the components as edges to establish the topological structure of the components.

4. The method according to claim 3, characterized in that The step of establishing the topological structure of the component specifically includes: Establishing an active device topology structure, wherein each port of the active device is connected to each other in a unilateral directed manner, and each port of the active device is connected to the ports of other components in a bilateral directed manner; and A passive device topology structure is established, wherein ports of the passive devices are connected in a bilaterally directed manner.

5. The method according to claim 4, characterized in that Generating the directed circuit topology diagram of the subcircuit and the analog integrated circuit in step S2 specifically includes: sorting and labeling the port nodes of each of the components in an ascending order.

6. The method according to claim 5, characterized in that After step S2 and before step S3, the method further includes: classifying and labeling the port nodes of the components of different types, using the same label for the same port nodes of the components of the same type, and generating a circuit topology label diagram of the subcircuit and the analog integrated circuit.

7. The method according to claim 1, characterized in that The step S3 of sorting the node search order of the subcircuit specifically includes: Probability calculation, calculating the number of corresponding nodes with the same node label as the node of the subcircuit found in the analog integrated circuit, the smaller the number of corresponding nodes in the analog integrated circuit, the greater the probability of finding the corresponding node that meets the subgraph isomorphism requirement, and the higher the search priority of the node corresponding to the subcircuit; and The node degrees are compared, and the out-degree and in-degree of the subcircuit nodes are calculated. The higher the out-degree and in-degree are, the higher the node search priority corresponding to the subcircuit is.

8. The method according to claim 1, characterized in that The selection principle of the candidate nodes in step S3 is: The order relationship between the current search node of the subcircuit and its parent node is the same as the order relationship between the candidate node and its parent node.

9. The method according to claim 1, characterized in that: The pruning of invalid branches of the search tree in step S5 specifically includes: determining whether the subgraph state of the currently searched tree node satisfies the feasibility rule; if not, determining that the tree node is an invalid node and abandoning the search for the tree node branch.

10. The method according to claim 9, characterized in that The feasibility rules specifically include: After the new node pair is added to the tree node of the search tree, the node labels of the corresponding nodes in the analog integrated circuit and the subcircuit are all the same, and the search tree is kept in a consistent state in the current subgraph state, the subgraph state of the next step, and the subgraph state of the next two steps, wherein the consistent state is specifically manifested as: After the new node pair is added to the tree node of the search tree, all the node pairs in the current subgraph state satisfy the subgraph isomorphism relationship.

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