Verification and Testing Methods for Reconfigurable FPGA Software

Abstract

The verification method disclosed in the present invention is used for on-board FPGA reconfigurable software verification. The verification test method comprises: a main control board receives a reconstruction configuration file and a verification test configuration file from a host computer; a first FPGA of the main control board stores the received configuration file in a main control board storage system, and performs a verification test execution reload program and a configuration release of a reload program of an FPGA to be tested according to actual test board requirements; a test execution FPGA of the test board calls a test execution FPGA reload program to generate a test execution FPGA dynamic test stimulus, and applies the dynamic test stimulus to the FPGA to be tested to perform a prototype verification test; the FPGA to be tested gives a test stimulus feedback to the test stimulus, and uploads and feeds back the test result through an interface control system; the host computer receives the FPGA verification test result for comparison and analysis to obtain the fault type and fault location, and at the same time, dynamically adjusts the verification file for the found or potential fault through a file configuration operation.

Description

Technical Field

[0001] The present invention relates to the field of computer software verification and testing, and in particular to a verification and testing method for reconfigurable FPGA software. Background Art

[0002] Field programmable logic device (FPGA) technology has achieved amazing development in the past few decades. The fundamental reason is that FPGA can not only solve the problems of miniaturization, low power consumption, and high reliability of electronic systems, but also has a short development cycle, low investment in development software, and continuously lower chip prices. These factors have prompted FPGA to increasingly replace ASIC in the market, especially for the demand for small-batch, multi-variety products, making FPGA the first choice.

[0003] Since there is currently no systematic and effective support for the implementation of FPGA reconfigurable verification testing, different reconstruction verification testing methods are often used to implement different FPGA software reconstruction implementation forms. In addition, for different chip selections, such as Xilinx's Virtex II, Virtex IV and Virtex V series, verification tests will be carried out for a single chip model.

[0004] In view of the actual verification and testing requirements of onboard reconfigurable FPGA, almost all verification tests can only be implemented through simulation, and it is impossible to carry out unified verification tests for different chip models. At the same time, due to the particularity of reconfigurable FPGA software, it is necessary to carry out unified verification tests on different reconfiguration software required to reconfigure the FPGA. At present, only simple individual software verification tests can be implemented through simulation, and it is impossible to truly implement the full-process follow-up verification test of reconfigurable FPGA software. In addition, it is very difficult to adjust the dynamic configurable test incentives for the characteristics of onboard reconfigurable FPGA software. At present, there is no efficient and general verification system for targeted verification of onboard reconfigurable FPGA software. Summary of the invention

[0005] The present invention provides a verification test method for reconfigurable FPGA software.

[0006] In one embodiment of the present invention, a verification test method for reconfigurable FPGA software is provided, comprising:

[0007] The main control board receives the reconstruction configuration file and the verification test configuration file from the host computer through the interface control system;

[0008] The first FPGA of the main control board stores the received configuration files in the storage system of the main control board through its internal logic, and performs verification test execution reload program and configuration release of the FPGA reload program to be tested through the interface control system according to the actual test board requirements;

[0009] The test execution FPGA of the test board calls the test execution FPGA reload program to generate a test execution FPGA dynamic test stimulus, and applies the dynamic test stimulus to the FPGA to be tested to perform a prototype verification test;

[0010] The FPGA to be tested provides test stimulus feedback to the test stimulus, and uploads the test result to the interface control system for feedback;

[0011] The test execution FPGA receives the test stimulus feedback, compares the test stimulus feedback with the defined behavior, and performs intelligent stimulus update through iterative test stimulus. After analyzing the comparison result, the test execution FPGA automatically reduces the test scope and performs targeted test operations on the test stimulus of the risky test point, and then acts on the FPGA to be tested again;

[0012] The host computer receives the FPGA verification test result, obtains the fault type and fault location by comparing and analyzing the feedback information with the identified correct behavior, and dynamically adjusts the verification file for the discovered or potential fault through file configuration operations, and transmits the modified verification file with a higher degree of fit again through the interface and downloads it to the verification board through the main control board for verification testing; and

[0013] The test executes an FPGA verification test after exchanging functions between the FPGA and the FPGA to be tested.

[0014] In one embodiment of the present invention, the host computer performs host computer user visualization operations.

[0015] In one embodiment of the present invention, the first FPGA is an anti-fuse FPGA.

[0016] In one embodiment of the present invention, the main control board has a first storage system, and the first storage system includes a solidified storage and a reconstructed storage.

[0017] In one embodiment of the present invention, the test execution FPGA and the FPGA to be tested are SRAM type FPGAs.

[0018] In one embodiment of the present invention, the test execution FPGA includes:

[0019] A test execution FPGA dynamic test stimulus generating unit is used to generate a test execution FPGA dynamic test stimulus based on a test execution FPGA reload program;

[0020] Verify test result intelligent comparison unit, used to compare test stimulus feedback with defined behaviors;

[0021] Iterative test stimulates the intelligent update unit, which is used to analyze based on the comparison results and automatically reduce the test scope and conduct targeted testing operations on risky test points.

[0022] In one embodiment of the present invention, the FPGA to be tested comprises:

[0023] The FPGA under test test stimulus feedback unit is used to provide test stimulus feedback to the test stimulus; and

[0024] The test result feedback unit is used to upload and feedback the test results through the interface control system.

[0025] The verification test system and verification test method for reconfigurable FPGA software provided by the present invention can improve the pertinence of FPGA software reconstruction test verification, the applicability to various reconstruction implementation forms, and the authenticity and efficiency of verification. The software and hardware work together to implement hardware verification testing of the reconfigurable FPGA software to be tested, which ensures the correctness of its functions while greatly shortening the software simulation time and greatly improving the authenticity of verification. The present invention provides a universal verification test system for on-orbit reconfigurable FPGA software on a satellite. The system can dynamically adjust the verification strategy of the target FPGA to be tested through a host computer or a satellite computer, and continuously approach the optimal verification conclusion. It fills the currently missing universal verification test system for on-orbit reconfigurable FPGA software on a satellite. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0027] Figure 1 A hardware block diagram of an FPGA reconstruction system is shown.

[0028] Figure 2 The block diagram of the hardware composition of the FPGA reconstruction system according to reconstruction scheme 1 is shown.

[0029] Figure 3 The block diagram of the hardware composition of the FPGA reconstruction system according to reconstruction scheme 2 is shown.

[0030] Figure 4 A verification flow chart is shown.

[0031] Figure 5 A schematic block diagram of a verification system 500 based on an on-board reconfigurable FPGA according to an embodiment of the present invention is shown.

[0032] Figure 6 A detailed block diagram of a verification system 600 based on an on-board reconfigurable FPGA according to an embodiment of the present invention is shown.

[0033] Figure 7 A schematic structural diagram of a main control board 620 according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0034] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments may be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention may be implemented without specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0035] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0036] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments may be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention may be implemented without specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0037] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0038] The general FPGA reconstruction implementation idea is to inject the reconstruction program into the corresponding FPGA program storage area from the ground, which requires the configuration of erasable programmable memory in the hardware design. Figure 1 shows a hardware block diagram of an FPGA reconstruction system.

[0039] FPGA reconstruction is usually implemented by CPU software to complete the integrity and correctness check of the reconstruction code. After the check is passed, the CPU software sends the reconstruction data to the FPGA. According to the different data receivers, FPGA software reconstruction schemes are usually divided into two types: Reconstruction scheme 1 SRAM (static random access memory) type FPGA receives data: the SRAM type FPGA receives the reconstruction code, then sends it to the anti-fuse FPGA, and writes it into the memory; Reconstruction scheme 2 Anti-fuse FPGA receives data: the anti-fuse FPGA directly receives the reconstruction code and writes it into the memory.

[0040] Figure 2 The hardware block diagram of the FPGA reconstruction system according to the reconstruction scheme 1 is shown. As shown in Figure 2, the SRAM type FPGA is connected to the CPU device and the anti-fuse FPGA, and the peripheral configuration memory 201 and the memory 202 are used for reset and program storage. Among them, the memory 201 is the program solidification area, and the memory 202 is the program reconstruction area. The same program code is burned before takeoff. When the on-orbit reconstruction occurs, the reconstruction area code is reconstructed first. After the test verification is correct, the ground determines whether to copy the solidification area program and other operations.

[0041] Compared with Scheme 1, the implementation of FPGA reconstruction scheme 2 is relatively simple in data transmission and reception processing, but it is necessary to add a communication interface connection between the anti-fuse FPGA and the CPU device. Figure 3 The block diagram of the hardware composition of the FPGA reconstruction system according to reconstruction scheme 2 is shown. The anti-fuse FPGA is directly connected to the CPU device.

[0042] For the above two FPGA reconstruction scheme implementation forms, the current verification test system can verify whether the complete code is written, whether the anti-fuse FPGA verification data is written correctly, whether the written program verification is correct, and other simple and intuitive information through the value of the telemetry return quantity. At the same time, the FPGA reconstruction timeline and other information are obtained by calculation. Its main purpose is to verify whether the reconfigurable FPGA design code meets the functional requirements in the design specification. The main verification process is as follows Figure 4As shown. In step 401, a verification plan is formulated and the function points to be verified are determined. Then, in step 402, a directional test case is written for the code to be tested using a hardware description language. In step 403, the reconfigurable code of the target to be tested is written. In step 404, waveform observation is performed. In step 405, during the verification process, the output waveform is observed to determine whether the designed function is correct. If so, in step 406, the verification is completed, otherwise, return to step 402.

[0043] The above-mentioned FPGA reconfigurable verification test is implemented by using different reconstruction verification test methods according to different FPGA software reconstruction implementation forms.

[0044] In order to adapt to different FPGA software reconstruction design implementation methods, and to cooperate with the FPGA reconstruction implementation under the current different FPGA model selection, the verification methods used in the prior art, such as: directional test case generation method, constrained random verification method, transaction-based verification method, coverage-driven verification method, assertion-based verification method, etc., are all helpful for functional test verification implementation, but they are unable to achieve the difficulties of reusability, high accuracy, and observability and controllability of verification. FPGA physical verification can make up for the disadvantages of software simulation, greatly shorten the simulation time, and improve the authenticity and reliability of simulation. The present invention proposes a verification system based on a satellite reconfigurable FPGA in combination with the above-mentioned hierarchical verification test scheme based on FPGA software reconstruction.

[0045] The verification system disclosed in the present invention is used for on-board FPGA reconfigurable software verification, and can perform verification tests on target codes to be tested in different implementation forms, different scales and different complexities. Figure 5 FIG. 5 is a schematic block diagram of a verification system 500 based on a satellite reconfigurable FPGA according to an embodiment of the present invention. Since FPGA has the characteristics of static programmability and online dynamic reconfiguration, this verification system uses a total of 3 FPGAs as the core components of the main control board and the test board. Figure 5 As shown, the verification test system 500 may include: a satellite service system / host computer 510, a main control board 520 and a test board 530.

[0046] In a specific embodiment of the present invention, the test board 530 may include a test execution FPGA 531, a dynamic program storage space 532, and a FPGA to be tested 533. For example, the test board 530 may use Xilinx's Virtex4 and Virtex5 series FPGAs as the test board core FPGA, the two FPGAs 531 and 533 on the test board are both SRAM type, and the hardware ensures that the general IOs are connected in pairs as much as possible. The two SRAM type main chips 531 and 533 of the hardware test verification system can be test execution FPGAs or FPGAs to be tested to meet the actual chip selection and function chip switching verification under aerospace requirements.

[0047] In a specific embodiment of the present invention, the main control board 520 may include an FPGA 521, an interface control 522, a dynamic program storage space 523, and a solidified program storage space 524. For example, the FPGA 521 may select ACTEL's A54SXA anti-fuse FPGA as the main control board mother chip, as the core chip of the main control board and at the same time realize the central operation of the reconfigurable. In the test, the corresponding storage media such as storage PROM, FLASH, EEPROM, the selection of the system global clock and the configurable module, the system reset logic, the FPGA chip download interface, the rich extension and connection interface, etc. are integrated to meet the verification and implementation of the reconfigurable test code. At the same time, in addition to adding necessary gate control processing, PLL phase-locked loop processing, etc., the verification test system also needs to make adjustments to the replacement use of storage units RAM and FIFO, as well as the rapid configuration of sub-modules and the processing of special units. And according to the specific FPGA reconstruction software, the constraints of FPGA-related timing control and pin IO are added.

[0048] The main control board is connected to the satellite service system or the host computer 510 through Ethernet and serial port for main control configuration. The satellite service system or the host computer 510 can realize the visualization display of the FPGA reconstruction software verification test, generate the configuration file for the chip under test, and even realize the fault type and fault location analysis.

[0049] As described above, the proposed verification and testing system 500 based on on-board reconfigurable FPGA software includes three levels, and each level is modularly established to maintain its own functional attributes while being flexible, coordinated, and unified.

[0050] The various modules of the verification system are described in detail below with reference to the accompanying drawings.

[0051] Figure 6 A detailed block diagram of a verification system 600 based on an on-board reconfigurable FPGA according to an embodiment of the present invention is shown.

[0052] The satellite service system / host computer 610 is the brain of the entire verification and test system. This module is mainly responsible for the following tasks: fault type and fault location analysis, host computer user visual operation interface, file configuration and interface transmission, etc.

[0053] Since the FPGA itself has limited resources and is implemented in the form of field programmable logic gate array, its fault type and fault location capabilities are poor. The fundamental purpose of verification testing is not only to verify whether the test function is correct, but also to analyze the type and location of the discovered or potential faults. Therefore, this solution feeds back the FPGA verification test results to the star service system / host computer, and obtains the fault type and fault location by comparing the feedback information with the correct behavior that has been identified. At the same time, for the discovered or potential faults, the verification file is dynamically adjusted through file configuration operations, and the modified verification file with a higher degree of fit is transmitted again through the interface in Ethernet, CAN or serial port mode and downloaded to the verification board through the main control board for verification testing. At the same time, for batch comparison operations, automated operations are more reasonable, but for operations that identify fault points or fine-tune configurations, the visual operation of the host computer user will bring great optimization operations, greatly improve the efficiency of verification testing, and accelerate the testing process.

[0054] The main control board 620 is the core of the entire verification system and is also the implementer of the onboard reconfigurable FPGA software. Figure 7 The schematic diagram of the structure of the main control board 620 according to an embodiment of the present invention is shown. The main control board 620 receives the reconstruction configuration file and the verification test configuration file from the satellite service system / host computer through the interface control system 622. The main chip of the main control board is the anti-fuse FPGA 621, which does not have the risk of single-particle upset on the satellite. The received configuration files are classified and stored in the main control board storage system through its internal logic, and the corresponding verification test execution reload program and the configuration release of the FPGA reload program to be tested are performed through the interface control system 622 according to the actual test board requirements. At the same time, the main chip also needs to perform overall control and storage planning operations on the storage system, divide the storage media such as programmable read-only memory PROM and FLASH contained in the storage system 623, and divide them into solidified storage and reconstruction storage.

[0055] The test board 630 is the core of the entire verification test system, and the module includes four parts: test execution FPGA 631, FPGA to be tested 633, reload program storage system 634, and interface control system 632. Among them, the reload program storage system includes the test execution FPGA reload program and the FPGA to be tested reload program.

[0056] The test execution FPGA 631 may be implemented by an SRAM type FPGA, which may include: a test execution FPGA dynamic test stimulus generation unit, a verification test result intelligent comparison unit, an iterative test stimulus intelligent update unit and other functional units.

[0057] The FPGA to be tested 633 is also implemented by an SRAM type FPGA, which may include: a test stimulus feedback unit for the FPGA to be tested, a test result feedback unit and other functional units. The test stimulus feedback unit for the FPGA to be tested is used to provide test stimulus feedback for the test stimulus. The test result feedback unit is used to upload and feedback the test result through the interface control system.

[0058] After calling the test execution FPGA reload program, the test execution FPGA 631 can generate a test execution FPGA dynamic test stimulus, and use the dynamic test stimulus to stimulate the FPGA to be tested through hardware to perform a prototype verification test. At the same time, the FPGA to be tested 633 will give a test stimulus feedback to the test stimulus, and upload the test results through the interface control system for feedback. After receiving the test stimulus feedback, the test execution FPGA 631 will perform intelligent stimulus updates through iterative test stimulus after intelligent comparison of the verification test results. The test execution FPGA 631 can perform preliminary analysis on the verification test feedback results, and automatically narrow the test scope, conduct targeted tests, and then act on the FPGA to be tested again for the test stimulus of the risky test points. In addition, the two FPGAs can be tested and executed by each other to facilitate the on-board reconfigurable FPGA chip requirements and dynamic resource adjustments. The entire verification test process constitutes a closed loop.

[0059] By comparing the information fed back by the FPGA 633 to be tested with the defined behavior inside the test FPGA 631, the fault type and fault location can be initially located. After the problem is found, the test FPGA 631 can dynamically adjust the verification file through file configuration operations, so that the errors or potential risk contents that may exist can be processed in a targeted and focused manner.

[0060] The verification test system and verification method of the reconfigurable FPGA software provided by the present invention can improve the pertinence of the FPGA software reconstruction test verification, the applicability to various reconstruction implementation forms, and the authenticity and efficiency of the verification. The software and hardware work together to implement hardware verification testing of the reconfigurable FPGA software to be tested, which ensures the correctness of its functions while greatly shortening the software simulation time and greatly improving the authenticity of the verification. The present invention provides a universal verification test system for on-orbit reconfigurable FPGA software on a satellite. The system can dynamically adjust the verification strategy of the target FPGA to be tested through a host computer or a satellite computer, and continuously approach the optimal verification conclusion. It fills the currently missing universal verification test system for on-orbit reconfigurable FPGA software on a satellite.

[0061] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A verification test method for reconfigurable FPGA software, comprising: The main control board receives the reconstruction configuration file and the verification test configuration file from the host computer through the interface control system; The first FPGA of the main control board stores the received configuration files in the storage system of the main control board through its internal logic, and performs verification test execution reload program and configuration release of the FPGA reload program to be tested through the interface control system according to the actual test board requirements; The test execution FPGA of the test board calls the test execution FPGA reload program to generate a test execution FPGA dynamic test stimulus, and applies the dynamic test stimulus to the FPGA to be tested to perform a prototype verification test; The FPGA to be tested provides test stimulus feedback to the test stimulus, and uploads the test result to the interface control system for feedback; The test execution FPGA receives the test stimulus feedback, compares the test stimulus feedback with the defined behavior, and performs intelligent stimulus update through iterative test stimulus. After analyzing the comparison result, the test execution FPGA automatically reduces the test scope and performs targeted test operations on the test stimulus of the risky test point, and then acts on the FPGA to be tested again; The host computer receives the FPGA verification test result, obtains the fault type and fault location by comparing and analyzing the feedback information with the identified correct behavior, and dynamically adjusts the verification file for the discovered or potential fault through file configuration operations, and transmits the modified verification file with a higher degree of fit again through the interface and downloads it to the verification board through the main control board for verification testing; and The test executes an FPGA verification test after the FPGA and the FPGA to be tested exchange functions.

2. The verification test method for reconfigurable FPGA software according to claim 1, characterized in that: The host computer performs the host computer user visualization operation.

3. The verification test method of reconfigurable FPGA software as claimed in claim 1, characterized in that: The first FPGA is an anti-fuse FPGA.

4. The verification test method of reconfigurable FPGA software as claimed in claim 1, characterized in that: The main control board has a first storage system, and the first storage system includes solidified storage and reconstructed storage.

5. The verification test method of reconfigurable FPGA software as claimed in claim 1, characterized in that: The test execution FPGA and the FPGA to be tested are SRAM type FPGAs.

6. The verification test method for reconfigurable FPGA software according to claim 1, characterized in that: The test execution FPGA includes: A test execution FPGA dynamic test stimulus generating unit is used to generate a test execution FPGA dynamic test stimulus based on a test execution FPGA reload program; Verify test result intelligent comparison unit, used to compare test stimulus feedback with defined behaviors; Iterative test stimulates the intelligent update unit, which is used to analyze based on the comparison results and automatically reduce the test scope and conduct targeted testing operations on risky test points.

7. The verification test method of reconfigurable FPGA software according to claim 1, characterized in that: The FPGA to be tested comprises: The FPGA under test test stimulus feedback unit is used to provide test stimulus feedback to the test stimulus; and The test result feedback unit is used to upload and feedback the test results through the interface control system.

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