A method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of NMOS transistors

Abstract

The method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor of the present invention comprises: preparing a series of calibration samples with the same solder layer porosity and different pore distribution positions; verifying the distribution of pores in the solder layer of each calibration sample by an ultrasonic scanning microscope; obtaining the relationship between the pore position and the thermal resistance parameter by a transient thermal resistance method; and determining the safe distribution range of the solder layer pores according to the relationship between the pore position and the thermal resistance parameter. The present invention quantitatively determines the safe distribution area of ​​the solder layer pores according to the solder pore-chip pad center point spacing, eliminates devices containing pores that significantly affect the heat dissipation performance, retains devices containing pores that do not significantly affect the heat dissipation performance, reduces unnecessary batch rejection, return to the factory and scrapping of NMOS transistors, improves the utilization rate of NMOS transistors, and solves the problem that the traditional method cannot quantitatively evaluate the degree of influence of the solder pore position on the heat dissipation performance of NMOS transistors.

Description

Technical Field

[0001] The invention relates to a detection technology in the field of electronic engineering, and in particular to a method for quantitatively evaluating a safe distribution area of ​​pores in a solder layer of an NMOS transistor. Background Art

[0002] In the process of preparing plastic-encapsulated NMOS transistors for aerospace use, the NMOS chip can be connected to the metal substrate through solder to achieve the fixation of the NMOS chip and circuit conduction. The bonding quality of the NMOS chip is mainly determined by factors such as the pore size, pore ratio and pore distribution inside the solder layer. During the aging and service process, the NMOS transistor is in a high current state. The presence of pores in the solder layer will significantly increase the thermal resistance of the solder layer, reduce the thermal conductivity of the heat dissipation path inside the device, and cause the chip temperature to rise significantly due to poor heat dissipation. However, not all pores will significantly increase the thermal resistance of the solder layer and reduce the thermal conductivity of the heat dissipation path of the device. Therefore, it is necessary to further determine the safe distribution range of the solder layer pores, eliminate devices with pores that significantly affect the heat dissipation performance, retain devices with pores that do not significantly affect the heat dissipation performance, reduce unnecessary batch rejection, return to the factory and scrapping of NMOS transistors, and improve the utilization rate of NMOS transistors.

[0003] At present, the pores in the solder layer of the plastic-encapsulated NMOS transistor are mainly detected by X-ray method, ultrasonic scanning microscopy method and thermal resistance test method. Among them, both X-ray method and ultrasonic scanning microscopy method can only detect whether there are pores in the solder layer of the NMOS transistor, and cannot evaluate the degree of influence of the pores in the solder layer on the heat dissipation performance of the device. The traditional thermal resistance test method can also detect whether there are pores inside the solder layer of the device. For example, the patent "A rapid evaluation method for the heat dissipation performance of the solid crystal layer of a high-power LED device" (application number 201510078344.9) discloses a method for detecting whether there are defects in the solid crystal layer of the device. The method extracts characteristic parameters characterizing the solid crystal layer and effectively identifies the pore defects in the solid crystal layer. However, the patent can only qualitatively determine whether there are defects in the solid crystal layer, and it is difficult to evaluate the degree of influence of pores at different positions on the heat dissipation performance of the device, and it is impossible to determine the safe distribution range of the pores. Only by quantitatively determining the degree of influence of pores at different positions on the heat dissipation performance of the device can it be determined whether the pores at a specific position will significantly affect the overall heat dissipation performance of the device, thereby effectively retaining the pores that do not significantly increase the thermal resistance of the device and reducing the return rate and scrap rate of the device. Summary of the invention

[0004] The purpose of the present invention is to provide a method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor, so as to solve the problem that the prior art cannot evaluate the influence of pores at different positions of the solder layer on the heat dissipation performance of the device.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor, comprising: preparing a series of calibration samples with the same solder layer porosity and different pore distribution positions; verifying the pore distribution of the solder layer of each calibration sample by an ultrasonic scanning microscope; obtaining the relationship between the pore position and the thermal resistance parameter by a transient thermal resistance method; and determining the safe distribution range of the solder layer pores based on the relationship between the pore position and the thermal resistance parameter.

[0006] The above-mentioned method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor, wherein the use of the transient thermal resistance method to obtain the relationship between the pore position and the thermal resistance parameters includes: using the transient thermal resistance method to determine the K coefficient of the calibration sample; monitoring the PN junction voltage drop of the calibration sample in the transient thermal resistance test, obtaining the integral function curve of the calibration sample through mathematical transformation, and extracting the thermal resistance parameters; superimposing the integral function curves of each calibration sample, determining the solder thermal resistance and total thermal resistance of the calibration sample with a specific solder layer porosity, and obtaining the relationship between the pore position of the solder layer and the thermal resistance parameters.

[0007] The above-mentioned method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor, wherein the preparation of a series of calibration samples with the same solder layer porosity and different pore distribution positions comprises: using a mask plate with a specific pattern to evaporate an Al2O3 ceramic film in the chip pad area on the metal substrate surface of the NMOS transistor to form solder layer pores; by designing the mask plate pattern, designing the area of ​​the Al2O3 ceramic film and the distance between the Al2O3 ceramic film and the center point of the chip pad area; the pattern design of each mask plate, the ratio of the area of ​​the Al2O3 ceramic film to the area of ​​the chip pad area is the same, and the distance between the Al2O3 ceramic film and the center point of the chip pad area is different, so as to obtain a series of calibration samples with the same solder layer porosity and different pore distribution positions.

[0008] The above-mentioned method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor, wherein, in monitoring the PN junction voltage drop of the calibration sample in the transient thermal resistance test, after coating thermal conductive silicone grease on the bottom of the metal substrate of the calibration sample, the calibration sample is fixed on a Cu block cold plate, and the temperature of the Cu block cold plate is kept constant.

[0009] The above method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor, wherein for each calibration sample, in the integral function curve of the calibration sample, the abscissa is the thermal resistance value, the ordinate is the thermal capacitance value, and the abscissa thermal resistance value corresponding to the origin to the first inflection point represents the NMOS chip PN junction thermal resistance x i The thermal resistance value on the horizontal axis from the first inflection point to the second inflection point represents the thermal resistance of the solder h. i The thermal resistance value on the horizontal axis corresponding to the second inflection point to the rightmost end of the integral function curve represents the sum of the thermal resistances of the metal substrate, thermal grease, and Cu block cold plate mi ; The thermal resistance value on the horizontal axis corresponding to the rightmost end of the integral function curve from the origin represents the total thermal resistance z of the calibration sample i , i=1,2,┄,N, N is the number of calibration samples; the relationship between the pore position and the thermal resistance parameter is: the NMOS chip PN junction thermal resistance of each calibration sample is equal; the solder thermal resistance of each calibration sample is different, and as the distance between the solder layer pore and the center point of the chip pad area increases, the solder thermal resistance decreases; the sum of the thermal resistances of the metal substrate, thermal grease and Cu block cold plate of each calibration sample is equal; the total thermal resistance of each calibration sample is different, and as the distance between the solder layer pore and the center point of the chip pad area increases, the total thermal resistance decreases; for any two calibration samples, the difference in total thermal resistance is equal to the corresponding difference in solder thermal resistance.

[0010] The above-mentioned method for quantitatively evaluating the safe distribution area of ​​the pores in the solder layer of the NMOS transistor, wherein the safe distribution range of the pores in the solder layer is determined according to the relationship between the pore position and the thermal resistance parameter, comprising: assuming that the maximum solder thermal resistance in the standard criterion of the thermal resistance of the NMOS transistor is h, and the maximum total thermal resistance is z; assuming that the distance between the pores in the solder layer of the i-th calibration sample and the center point of the chip pad area is r i , solder thermal resistance is h i , total thermal resistance z i , i=1,2,┄,N, N is the number of calibration samples, and r1<r2<┄<r N ; The solder thermal resistance h of each calibration sample i And the total thermal resistance z i Compare with h and z respectively. If the conditions h≥h1, z≥z1 are met, the area where the distance between the solder layer pores and the center point of the chip pad area is ≥r1 is the safe distribution range of the solder layer pores; if the conditions h are met, i-1 ≥h≥h i , z i-1 ≥z≥z i , i≠1, then the distance between the solder layer pore and the center point of the chip pad area ≥r i The area is the safe distribution range of the solder layer pores; if the condition h is met N ≥h,z N ≥z, there must be no solder layer voids anywhere in the chip pad area.

[0011] Compared with the prior art, the beneficial effects of the present invention include:

[0012] 1. The present invention can quantitatively determine the degree of influence of solder layer pores at different positions on the heat dissipation performance of the device based on the integral function curve and thermal resistance value of the calibration sample according to the known solder layer pore position, thereby determining the safe distribution area of ​​pores in the solder layer of the device of this type, solving the problem that the traditional method is difficult to evaluate the degree of influence of solder layer pores at different positions on the heat dissipation performance of the device; the present invention quantitatively determines the safe distribution area of ​​solder layer pores, eliminates devices containing pores that significantly affect the heat dissipation performance, and retains devices containing pores that do not significantly affect the heat dissipation performance, thereby reducing unnecessary batch rejection, return to the factory and scrapping of NMOS transistors, and improving the utilization rate of NMOS transistors;

[0013] 2. The present invention not only designs and prepares solder layer pores at different positions in the device solder layer and determines the relationship between the pore position and the thermal resistance parameter, but also reversely verifies the porosity and pore distribution position of the device solder layer by ultrasonic scanning microscopy, thereby ensuring the consistency of the porosity of the solder layer of different calibration samples and avoiding the difference between the designed pore position and the actual pore position of the same calibration sample;

[0014] 3. By adjusting the pattern of the mask plate, not only the pore distribution position of the solder layer can be changed, but also the porosity of the solder layer can be changed. Under the premise of ensuring that the NMOS chip has sufficient mechanical and electrical stability, the porosity of the solder layer can be changed within the range of 1-20%. For calibration samples with different solder layer porosities, the present invention can sequentially determine the corresponding solder layer pore safe distribution area;

[0015] 4. The present invention only needs to measure the transient thermal resistance parameters of the calibration sample with known solder layer pore position to determine the safe distribution range of the solder layer pore of the device. In the actual production process of this type of device, there is no need to test the transient thermal resistance parameters of the production device again. It is only necessary to perform ultrasonic scanning microscope detection on the production device to determine the solder pore position, and then combine the safe distribution range of the solder layer pore to determine whether the heat dissipation performance of the production device meets the screening requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor of the present invention is provided by the following embodiments and drawings.

[0017] Figure 1 The figure is a flow chart of a method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor according to a preferred embodiment of the present invention.

[0018] Figure 2 It is a schematic diagram of evaporating an Al2O3 ceramic film on the surface of a metal substrate covered with a mask plate in a preferred embodiment of the present invention.

[0019] Figure 3 Schematic diagram of coating solder on the chip pad area on the surface of a metal substrate in a preferred embodiment of the present invention.

[0020] Figure 4 It is a schematic diagram of welding an NMOS chip to a chip pad area on the surface of a metal substrate in a preferred embodiment of the present invention.

[0021] Figure 5 It is a schematic diagram of bonding an NMOS chip to a lead pad on the surface of a metal substrate in a preferred embodiment of the present invention.

[0022] Figure 6 It is a schematic diagram of the injection molding sealing cap for calibrating the sample in the preferred embodiment of the present invention.

[0023] Figure 7 This is a distribution diagram of solder layer pores in a preferred embodiment of the present invention, where the distances between the solder layer pores and the center points of the chip pad area are r1, r2, r3 and r4 respectively.

[0024] Figure 8 This is a cross-sectional view of the pore distribution position of the solder layer detected by an ultrasonic scanning microscope in a preferred embodiment of the present invention.

[0025] Fig. 9 This is a circuit diagram for testing transient thermal resistance of an NMOS transistor in a preferred embodiment of the present invention.

[0026] Fig.10 It is a cross-sectional diagram of a one-dimensional heat dissipation path of an NMOS transistor during a transient thermal resistance test in a preferred embodiment of the present invention.

[0027] Fig.11 It is an integral function curve corresponding to the calibration sample with a distance r1 between the solder layer pores and the center point of the chip pad area in a preferred embodiment of the present invention.

[0028] Fig.12 It is an overlay diagram of integral function curves corresponding to calibration samples whose spacings between the solder layer pores and the center points of the chip pad area are r1, r2, r3 and r4 respectively in a preferred embodiment of the present invention.

[0029] Fig.13 This is a diagram of the safe distribution area of ​​the solder layer porosity of a calibrated sample with a solder layer porosity of 1% in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined Figures 1 to 13 The method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor of the present invention is further described in detail.

[0031] The present invention solves the problem that the prior art cannot evaluate the degree of influence of pores at different positions of the solder layer on the heat dissipation performance of the device. The method of the present invention for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor comprises: preparing a series of calibration samples with the same solder layer porosity and different pore distribution positions; verifying the pore distribution of the solder layer of each calibration sample by ultrasonic scanning microscopy; obtaining the relationship between the pore position and the thermal resistance parameter by using a transient thermal resistance method; and determining the safe distribution range of the pores in the solder layer according to the relationship between the pore position and the thermal resistance parameter.

[0032] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0033] Figure 1 The figure is a flow chart of a method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor according to a preferred embodiment of the present invention.

[0034] See also Figure 1 The method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor according to an embodiment of the present invention comprises the following steps:

[0035] S10, preparing a series of NMOS transistors with a solder layer porosity of 1% and different pore distribution positions as calibration samples;

[0036] S11, such as Figure 2 The chip pad area 112 on the surface of the metal substrate 111 is used to solder the NMOS chip. The metal substrate 111 is covered with a mask plate 113 with a specific pattern. Except for a circular hole area 114 in the chip pad area 112 that is not covered by the mask plate 113, the rest of the metal substrate 111 is covered by the mask plate 113; Al2O3 ceramic with a thickness of 100um is evaporated in the chip pad area 112 covered with the mask plate 113, and Al2O3 ceramic film 115 is formed in the circular hole area 114 not covered with the mask plate, such as Figure 3 As shown, it is assumed that the area of ​​the Al2O3 ceramic film 115 is 1% of the area of ​​the chip pad region 112, and the distance between the Al2O3 ceramic film 115 and the center point 116 of the chip pad region 112 is r1;

[0037] S12, such as Figure 3 , removing the mask plate 113, and coating the tin-lead solder in the chip pad area 112 where the Al2O3 ceramic film 115 is not evaporated, as the solder coating area 117;

[0038] S13, such as Figure 4, placing the NMOS chip 118 on the chip pad area 112, the back side of the NMOS chip 118 contacts the Al2O3 ceramic film 115 and the solder coating area 117, placing the metal substrate 111 on the heating tube 119 for reflow soldering, so that the solder melts and connects the NMOS chip 118 and the chip pad area 112, because the molten tin-lead solder does not wet the Al2O3 ceramic film 115, the Al2O3 ceramic film 115 forms solder layer pores 120 of a specific size, and naturally cools to room temperature after the reflow soldering is completed;

[0039] S14, such as Figure 5 , the NMOS chip 118 is bonded to the pin pad 121 on the surface of the metal substrate 111; Figure 6 , performing injection molding to form a plastic-encapsulated tube shell 122, and obtaining a calibration sample with a solder layer porosity of 1% and a distance between the solder layer pore 120 and the center point 116 of the chip pad area being r1;

[0040] By designing masks with different patterns, calibration samples with a solder layer porosity of 1% and distances between the solder layer pores 120 and the center point 116 of the chip pad area are r1, r2, r3, and r4, respectively. Figure 7 As shown, in this embodiment, it is assumed that r1<r2<r3<r4;

[0041] S20, using ultrasonic scanning microscopy to verify the porosity and pore position distribution of the solder layer of each calibration sample;

[0042] like Figure 8 As shown, each calibration sample is scanned by an ultrasonic scanning microscope 123, and the ultrasonic wave passes through the plastic package tube shell 122, the NMOS chip 118, the solder layer pores 120, the solder coating area 117 and the metal substrate 111 in sequence, and the actual pore area P of the solder layer, the chip pad area Q and the distribution position of the solder layer pores 120 are obtained, and the actual porosity T of the solder layer is calculated (T=P / Q). If the actual porosity of the solder layer and the distribution position of the solder layer pores 120 are consistent with the experimental design, it shows that the solder layer pore distribution design method and preparation process are reasonable;

[0043] S30, determining the K factor of the calibration sample;

[0044] S31, according to Fig. 9The circuit diagram of the transient thermal resistance test of the NMOS transistor shown in the figure is used to connect the calibration sample; since there is a parasitic diode between the source S and the drain D of the calibration sample 131 (i.e., the NMOS transistor), the source-drain voltage drop can be used as a temperature sensitive parameter; since the actual directions of the IM test current 133 and the IH heating current 134 are opposite, three diodes are connected in series in the circuit as isolation diodes 135, so that the IH heating current 134 is displayed as a positive value (+), and the IM test current 133 is displayed as a negative value (-); since the source-drain voltage drop of the calibration sample 131 is opposite to the direction of the VF voltage sensor 132 of the T3ster device, the VF voltage sensor 132 is displayed as a negative value (-); the T3ster device is used to load only the IM test current 133 of 5mA on the calibration sample 131, and does not load the IH heating current 134, and the VF voltage sensor 132 is used to monitor the PN junction voltage drop change of the calibration sample 131 in real time;

[0045] S32, placing the calibration sample 131 in a constant temperature oil bath, the temperature of the constant temperature oil bath is equal to the PN junction temperature of the calibration sample, adjusting the temperature of the constant temperature oil bath so that the PN junction temperature of the calibration sample 131 gradually increases from 20°C to 160°C, the heating rate is 5°C / minute, the interval of the temperature monitoring points is set to 5°C, and the corresponding PN junction voltage drop is tested at each temperature monitoring point after the junction temperature of the calibration sample 131 is stable. After the test is completed, the PN junction voltage drop-junction temperature curve of the calibration sample, i.e., the K coefficient curve, is plotted;

[0046] Step S31 and step S32 are respectively performed on each calibration sample to obtain the K coefficient curve of each calibration sample;

[0047] S40, monitoring the PN junction voltage drop of the calibration sample, obtaining the integral function curve of the calibration sample through mathematical transformation, and extracting the thermal resistance parameter;

[0048] S41, such as Fig.10 As shown, after the thermal conductive silicone grease 129 is coated on the bottom of the metal substrate 111 of the calibration sample, the calibration sample 131 is fixed on the Cu block cold plate 130, and the temperature of the Cu block cold plate 130 is maintained at 20°C; during the transient thermal resistance test, the calibration sample 131 (NMOS transistor) satisfies the one-dimensional heat dissipation path, and the heat generated by the NMOS chip 118 is mainly conducted outward through the heat dissipation path of the solder coating area 117-metal substrate 111-thermal conductive silicone grease 129-Cu block cold plate 130;

[0049] S42, using the T3ster device to load the calibration sample 131 with an IH heating current 134 of 10A, and after the junction temperature of the calibration sample 131 reaches a thermal steady state, the IH heating current 134 is quickly switched to the IM test current 133 of 5mA, and the VF voltage sensor 132 of the T3ster device is used to monitor the PN junction voltage drop curve of the calibration sample 131, until the PN junction voltage drop of the calibration sample 131 reaches a stable value;

[0050] S43, using the K coefficient of the calibration sample obtained in step S30, converting the PN junction voltage drop curve into a transient temperature drop curve;

[0051] S44, converting the transient cooling curve into an integral function curve through mathematical transformation;

[0052] Execute steps S41 to S44 for each calibration sample to obtain an integral function curve of each calibration sample. Assume that the integral function curves corresponding to the calibration samples with the spacing between the solder layer pore and the center point of the chip pad area being r1, r2, r3 and r4 are j1, j2, j3 and j4 respectively.

[0053] Fig.11 is the integral function curve j1 corresponding to the calibration sample with a distance r1 between the pores of the solder layer and the center point of the chip pad area;

[0054] like Fig.11 As shown, in the integral function curve j1, the abscissa is the thermal resistance value, the ordinate is the thermal capacitance value, the abscissa thermal resistance value corresponding to the origin to the first inflection point represents the NMOS chip PN junction thermal resistance x1, the abscissa thermal resistance value corresponding to the first inflection point to the second inflection point represents the solder thermal resistance h1, the abscissa thermal resistance value corresponding to the second inflection point to the rightmost end of the integral function curve represents the sum of the thermal resistances of the metal substrate, thermal grease and Cu block cold plate m1; the abscissa thermal resistance value corresponding to the origin to the rightmost end of the integral function curve represents the total thermal resistance z1 (z1=x1+h1+m1) of the calibration sample;

[0055] Assume that the distance between the solder layer pore and the center point of the chip pad area is r2, r3 and r4, and the PN junction thermal resistance is x2, x3 and x4 respectively; the solder thermal resistance is h2, h3 and h4 respectively; the sum of the thermal resistance of the metal substrate, thermal grease and Cu block cold plate is m2, m3 and m4 respectively; the total thermal resistance is z2, z3 and z4 respectively;

[0056] S50, superimposing the integral function curves of each calibration sample, determining the solder thermal resistance and total thermal resistance of the calibration sample with a solder layer porosity of 1%, and obtaining the relationship between the solder layer porosity position and the thermal resistance parameter;

[0057] Fig.12The figure shows the integral function curve superposition diagram corresponding to the calibration samples with the distances between the solder layer pores and the center point of the chip pad area being r1, r2, r3 and r4 respectively;

[0058] like Fig.12 As shown in the superimposed integral function curve, the NMOS chip PN junction thermal resistance values ​​corresponding to the calibration samples with different solder layer pore positions are the same (i.e., x1=x2=x3=x4), and the integral function curve segments from the origin to the first inflection point also overlap with each other;

[0059] like Fig.12 As shown in the figure, the solder thermal resistance corresponding to the calibration samples with different solder layer pore positions is different. As the distance between the solder layer pore and the center point of the chip pad area increases from r1, r2, r3 to r4, the solder thermal resistance decreases from h1, h2, h3 to h4, and the integral function curve segment from the first inflection point to the second inflection point shifts to the left. The offset is related to the distance between the solder layer pore and the center point of the chip pad area. The larger the distance, the greater the left offset.

[0060] like Fig.12 As shown in the figure, the sum of the thermal resistances of the metal substrate, thermal grease and Cu block cold plate corresponding to the calibration samples with different pore positions in the solder layer is the same (i.e., m1=m2=m3=m4). Although the corresponding integral function curve segments do not overlap with each other, the basic trends are consistent.

[0061] like Fig.12 As shown, as the distance between the solder layer pores and the center point of the chip pad area increases from r1, r2, r3 to r4, the total thermal resistance of the calibration sample from the origin to the rightmost end of the integral function curve decreases from z1, z2, z3 to z4. For any two calibration samples, the difference in total thermal resistance is equal to the difference in the corresponding solder thermal resistance (i.e., z4-z1=h4-h1; z3-z1=h3-h1; z2-z1=h2-h1);

[0062] Step S60, determining the safe distribution range of the solder layer pores of the solder layer of the calibration sample with a solder layer porosity of 1% according to the relationship between the solder layer pore position and the thermal resistance parameter;

[0063] Fig.13 The figure shows the safe distribution area of ​​the solder layer porosity of the solder layer of the calibration sample with a porosity of 1%. Fig.13 As shown, the center point 116 of the chip pad area is taken as the origin, and the maximum radius of the pore distribution area of ​​the unqualified solder layer is set to r i 163, the distance between the solder layer pore and the center point of the chip pad area ≥ r i The area is the qualified solder layer pore distribution area 161, and the distance between the solder layer pore and the center point of the chip pad area is less than r iThe area is an unqualified solder layer pore distribution area 162, where i=1, 2, 3, 4;

[0064] like Fig.13 As shown, the maximum solder thermal resistance in the standard criterion for thermal resistance of NMOS transistor is set to h, and the maximum total thermal resistance is set to z;

[0065] If condition A is met (i.e., h≥h1, z≥z1), the area where the distance between the solder layer pores and the center point of the chip pad area is ≥r1 is the safe distribution range of the solder layer pores of the sample to be tested;

[0066] If condition B is met (i.e., h1≥h≥h2, z1≥z≥z2), the area where the distance between the solder layer pores and the center point of the chip pad area is ≥r2 is the safe distribution range of the solder layer pores of the sample to be tested;

[0067] If condition C is met (i.e., h2≥h≥h3, z2≥z≥z3), the area where the distance between the solder layer pores and the center point of the chip pad area is ≥r3 is the safe distribution range of the solder layer pores of the sample to be tested;

[0068] If condition D is met (i.e., h3≥h≥h4, z3≥z≥z4), the area where the distance between the solder layer pores and the center point of the chip pad area is ≥r4 is the safe distribution range of the solder layer pores of the sample to be tested;

[0069] If the condition E is satisfied (ie, h4≥h, z4≥z), there is no solder layer void safe distribution area in the entire chip pad area 112, and solder layer voids at any position of the chip pad area 112 cannot be accepted.

[0070] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.

Claims

1. A method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor, characterized in that: include: Prepare a series of calibration samples with the same solder layer porosity and different pore distribution positions; The pore distribution of the solder layer of each calibration sample was verified by ultrasonic scanning microscopy; The transient thermal resistance method is used to obtain the relationship between the pore position and the thermal resistance parameter; based on the relationship between the pore position and the thermal resistance parameter, the safe distribution range of the pores in the solder layer is determined; The relationship between the pore position and the thermal resistance parameter obtained by using the transient thermal resistance method includes: The K factor of the calibration sample is determined by the transient thermal resistance method; In the transient thermal resistance test, the PN junction voltage drop of the calibration sample is monitored, and the integral function curve of the calibration sample is obtained through mathematical transformation to extract the thermal resistance parameters; The integral function curves of each calibration sample are superimposed to determine the solder thermal resistance and total thermal resistance of the calibration sample with a specific solder layer porosity, and to obtain the relationship between the solder layer porosity position and the thermal resistance parameter; Determining the safe distribution range of the solder layer pores according to the relationship between the pore positions and the thermal resistance parameters includes: Assume that the maximum solder thermal resistance in the NMOS transistor thermal resistance standard criterion is h, and the maximum total thermal resistance is z; Assume that the distance between the pores in the solder layer of the i-th calibration sample and the center point of the chip pad area is r i , solder thermal resistance is h i , total thermal resistance z i , i=1,2,┄,N, N is the number of calibration samples, and r1<r2<┄<r N ; The solder thermal resistance h of each calibration sample i And the total thermal resistance z i Compare with h and z respectively. If the conditions h≥h1, z≥z1 are met, the area where the distance between the solder layer pores and the center point of the chip pad area is ≥r1 is the safe distribution range of the solder layer pores; if the conditions h are met, i-1 ≥h≥h i , z i-1 ≥z≥z i , i≠1, then the distance between the solder layer pore and the center point of the chip pad area ≥r i The area is the safe distribution range of the solder layer pores; if the condition h is met N ≥h,z N ≥z, there must be no solder layer voids anywhere in the chip pad area.

2. The method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor according to claim 1, characterized in that: The preparation of a series of calibration samples with the same solder layer porosity and different pore distribution positions comprises: An Al2O3 ceramic film is evaporated in the chip pad area on the metal substrate surface of the NMOS transistor using a mask with a specific pattern to form solder layer pores. The area of ​​the Al2O3 ceramic film and the distance between the Al2O3 ceramic film and the center point of the chip pad area are designed by designing the mask pattern. The pattern designs of each mask have the same ratio of the area of ​​the Al2O3 ceramic film to the area of ​​the chip pad area and different distances between the Al2O3 ceramic film and the center point of the chip pad area, so as to obtain a series of calibration samples with the same solder layer porosity and different pore distribution positions.

3. The method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor according to claim 1, characterized in that: In monitoring the PN junction voltage drop of the calibration sample in the transient thermal resistance test, after coating the bottom of the metal substrate of the calibration sample with thermal conductive silicone grease, the calibration sample is fixed on a Cu block cold plate, and the temperature of the Cu block cold plate is kept constant.

4. The method for quantitatively evaluating the safe distribution area of ​​pores in the solder layer of an NMOS transistor according to claim 3, characterized in that: For each calibration sample, in the integral function curve of the calibration sample, the horizontal axis is the thermal resistance value, the vertical axis is the thermal capacitance value, and the horizontal axis thermal resistance value corresponding to the origin to the first inflection point represents the NMOS chip PN junction thermal resistance x i The thermal resistance value on the horizontal axis from the first inflection point to the second inflection point represents the thermal resistance of the solder h. i The thermal resistance value on the horizontal axis corresponding to the second inflection point to the rightmost end of the integral function curve represents the sum of the thermal resistances of the metal substrate, thermal grease, and Cu block cold plate m i ; The thermal resistance value on the horizontal axis corresponding to the rightmost end of the integral function curve from the origin represents the total thermal resistance z of the calibration sample i , i=1,2,┄,N, N is the number of calibration samples; The relationship between the pore position and the thermal resistance parameter is: the NMOS chip PN junction thermal resistance of each calibration sample is equal; the solder thermal resistance of each calibration sample is different, and as the distance between the pores in the solder layer and the center point of the chip pad area increases, the solder thermal resistance decreases; the sum of the thermal resistances of the metal substrate, thermal grease and Cu block cold plate of each calibration sample is equal; the total thermal resistance of each calibration sample is different, and as the distance between the pores in the solder layer and the center point of the chip pad area increases, the total thermal resistance decreases; for any two calibration samples, the difference in total thermal resistance is equal to the corresponding difference in solder thermal resistance.

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