Semiconductor memory device

Abstract

The nanosheets (21 to 23) are arranged in the X direction in the order of the nanosheets (21 to 23). The nanosheets (24 to 26) are arranged in the X direction in the order of the nanosheets (24 to 26). In the embedded wiring layer, a power supply wiring (11) is formed between the nanosheet (22) and the nanosheet (25) in a plan view. The surface of one side, i.e., the first side, of the nanosheet (22) in the X direction is exposed from the gate wiring (32). The surface of the other side, i.e., the second side, of the nanosheet (25) in the X direction is exposed from the gate wiring (35).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device including a nanosheet FET (Field Effect Transistor), and particularly to a layout structure of a single-port SRAM (Static Random Access Memory) cell using a nanosheet FET (hereinafter also appropriately abbreviated as a cell). Background Art

[0002] SRAMs are widely used in semiconductor integrated circuits.

[0003] As a basic component of an LSI, a transistor has achieved an increase in integration density, a reduction in operating voltage, and an increase in operating speed by reducing the gate length (scaling). However, in recent years, the problem has arisen that excessive scaling causes an off-current, and the off-current causes a significant increase in power consumption. To solve this problem, active research has been started on three-dimensional transistors, that is, changing the transistor structure from the existing planar type to a three-dimensional type. Nanosheet FFT (nanowire FET) has attracted attention as one of the three-dimensional transistors.

[0004] Among nanosheet FETs, a fork sheet transistor in which the gate electrode is in a fork shape has been proposed. Layouts of SRAM cells using fork sheet transistors are disclosed in Non-Patent Documents 1 and 2, achieving a reduction in the area of the semiconductor memory device.

[0005] Non-Patent Document 1: P. Weckx et al., “Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm”, 2017 IEEE International Electron Devices Meeting (IEDM), December 2017, IEDM17-505~508

[0006] Non-Patent Document 2: P. Weckx et al., “Novel forksheet device architecture as ultimate logic scaling device towards 2nm”, 2019 IEEE International Electron Devices Meeting (IEDM), December 2019, IEDM19-871~874 Summary of the Invention

[0007] -Technical Problem to be Solved by the Invention-

[0008] In this specification, a nanosheet FET with a fork-shaped gate electrode is referred to as a fork-sheet transistor according to the prior art.

[0009] However, in Non-Patent Document 1, for a single-port SRAM cell, only the layout structure of each transistor is shown, and the structure including wiring is not studied in detail.

[0010] An object of the present disclosure is to suppress an increase in the area of a semiconductor memory device and at the same time achieve high speed and improved write characteristics of the semiconductor memory device in a layout structure of a single-port SRAM cell using a fork-sheet transistor.

[0011] -Technical Solution for Solving the Technical Problem-

[0012] In a first aspect of the present disclosure, a semiconductor memory device includes a single-port SRAM cell. The single-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. One node of the first transistor is connected to a first power supply that supplies a first voltage, and the other node is connected to a first node, and the gate is connected to a second node. One node of the second transistor is connected to the first power supply, and the other node is connected to the second node, and the gate is connected to the first node. One node of the third transistor is connected to the first node, and the other node is connected to a second power supply that supplies a second voltage, and the gate is connected to the second node. The second voltage is different from the first voltage. One node of the fourth transistor is connected to the second node, and the other node is connected to the second power supply, and the gate is connected to the first node. One node of the fifth transistor is connected to a first bit line, and the other node is connected to the first node, and the gate is connected to a word line. One node of the sixth transistor is connected to a second bit line, and the other node is connected to the second node, and the gate is connected to the word line. The second bit line and the first bit line form a complementary bit line pair. The first transistor includes a first nanosheet and a first gate wiring. The second transistor includes a second nanosheet and a second gate wiring. The third transistor includes a third nanosheet and a third gate wiring. The fourth transistor includes a fourth nanosheet and a fourth gate wiring. The fifth transistor includes a fifth nanosheet and a fifth gate wiring. The sixth transistor includes a sixth nanosheet and a sixth gate wiring. The first nanosheet to the sixth nanosheet extend in a first direction. The first gate wiring surrounds the outer periphery of the first nanosheet in a second direction and a third direction. The second gate wiring surrounds the outer periphery of the second nanosheet in a second direction and a third direction. The third gate wiring surrounds the outer periphery of the third nanosheet in a second direction and a third direction. The fourth gate wiring surrounds the outer periphery of the fourth nanosheet in a second direction and a third direction. The fifth gate wiring surrounds the outer periphery of the fifth nanosheet in a second direction and a third direction. The sixth gate wiring surrounds the outer periphery of the sixth nanosheet in a second direction and a third direction. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first direction and the second direction. The first nanosheet, the third nanosheet, and the sixth nanosheet are arranged in the second direction in the order of the sixth nanosheet, the first nanosheet, and the third nanosheet. The second nanosheet, the fourth nanosheet, and the fifth nanosheet are arranged in the second direction in the order of the fourth nanosheet, the second nanosheet, and the fifth nanosheet.The surfaces on either side of the first nanosheet in the second direction are exposed from the first gate wiring, the surfaces on either side of the second nanosheet in the second direction are exposed from the second gate wiring, the surfaces on either side of the third nanosheet in the second direction are exposed from the third gate wiring, the surfaces on either side of the fourth nanosheet in the second direction are exposed from the fourth gate wiring, the surfaces on either side of the fifth nanosheet in the second direction are exposed from the fifth gate wiring, and the surfaces on either side of the sixth nanosheet in the second direction are exposed from the sixth gate wiring. A first power supply wiring for supplying a first voltage is formed in a lower layer below the first to sixth transistors. When viewed from above, the first power supply wiring extends in the first direction between the first nanosheet and the second nanosheet and supplies the first voltage. The surface of the second side, which is the side opposite to the first side of the first nanosheet in the second direction, is exposed from the first gate wiring, and the first power supply wiring is formed on the first side of the first nanosheet. The surface of the first side, which is the side opposite to the second side of the second nanosheet in the second direction, is exposed from the second gate wiring, and the first power supply wiring is formed on the second side of the second nanosheet.

[0013] According to the present disclosure, a first power supply wiring for supplying a first voltage is formed in a lower layer below the first to sixth transistors. Therefore, for example, in an upper layer above the first to sixth transistors, the width of the wiring for supplying the first voltage can be reduced (or this wiring can be omitted). In this way, the widths of the wirings that become the first bit line and the second bit line can be increased, and thus the high-speed operation and the improvement of the writing characteristics of the semiconductor memory device can be achieved.

[0014] When viewed from above, the first power supply wiring is formed between the first nanosheet and the second nanosheet. The surfaces of the first nanosheet and the second nanosheet on the side facing each other in the second direction are not exposed from the first gate wiring and the second gate wiring, respectively. That is, when viewed from above, the first power supply wiring is formed between the first transistor and the second transistor, and the distance between the first transistor and the second transistor in the second direction is large. In this way, an increase in the area of the semiconductor memory device can be suppressed.

[0015] Therefore, in the layout structure of the single-port SRAM cell using the cross-sheet transistor, an increase in the area of the semiconductor memory device can be suppressed, and at the same time, the high-speed operation and the improvement of the writing characteristics of the semiconductor memory device can be achieved.

[0016] In a second aspect of the present disclosure, a semiconductor memory device includes a single-port SRAM cell. The single-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. One node of the first transistor is connected to a first power supply that supplies a first voltage, another node is connected to a first node, and a gate is connected to a second node. One node of the second transistor is connected to the first power supply, another node is connected to the second node, and a gate is connected to the first node. One node of the third transistor is connected to the first node, another node is connected to a second power supply that supplies a second voltage, and a gate is connected to the second node. The second voltage is different from the first voltage. One node of the fourth transistor is connected to the second node, another node is connected to the second power supply, and a gate is connected to the first node. One node of the fifth transistor is connected to a first bit line, another node is connected to the first node, and a gate is connected to a word line. One node of the sixth transistor is connected to a second bit line, another node is connected to the second node, and a gate is connected to the word line. The second bit line and the first bit line form a complementary bit line pair. The first transistor includes a first nanosheet and a first gate wiring. The second transistor includes a second nanosheet and a second gate wiring. The third transistor includes a third nanosheet and a third gate wiring. The fourth transistor includes a fourth nanosheet and a fourth gate wiring. The fifth transistor includes a fifth nanosheet and a fifth gate wiring. The sixth transistor includes a sixth nanosheet and a sixth gate wiring. The first nanosheet to the sixth nanosheet extend in a first direction. The first gate wiring surrounds the outer periphery of the first nanosheet in a second direction and a third direction. The second gate wiring surrounds the outer periphery of the second nanosheet in a second direction and a third direction. The third gate wiring surrounds the outer periphery of the third nanosheet in a second direction and a third direction. The fourth gate wiring surrounds the outer periphery of the fourth nanosheet in a second direction and a third direction. The fifth gate wiring surrounds the outer periphery of the fifth nanosheet in a second direction and a third direction. The sixth gate wiring surrounds the outer periphery of the sixth nanosheet in a second direction and a third direction. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first direction and the second direction. The first nanosheet, the third nanosheet, and the sixth nanosheet are arranged in the second direction in the order of the sixth nanosheet, the first nanosheet, and the third nanosheet. The second nanosheet, the fourth nanosheet, and the fifth nanosheet are arranged in the second direction in the order of the fourth nanosheet, the second nanosheet, and the fifth nanosheet.A surface on either side of the first nanosheet in the second direction is exposed from the first gate wiring, a surface on either side of the second nanosheet in the second direction is exposed from the second gate wiring, a surface on either side of the third nanosheet in the second direction is exposed from the third gate wiring, a surface on either side of the fourth nanosheet in the second direction is exposed from the fourth gate wiring, a surface on either side of the fifth nanosheet in the second direction is exposed from the fifth gate wiring, and a surface on either side of the sixth nanosheet in the second direction is exposed from the sixth gate wiring. A surface of the first side of the first nanosheet is exposed from the first gate wiring, and the first side is a side opposed to the second nanosheet in the second direction. A surface of the second side of the second nanosheet is exposed from the second gate wiring, and the second side is a side opposed to the first nanosheet in the second direction. A first power supply wiring is formed in a lower layer below the first transistor to the sixth transistor. When viewed from above, the first power supply wiring extends along the first direction on the second side of the first nanosheet and supplies the first voltage or the second voltage. A second power supply wiring is formed in a lower layer below the first transistor to the sixth transistor. When viewed from above, the second power supply wiring extends along the first direction on the second side of the second nanosheet and supplies the first voltage or the second voltage.

[0017] According to the present disclosure, a first power supply wiring for supplying the first voltage or the second voltage is formed in a lower layer below the first transistor to the sixth transistor. A second power supply wiring for supplying the first voltage or the second voltage is formed in a lower layer below the first transistor to the sixth transistor. Therefore, for example, in an upper layer above the first transistor to the sixth transistor, the width of the wiring for supplying the first voltage or the second voltage can be reduced (or the wiring can be omitted). In this way, the width of the wiring that becomes the first bit line and the second bit line can be increased, and thus the high speed operation and the improvement of the writing characteristics of the semiconductor memory device can be achieved.

[0018] When viewed from above, the first power supply wiring is formed on the first side of the second nanosheet. When viewed from above, the second power supply wiring is formed on the second side of the first nanosheet. A surface of the first side of the second nanosheet is not exposed from the second gate wiring. A surface of the second side of the first nanosheet is not exposed from the first gate wiring. That is, when viewed from above, the first power supply wiring is formed on the first side of the second transistor, where the distance in the second direction between the transistors is large. When viewed from above, the second power supply wiring is formed on the second side of the first transistor, where the distance in the second direction between the transistors is large. In this way, an increase in the area of the semiconductor memory device can be suppressed.

[0019] Therefore, in the layout structure of a single-port SRAM cell using a fork transistor, it is possible to suppress an increase in the area of the semiconductor memory device while achieving high speed operation and improved write characteristics of the semiconductor memory device.

[0020] In a third aspect of the present disclosure, a semiconductor memory device includes a single-port SRAM cell. The single-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. One node of the first transistor is connected to a first power supply that supplies a first voltage, another node is connected to a first node, and a gate is connected to a second node. One node of the second transistor is connected to the first power supply, another node is connected to the second node, and a gate is connected to the first node. One node of the third transistor is connected to the first node, another node is connected to a second power supply that supplies a second voltage, and a gate is connected to the second node. The second voltage is different from the first voltage. One node of the fourth transistor is connected to the second node, another node is connected to the second power supply, and a gate is connected to the first node. One node of the fifth transistor is connected to a first bit line, another node is connected to the first node, and a gate is connected to a word line. One node of the sixth transistor is connected to a second bit line, another node is connected to the second node, and a gate is connected to the word line. The second bit line and the first bit line form a complementary bit line pair. The first transistor includes a first nanosheet and a first gate wiring. The second transistor includes a second nanosheet and a second gate wiring. The first nanosheet and the second nanosheet extend in a first direction. The first gate wiring surrounds the outer periphery of the first nanosheet in a second direction and a third direction. The second gate wiring surrounds the outer periphery of the second nanosheet in the second direction and the third direction. The second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and the second direction. The third transistor includes a third gate wiring and a plurality of third nanosheets. The fourth transistor includes a fourth gate wiring and a plurality of fourth nanosheets. The fifth transistor includes a fifth gate wiring and a plurality of fifth nanosheets. The sixth transistor includes a sixth gate wiring and a plurality of sixth nanosheets. The plurality of third nanosheets to the plurality of sixth nanosheets extend in the first direction. The third gate wiring surrounds the outer periphery of the plurality of third nanosheets in the second direction and the third direction. The fourth gate wiring surrounds the outer periphery of the plurality of fourth nanosheets in the second direction and the third direction. The fifth gate wiring surrounds the outer periphery of the plurality of fifth nanosheets in the second direction and the third direction. The sixth gate wiring surrounds the outer periphery of the plurality of sixth nanosheets in the second direction and the third direction. The first nanosheet, the plurality of third nanosheets, and the plurality of sixth nanosheets are arranged in the second direction in the order of the plurality of sixth nanosheets, the first nanosheet, and the plurality of third nanosheets. The second nanosheet, the plurality of fourth nanosheets, and the plurality of fifth nanosheets are arranged in the second direction in the order of the plurality of fourth nanosheets, the second nanosheet, and the plurality of fifth nanosheets.The surfaces on either side of the first nanosheet in the second direction are exposed from the first gate wiring, and the surfaces on either side of the second nanosheet in the second direction are exposed from the second gate wiring. The surfaces on either side of each of the plurality of third nanosheets in the second direction are exposed from the third gate wiring. The surfaces on either side of each of the plurality of fourth nanosheets in the second direction are exposed from the fourth gate wiring. The surfaces on either side of each of the plurality of fifth nanosheets in the second direction are exposed from the fifth gate wiring. The surfaces on either side of each of the plurality of sixth nanosheets in the second direction are exposed from the sixth gate wiring. A plurality of power supply wirings are formed in a lower layer below the first transistor to the sixth transistor, and the plurality of power supply wirings extend in the first direction and supply the second voltage. At least one of the plurality of power supply wirings is formed on the side opposite to the side from which the third gate wiring is exposed in the second direction when viewed from above among the plurality of third nanosheets. At least one of the plurality of power supply wirings is formed on the side opposite to the side from which the fourth gate wiring is exposed in the second direction when viewed from above among the plurality of fourth nanosheets. At least one of the plurality of power supply wirings is formed on the side opposite to the side from which the fifth gate wiring is exposed in the second direction when viewed from above among the plurality of fifth nanosheets. At least one of the plurality of power supply wirings is formed on the side opposite to the side from which the sixth gate wiring is exposed in the second direction when viewed from above among the plurality of sixth nanosheets.

[0021] According to the present disclosure, a plurality of power supply wirings for supplying the first voltage or the second voltage are formed in a lower layer below the first transistor to the sixth transistor. Therefore, for example, in the upper layer above the first transistor to the sixth transistor, the width of the wiring for supplying the first voltage or the second voltage can be reduced (or the wiring can be omitted), and thus the width of the wiring that becomes the first bit line and the second bit line can be increased. In this way, high-speed operation of the semiconductor memory device and improvement of the writing characteristics can be achieved.

[0022] Among the plurality of third nanosheets, there is a third nanosheet in which a power supply wiring is formed on a side that is not exposed from the third gate wiring in the second direction in a plan view. Among the plurality of fourth nanosheets, there is a fourth nanosheet in which a power supply wiring is formed on a side that is not exposed from the fourth gate wiring in the second direction in a plan view. Among the plurality of fifth nanosheets, there is a fifth nanosheet in which a power supply wiring is formed on a side that is not exposed from the fifth gate wiring in the second direction in a plan view. Among the plurality of sixth nanosheets, there is a sixth nanosheet in which a power supply wiring is formed on a side that is not exposed from the sixth gate wiring in the second direction in a plan view. That is, in a plan view, the power supply wiring is formed at a position where the distance in the second direction between the transistors is relatively large. In this way, an increase in the area of the semiconductor memory device can be suppressed.

[0023] Therefore, in the layout structure of a single-port SRAM cell using cross-sheet transistors, an increase in the area of the semiconductor memory device can be suppressed, and at the same time, high-speed operation and improved write characteristics of the semiconductor memory device can be achieved.

[0024] - Effects of the Invention -

[0025] According to the present disclosure, in the layout structure of a single-port SRAM cell using cross-sheet transistors, an increase in the area of the semiconductor memory device can be suppressed, and at the same time, high-speed operation and improved write characteristics of the semiconductor memory device can be achieved. Description of the Drawings

[0026] Figure 1 is a plan view showing an example of the layout structure of a single-port SRAM cell according to the first embodiment.

[0027] Figure 2 is a cross-sectional view showing an example of the layout structure of a single-port SRAM cell according to the first embodiment.

[0028] Figure 3 is a cross-sectional view showing an example of the layout structure of a single-port SRAM cell according to the first embodiment.

[0029] Figure 4 is a circuit diagram showing the configuration of a single-port SRAM cell according to the first embodiment.

[0030] Figure 5 is a plan view showing another example of the layout structure of a single-port SRAM cell according to the first embodiment.

[0031] Figure 6 is a cross-sectional view showing another example of the layout structure of a single-port SRAM cell according to the first embodiment.

[0032] Figure 7It is a top view showing another example of the layout structure of the single-port SRAM cell according to the first embodiment.

[0033] Figure 8 It is a top view showing an example of the layout structure of the single-port SRAM cell according to the second embodiment.

[0034] Figure 9 It is a top view showing another example of the layout structure of the single-port SRAM cell according to the second embodiment.

[0035] Figure 10 It is a top view showing an example of the layout structure of the single-port SRAM cell according to the third embodiment.

[0036] Figure 11 It is a top view showing another example of the layout structure of the single-port SRAM cell according to the third embodiment.

[0037] Figure 12 It is a top view showing another example of the layout structure of the single-port SRAM cell according to the third embodiment.

[0038] Figure 13 It is a top view showing another example of the layout structure of the single-port SRAM cell according to the third embodiment.

[0039] Figure 14 It is a diagram showing the basic structure of the fork FET. Detailed Embodiments

[0040] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, the semiconductor memory device includes a plurality of SRAM cells (appropriately abbreviated as cells in this specification), and at least a part of the plurality of SRAM cells includes a fork transistor in which the gate electrode is in a fork shape in a nanosheet FET (nanowire FET). The nanosheet FET is an FET formed using a thin sheet (nanosheet) through which current flows. The nanosheet is formed of silicon, for example. In the semiconductor integrated circuit device, a part of the nanosheet FET is a fork FET in which the gate electrode is in a fork shape.

[0041] In the present disclosure, the semiconductor layer portion that is formed at both ends of the nanosheet and constitutes the terminal serving as the source or drain of the nanosheet FET is referred to as a "pad". In addition, in the following description, in Figure 1 top views such as, the longitudinal direction of the drawing is set as the Y direction (corresponding to the first direction), the lateral direction of the drawing is set as the X direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is set as the Z direction (corresponding to the third direction).

[0042] (Structure of the Fork)

[0043] Figure 14 FIG. 2 is a diagram showing the basic structure of a finFET, where (a) is a top view and (b) is a cross-sectional view taken along line Y-Y' in (a). In Figure 14 the basic structure, two transistors TR1 and TR2 are arranged with a gap S in the Y direction. The gate wiring 531 that forms the gate of transistor TR1 and the gate wiring 532 that forms the gate of transistor TR2 both extend in the Y direction and are arranged at the same position in the X direction.

[0044] The channel portions 521 that form the channel regions of transistor TR1 and 526 that form the channel regions of transistor TR2 are composed of nanosheets. In Figure 14 this structure, the channel portions 521 and 526 are respectively composed of nanosheets formed by three sheet-like structures that overlap in a top view. On both sides of the channel portion 521 in the X direction, pads 522a and 522b that form the source region or drain region of transistor TR1 are formed. On both sides of the channel portion 526 in the X direction, pads 527a and 527b that form the source region or drain region of transistor TR2 are formed. The pads 522a and 522b are formed by epitaxial growth of the nanosheets that make up the channel portion 521. The pads 527a and 527b are formed by epitaxial growth of the nanosheets that make up the channel portion 526.

[0045] The gate wiring 531 surrounds the outer periphery of the channel portion 521 composed of nanosheets in the Y and Z directions with a gate insulating film (not shown) interposed therebetween. However, the surface of the nanosheets that make up the channel portion 521 on the side closer to transistor TR2 in the Y direction is not covered by the gate wiring 531 but is exposed from the gate wiring 531. That is, in Figure 14 the cross-sectional view of (b) of FIG. 2, the gate wiring 531 does not cover the right side of the drawing of the nanosheets that make up the channel portion 521, but covers the upper side, left side, and lower side of the drawing. The gate wiring 531 overlaps on the side opposite to transistor TR2 in the Y direction with respect to the nanosheets that make up the channel portion 521, and the overlap amount is a length OL.

[0046] The gate wiring 532 surrounds the outer periphery of the channel portion 526 composed of nanosheets in the Y and Z directions with a gate insulating film (not shown) interposed therebetween. However, the surface of the nanosheets that make up the channel portion 526 on the side closer to transistor TR1 in the Y direction is not covered by the gate wiring 532 but is exposed from the gate wiring 532. That is, in Figure 14In the cross-sectional view of (b), the gate wiring 532 does not cover the left side of the drawing of the nanosheets constituting the channel portion 526, but covers the upper side, right side, and lower side of the drawing. The gate wiring 532 overlaps with the nanosheets constituting the channel portion 526 on the side opposite to the transistor TR1 in the Y direction, and the overlap amount is the length OL.

[0047] If the width (dimension in the Y direction) of each nanosheet is set to W and the height (dimension in the Z direction) is set to H, the effective gate width Weff is:

[0048] Weff = 2×W + H.

[0049] Since the channel portions 521 of the transistor TR1 and the channel portions 526 of the transistor TR2 are both composed of three nanosheets, the effective gate widths of the transistors TR1 and TR2 are:

[0050] 3×(2×W + H).

[0051] According to Figure 14 the structure, the gate wiring 531 does not overlap with the nanosheets constituting the channel portion 521 on the side closer to the transistor TR2 in the Y direction. In addition, the gate wiring 532 does not overlap with the nanosheets constituting the channel portion 526 on the side closer to the transistor TR1 in the Y direction. In this way, the transistors TR1 and TR2 can be made closer to each other, and thus miniaturization can be achieved.

[0052] It should be noted that the number of nanosheets constituting the channel portion of the transistor is not limited to three. That is to say, the nanosheets can be formed by a single sheet-like structure, or can be formed by multiple sheet-like structures overlapping when viewed from above. In addition, in Figure 14 the (b), the cross-sectional shape of the nanosheets is rectangular, but it is not limited to this. For example, the cross-sectional shape of the nanosheets can also be square, circular, elliptical, etc.

[0053] Cross-sheet FETs and nanosheet FETs can coexist in the semiconductor integrated circuit device, and the entire periphery of the nanosheets of the nanosheet FET is surrounded by gate wiring.

[0054] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In addition, in this specification, expressions such as "the same wiring width" that mean equality of width, etc. include the manufacturing deviation range.

[0055] In this specification, the semiconductor layer portions formed at both ends of the nanosheets and constituting the terminals that become the source or drain of the transistor are called "pads".

[0056] In the top views and cross-sectional views in the following embodiments, illustration of each insulating film and the like may sometimes be omitted. In the top views and cross-sectional views in the following embodiments, the nanosheet and the pads on both sides thereof may sometimes be drawn in a simplified linear shape. In this specification, expressions such as "the same size" that mean equality of dimensions and the like include the range of manufacturing deviations.

[0057] In this specification, the source and drain of a transistor are appropriately referred to as the "nodes" of the transistor. That is, one node of a transistor refers to the source or drain of the transistor, and two nodes of a transistor refer to the source and drain of the transistor.

[0058] In the following embodiments and their modified examples, the same symbols may sometimes be assigned to the same components and the like, and their descriptions may be omitted.

[0059] (First Embodiment)

[0060] Figures 1 to 3 is a diagram showing an example of the layout structure of a single-port SRAM cell according to the first embodiment. Figure 1 of (a), Figure 1 of (b) is a top view, Figure 2 of (a) to Figure 2 of (c) and Figure 3 of (a), Figure 3 of (b) are cross-sectional views taken along the horizontal direction when viewed from above. Specifically, Figure 1 of (a) shows the upper part of the cell, i.e., the M1 and M2 wiring layers, Figure 1 of (b) shows the lower part of the cell, which is the part including the nanosheet FETs and is located below the M1 and M2 wiring layers. Figure 2 of (a) shows the cross-section taken along line X1-X1', Figure 2 of (b) shows the cross-section taken along line X2-X2', Figure 2 of (c) shows the cross-section taken along line X3-X3', Figure 3 of (a) shows the cross-section taken along line X4-X4', Figure 3 of (b) shows the cross-section taken along line X5-X5'.

[0061] Figure 4 is a circuit diagram showing the configuration of a single-port SRAM cell according to the first embodiment. As Figure 4 shown, in the single-port SRAM cell, a single-port SRAM circuit is constituted by load transistors PU1, PU2, drive transistors PD1, PD2, and access transistors PG1, PG2. The load transistors PU1, PU2 are P-type FETs, and the drive transistors PD1, PD2 and the access transistors PG1, PG2 are N-type FETs.

[0062] The load transistor PU1 is provided between the power supply VDD and the first node NA, and the drive transistor PD1 is provided between the first node NA and the power supply VSS. The gates of the load transistor PU1 and the drive transistor PD1 are connected to the second node NB, thereby forming an inverter INV1. The load transistor PU2 is provided between the power supply VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the load transistor PU2 and the drive transistor PD2 are connected to the first node NA, thereby forming an inverter INV2. That is to say, the output of one inverter is connected to the input of the other inverter, and in this way, a latch is formed.

[0063] The access transistor PG1 is provided between the bit line BL and the first node NA, and its gate is connected to the word line WL. The access transistor PG2 is provided between the bit line BLB and the second node NB, and its gate is connected to the word line WL. It should be noted that the bit lines BL and BLB form a complementary bit line pair.

[0064] In the single-port SRAM circuit, after the bit lines BL and BLB forming the complementary bit line pair are respectively driven to high level and low level, and the word line WL is driven to high level, the high level is written into the first node NA, and the low level is written into the second node NB. On the other hand, after the bit lines BL and BLB are respectively driven to low level and high level, and the word line WL is driven to high level, the low level is written into the first node NA, and the high level is written into the second node NB. And, in the state where data has been respectively written into the first node NA and the second node NB, after the word line WL is driven to low level, the latch state is determined, thereby maintaining the data written into the first node NA and the second node NB.

[0065] After the bit lines BL and BLB are precharged to high level in advance, and the word line WL is driven to high level, the states of the bit lines BL and BLB are respectively determined according to the data written into the first node NA and the second node NB, so that data can be read out from the SRAM cell. Specifically, if the first node NA is at high level and the second node NB is at low level, the bit line BL remains at high level, and the bit line BLB is discharged to low level. On the other hand, if the first node NA is at low level and the second node NB is at high level, the bit line BL is discharged to low level, and the bit line BLB remains at high level.

[0066] As described above, the single-port SRAM cell has the functions of writing data into the SRAM cell, maintaining data, and reading data from the SRAM cell by controlling the bit lines BL and BLB and the word line WL.

[0067] It should be noted that in the following description, in Figure 1 the solid lines extending horizontally and vertically in theFigure 2 In the longitudinal cross-sectional views such as Figure 2 , solid lines extending longitudinally show the grid used for arranging components during design. The grid is arranged at equal intervals in the X direction and at equal intervals in the Y direction. It should be noted that the grid intervals can be the same or different in the X direction and the Y direction. The grid intervals can also be different for each layer. Moreover, each component does not necessarily have to be arranged on the grid. However, from the perspective of suppressing manufacturing deviations, it is preferable to arrange the components on the grid.

[0068] In Figure 1 In the top views such as Figure 1 , the dashed lines representing the unit frames of the single-port SRAM units (the outer edges of the single-port SRAM units) are shown in a way that encloses the units. The unit frames of the single-port SRAM units are arranged in contact with the unit frames of the adjacent units in the X direction or the Y direction.

[0069] In Figure 1 In the top views such as Figure 1 , units obtained by inverting the single-port SRAM unit in the X direction are arranged on both sides of the single-port SRAM unit in the X direction. Units obtained by inverting the single-port SRAM unit in the Y direction are arranged on both sides of the single-port SRAM unit in the Y direction.

[0070] As Figure 1 shown in (b) of Figure 1 , power supply wirings 11 to 13 extending in the Y direction to the upper and lower ends of the drawing of the unit are formed. The power supply wirings 11 to 13 are buried power supply wirings (BPR: Buried Power Rail) formed in the buried wiring layer. The power supply wiring 11 is formed near the center of the drawing of the unit, and the power supply wirings 12 and 13 are formed at the left and right ends of the drawing of the unit, respectively. The power supply wiring 11 supplies the power supply voltage VDD. The power supply wirings 12 and 13 supply the power supply voltage VSS.

[0071] As Figure 1 shown in (b) of Figure 1 , nanosheets 21 to 26 extending in the X direction and the Y direction are formed. The nanosheets 21 to 23 are arranged in the X direction in the order of nanosheets 21 to 23. The nanosheets 24 to 26 are arranged in the X direction in the order of nanosheets 24 to 26. The nanosheets 21 and 24 are arranged in the Y direction. The nanosheets 23 and 26 are arranged in the Y direction.

[0072] The widths of the nanosheets 21, 23, 24, and 26 in the X direction are twice the widths of the nanosheets 22 and 25 in the X direction.

[0073] The nanosheets 21 and 24 are formed at positions close to the unit boundary on the left side of the drawing. The nanosheets 23 and 26 are formed at positions close to the unit boundary on the right side of the drawing.

[0074] The nanosheets 21 to 26 respectively form the channel portions of the access transistors PG2, the load transistor PU1, the drive transistors PD1 and PD2, the load transistor PU2, and the access transistor PG1.

[0075] The gate wirings (Gate) 31 to 36 extend in the X direction and the Z direction. The gate wirings 31 to 33 are arranged in the X direction, and the gate wirings 34 to 36 are arranged in the X direction.

[0076] When viewed from above, the gate wirings 31 to 36 respectively overlap the nanosheets 21 to 26.

[0077] The gate wiring 31 serves as the gate of the access transistor PG2. The gate wiring 32 serves as the gate of the load transistor PU1. The gate wiring 33 serves as the gate of the drive transistor PD1. The gate wiring 34 serves as the gate of the drive transistor PD2. The gate wiring 35 serves as the gate of the load transistor PU2. The gate wiring 36 serves as the gate of the access transistor PG1.

[0078] The gate wirings 32 and 33 are connected to each other via a bridge portion 131 extending in the X direction. The gate wirings 34 and 35 are connected to each other via a bridge portion 132 extending in the X direction.

[0079] At the upper end of the drawing surface of the nanosheet 21, between the nanosheets 21 and 24, the lower end of the drawing surface of the nanosheet 24, the upper end of the drawing surface of the nanosheet 23, between the nanosheets 23 and 26, and the lower end of the drawing surface of the nanosheet 26, pads 40 to 45 doped with an N-type semiconductor are respectively formed. The pads 40 and 41 form the nodes of the access transistor PG2. The pads 41 and 42 form the nodes of the drive transistor PD2. The pads 43 and 44 form the nodes of the drive transistor PD1. The pads 44 and 45 form the nodes of the access transistor PG1.

[0080] That is, the access transistor PG2 is formed by the nanosheet 21, the gate wiring 31, and the pads 40 and 41. The drive transistor PD1 is formed by the nanosheet 23, the gate wiring 33, and the pads 43 and 44. The drive transistor PD2 is formed by the nanosheet 24, the gate wiring 34, and the pads 41 and 42. The access transistor PG1 is formed by the nanosheet 26, the gate wiring 36, and the pads 44 and 45.

[0081] At the upper end of the drawing surface of the nanosheet 22, the lower end of the drawing surface of the nanosheet 22, the upper end of the drawing surface of the nanosheet 25, and the lower end of the drawing surface of the nanosheet 25, pads 46 to 49 doped with a P-type semiconductor are respectively formed. The pads 46 and 47 form the nodes of the load transistor PU1. The pads 48 and 49 form the nodes of the load transistor PU2.

[0082] That is, the load transistor PU1 is composed of the nanosheet 22, the gate wiring 32, and the pads 46 and 47. The load transistor PU2 is composed of the nanosheet 25, the gate wiring 35, and the pads 48 and 49.

[0083] Therefore, the access transistor PG2, the load transistor PU1, and the drive transistor PD1 are arranged in the X direction. The drive transistor PD2, the load transistor PU2, and the access transistor PG1 are arranged in the X direction. In addition, the access transistor PG2 and the drive transistor PD2 are arranged in the Y direction. The drive transistor PD1 and the access transistor PG1 are arranged in the Y direction.

[0084] According to the above arrangement, each transistor is arranged to be point-symmetrical with respect to the center point of the cell. Specifically, the load transistors PU1 and PU2 are arranged to be point-symmetrical with respect to the center point of the cell. The drive transistors PD1 and PD2 are arranged to be point-symmetrical with respect to the center point of the cell. The access transistors PG1 and PG2 are arranged to be point-symmetrical with respect to the center point of the cell.

[0085] Local wirings (LI: Local Interconnect) 51 to 58 extending in the X direction are formed in the local wiring layer. The local wiring 51 is connected to the pad 40. The local wiring 52 is connected to the pad 46. The local wiring 53 is connected to the pad 43. The local wiring 54 is connected to the pads 41 and 48. The local wiring 55 is connected to the pads 47 and 44. The local wiring 56 is connected to the pad 42. The local wiring 57 is connected to the pad 49. The local wiring 58 is connected to the pad 45.

[0086] The local wiring 52 is connected to the power supply wiring 11 via the contact hole (Via) 111. The local wiring 53 is connected to the power supply wiring 13 via the contact hole 112. The local wiring 56 is connected to the power supply wiring 12 via the contact hole 113. The local wiring 57 is connected to the power supply wiring 11 via the contact hole 114.

[0087] The local wiring 54 is connected to the gate wiring 32 via the shared contact hole (Shared-contact) 61. The local wiring 55 is connected to the gate wiring 35 via the shared contact hole 62. It should be noted that the gate wirings 34 and 35, the bridge portion 132, the local wiring 55, and the shared contact hole 62 correspond to the first node NA. The gate wirings 32 and 33, the bridge portion 131, the local wiring 54, and the shared contact hole 61 correspond to the second node NB.

[0088] As Figure 1As shown in (a) of the figure, wirings 71 to 75 extending in the Y direction to the upper and lower ends of the drawing of the cell are formed on the M1 wiring layer. In addition, wirings 76 and 77 extending in the Y direction are formed. Wiring 71 supplies the power supply voltage VDD. Wirings 72 and 73 supply the power supply voltage VSS. Wirings 74 and 75 correspond to bit lines BLB and BL, respectively. In addition, wirings 74 and 75 are arranged symmetrically with respect to the center line in the X direction of the cell.

[0089] Wirings 71 to 75 are arranged in the order of wirings 72, 74, 71, 75, and 73 in the X direction. That is, wiring 71 is provided between wiring 74 and wiring 75.

[0090] Wiring 71 is connected to local wiring 52 via contact hole (Via) 81 and is connected to local wiring 57 via contact hole 82. Wiring 72 is connected to local wiring 56 via contact hole 83. Wiring 73 is connected to local wiring 53 via contact hole 84. Wiring 74 is connected to local wiring 51 via contact hole 85. Wiring 75 is connected to local wiring 58 via contact hole 86. Wiring 76 is connected to gate wiring 31 via contact hole (Gate-contact) 87. Wiring 77 is connected to gate wiring 36 via contact hole 88.

[0091] On the upper layer of the M1 wiring layer, that is, the M2 wiring layer, wirings 91 to 93 extending in the X direction to the left and right ends of the drawing of the cell are formed. Wirings 91 and 93 supply the power supply voltage VSS. Wiring 92 corresponds to the word line WL. Wiring 92 is formed between wiring 91 and wiring 93.

[0092] Wiring 91 is connected to wiring 72 via contact hole 101 and is connected to wiring 73 via contact hole 102. Wiring 92 is connected to wiring 76 via contact hole 103 and is connected to wiring 77 via contact hole 104. Wiring 93 is connected to wiring 72 via contact hole 105 and is connected to wiring 73 via contact hole 106.

[0093] As Figure 2 shown in (b) of the figure and Figure 3 shown in (a) of the figure, nanosheets 21 to 26 are each composed of three sheet-like semiconductors (nanosheets). Among nanosheets 21 to 26, the nanosheets constituting each of nanosheets 21 to 26 are arranged in an overlapping manner in a plan view and are formed separately from each other in the Z direction. That is, the nanosheet FETs provided in the single-port SRAM cell according to the present embodiment each include three nanosheets.

[0094] The outer peripheries of nanosheets 21 to 26 in the X direction and the Z direction are respectively surrounded by gate wirings. Here, a part of the outer peripheries of nanosheets 21 to 26 in the X direction and the Z direction are not covered by the gate wirings and are exposed from the gate wirings.

[0095] Specifically, the right-side surfaces of the nanosheets 21, 22, and 24 in the drawing plane are not covered by the gate wirings 31, 32, and 34, respectively, and are exposed from the gate wirings 31, 32, and 34, respectively. The left-side surfaces of the nanosheets 23, 25, and 26 in the drawing plane are not covered by the gate wirings 33, 35, and 36, respectively, and are exposed from the gate wirings 33, 35, and 36, respectively.

[0096] That is, the surfaces of the nanosheets 22 and 23 on the side facing each other in the X direction are exposed from the gate wirings 32 and 33, respectively. The surfaces of the nanosheets 24 and 25 on the side facing each other in the X direction are exposed from the gate wirings 34 and 35, respectively.

[0097] The left-side surfaces of the nanosheets 21, 22, and 24 in the drawing plane are covered by the gate wirings 31, 32, and 34, respectively, and are not exposed from the gate wirings 31, 32, and 34, respectively. The right-side surfaces of the nanosheets 23, 25, and 26 in the drawing plane are covered by the gate wirings 33, 35, and 36, respectively, and are not exposed from the gate wirings 33, 35, and 36, respectively.

[0098] The nanosheet 22 is formed above the right side of the nanosheet 25 in the drawing plane. That is, the surfaces of the nanosheets 22 and 25 on the side facing each other in the X direction are not exposed from the gate wirings 32 and 35, respectively.

[0099] It should be noted that, as Figure 1 shown, although the nanosheets 22 and 25 are arranged at different positions in the Y direction, they are arranged close to each other in the X direction. Therefore, in this specification, the nanosheets 22 and 25 are said to face each other in the X direction. Therefore, the left-side surface of the nanosheet 22 becomes the surface on the side facing the nanosheet 25. The right-side surface of the nanosheet 25 becomes the surface on the side facing the nanosheet 22. The same applies to the following description.

[0100] The nanosheets 21 and 24 are formed at positions close to the unit boundary on the left side of the drawing plane. The nanosheets 23 and 26 are formed at positions close to the unit boundary on the right side of the drawing plane. On both sides in the left-right direction of the drawing plane of the single-port SRAM cell in Figure 1 are arranged single-port SRAM cells obtained by inverting the single-port SRAM cell along the X direction. That is, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are not exposed from the gate wiring 31. The surfaces of the nanosheets 23 facing each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24 facing each other in the X direction are not exposed from the gate wiring 34. The surfaces of the nanosheets 26 facing each other in the X direction are not exposed from the gate wiring 36.

[0101] In Figure 1In [description], when viewed from above, the power supply wiring 11 is formed between the nanosheets 22 and 25. When viewed from above, the power supply wirings 12 and 13 are formed at the unit boundary on the left side of the drawing plane and the unit boundary on the right side of the drawing plane, respectively.

[0102] As Figure 1 Shown in (a) of [reference], the width of wirings 74 and 75 in the X direction is wider than the width of wirings 76 and 77 in the X direction. Wirings 76 and 77 are the wirings with the smallest width in the X direction in the M1 wiring layer. That is to say, wirings 74 and 75 are formed to have a width in the X direction wider than that of the wiring with the smallest width in the X direction in the M1 wiring layer.

[0103] According to the above configuration, in the load transistor PU1, the pad 46 is connected to the wiring 71 for supplying the power supply voltage VDD, the pad 47 is connected to the local wiring 55 (the first node NA), and the gate wiring 32 is connected to the shared contact hole 61 (the second node NB). In the load transistor PU2, the pad 49 is connected to the wiring 71 for supplying the power supply voltage VDD, the pad 48 is connected to the local wiring 54 (the second node NB), and the gate wiring 35 is connected to the shared contact hole 62 (the first node NA). In the driving transistor PD1, the pad 44 is connected to the local wiring 55 (the first node NA), the pad 43 is connected to the wiring 73 for supplying the power supply voltage VSS, and the gate wiring 33 is connected to the shared contact hole 61 (the second node NB). In the driving transistor PD2, the pad 41 is connected to the local wiring 54 (the second node NB), the pad 42 is connected to the wiring 72 for supplying the power supply voltage VSS, and the gate wiring 34 is connected to the shared contact hole 62 (the first node NA). In the access transistor PG1, the pad 45 is connected to the wiring 75 (bit line BL), the pad 44 is connected to the local wiring 55 (the first node NA), and the gate wiring 36 is connected to the wiring 92 (word line WL). In the access transistor PG2, the pad 40 is connected to the wiring 74 (bit line BLB), the pad 41 is connected to the local wiring 54 (the second node NB), and the gate wiring 31 is connected to the wiring 92 (word line WL).

[0104] The load transistors PU1 and PU2, the drive transistors PD1 and PD2, and the access transistors PG1 and PG2 each include nanosheets 22, 25, 23, 24, 26, 21 extending in the Y direction and gate wirings 32, 35, 33, 34, 36, 31. The nanosheets 21 to 23 are arranged in the order of nanosheets 21 to 23 in the X direction. The nanosheets 24 to 26 are arranged in the order of nanosheets 24 to 26 in the X direction. The gate wirings 31 to 36 respectively surround the outer peripheries of the nanosheets 21 to 26 in the X direction and the Z direction. The right-side surfaces of the nanosheets 21, 22, 24 in the drawing plane are exposed from the gate wirings 31, 32, 34 respectively. The left-side surfaces of the nanosheets 23, 25, 26 in the drawing plane are exposed from the gate wirings 33, 35, 36 respectively. In plan view, the nanosheet 22 is formed above the right side of the nanosheet 25 in the drawing plane. A power supply wiring 11 is formed in the embedded wiring layer. The power supply wiring 11 extends in the Y direction, is disposed between the nanosheet 21 and the nanosheet 25 in plan view, and supplies a power supply voltage VDD.

[0105] That is to say, the load transistors PU1 and PU2, the drive transistors PD1 and PD2, and the access transistors PG1 and PG2 are each composed of cross-sheet transistors. In this way, a single-port SRAM cell using cross-sheet transistors is realized.

[0106] The surfaces of the nanosheets 22 and 23 facing each other in the X direction are exposed from the gate wirings 32 and 33 respectively. The surfaces of the nanosheets 24 and 25 facing each other in the X direction are exposed from the gate wirings 34 and 35 respectively. In this way, the distance d1 in the X direction between the load transistor PU1 and the drive transistor PD1 and the distance d1 in the X direction between the drive transistor PD2 and the load transistor PU2 can be reduced. Therefore, miniaturization of the semiconductor memory device can be achieved.

[0107] By forming the power supply wiring 11 in the embedded wiring layer, in the M1 wiring layer, the width of the wiring 71 for supplying the power supply voltage VDD in the X direction can be reduced. Therefore, the widths of the wirings 75 and 74 that become the bit lines BL and BLB respectively can be expanded in the X direction. In this way, high-speed operation of the semiconductor memory device and improvement of the write characteristics can be achieved.

[0108] In a plan view, the power supply wiring 11 is formed between the nanosheets 22 and 25. In addition, the surfaces of the nanosheets 22 and 25 on the side facing each other in the X direction are not exposed from the gate wirings 32 and 35, respectively. Therefore, in a plan view, the power supply wiring 11 is formed between the load transistors PU1 and PU2, and the distance in the X direction between the load transistors PU1 and PU2 is larger than the distance d1. That is, the power supply wiring 11 can be easily formed without expanding the pitch in the X direction between the load transistors PU1 and PU2. In this way, an increase in the area of the semiconductor memory device can be suppressed.

[0109] Therefore, in a semiconductor memory device including a single-port SRAM cell using a cross-sheet transistor, an increase in area can be suppressed, and at the same time, high speed and improvement in write characteristics can be achieved.

[0110] By forming the power supply wirings 12 and 13 for supplying the power supply voltage VSS in the buried wiring layer, in the M1 wiring layer, the widths of the wirings 72 and 73 for supplying the power supply voltage VSS in the X direction can be reduced, and therefore the widths of the wirings 75 and 74 that become the bit lines BL and BLB, respectively, in the X direction can be expanded. In this way, high speed and improvement in write characteristics of the semiconductor memory device can be achieved.

[0111] In a top view, power supply wirings 12 and 13 are respectively formed at the cell boundaries on the left side of the drawing plane and at the cell boundaries on the right side of the drawing plane. In addition, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction do not protrude from the gate wiring 31. The surfaces of the nanosheets 23 facing each other in the X direction do not protrude from the gate wiring 33. The surfaces of the nanosheets 24 facing each other in the X direction do not protrude from the gate wiring 34. The surfaces of the nanosheets 26 facing each other in the X direction do not protrude from the gate wiring 36. Therefore, in a top view, the power supply wiring 12 is formed between the driving transistors PD2 and between the access transistors PG2, and the distance in the X direction between the driving transistors PD2 and between the access transistors PG2 is larger than the distance d1. In a top view, the power supply wiring 13 is formed between the driving transistors PD1 and between the access transistors PG1, and the distance in the X direction between the driving transistors PD1 and between the access transistors PG1 is larger than the distance d1. That is, the power supply wiring 12 can be easily formed without increasing the pitch in the X direction between the access transistors PG2 and between the driving transistors PD2. The power supply wiring 13 can be easily formed without increasing the pitch in the X direction between the driving transistors PD1 and between the access transistors PG1. In this way, an increase in the area of the semiconductor memory device can be suppressed.

[0112] Therefore, in a semiconductor memory device including single-port SRAM cells using cross-sheet transistors, an increase in area can be suppressed, and at the same time, high speed operation and improvement in write characteristics can be achieved.

[0113] On the M1 wiring layer, a wiring 71 for supplying the power supply voltage VDD and wirings 72 and 73 for supplying the power supply voltage VSS are formed. That is, wirings for supplying the power supply voltages VDD and VSS are formed on the M1 wiring layer and the buried wiring layer, respectively. In this way, the width in the X direction of the wirings for supplying the power supply voltages VDD and VSS on the M1 wiring layer can be reduced, and at the same time, the resistance value of the wirings for supplying the power supply voltages VDD and VSS on the buried wiring layer can be reduced. Therefore, an increase in the area of the semiconductor memory device can be suppressed, and at the same time, high speed operation of the semiconductor memory device can be achieved.

[0114] On the M2 wiring layer, wirings 91 and 93 for supplying the power supply voltage VSS are formed. A wiring 92 (word line WL) is formed between the wiring 91 and the wiring 93. In Figure 1On both sides in the vertical direction of the drawing of the single-port SRAM cell, single-port SRAM cells obtained by inverting the single-port SRAM cell in the Y direction are arranged. That is, in the single-port SRAM cells arranged in the Y direction, wirings 91 or 93 are formed between the wirings 92. In this way, the power supply to the single-port SRAM cell can be strengthened, and at the same time, the crosstalk between word lines can be prevented by the shielding effect of the wirings 91 and 93.

[0115] The widths of the wirings 74 and 75 in the X direction are wider than the widths of the wirings 76 and 77 in the X direction. The wirings 76 and 77 are the wirings with the smallest width in the X direction in the M1 wiring layer. That is, the wirings 74 and 75 are formed to have a width in the X direction wider than that of the wiring with the smallest width in the X direction in the M1 wiring layer. In this way, in the semiconductor memory device, the high-speed writing and reading via the wirings 74 and 75 can be realized.

[0116] The load transistors PU1 and PU2 are arranged point-symmetrically with respect to the center point of the cell. The drive transistors PD1 and PD2 are arranged point-symmetrically with respect to the center point of the cell. The access transistors PG1 and PG2 are arranged point-symmetrically with respect to the center point of the cell. In this way, the characteristics between the bit lines BL and BLB are consistent, and the operating stability and operating speed of the semiconductor memory device are improved.

[0117] In the M1 wiring layer, the wirings 75 and 74 are arranged symmetrically with respect to the central line of the cell in the X direction. That is, the wirings corresponding to the bit lines BL and BLB are arranged symmetrically with respect to the central line of the cell in the X direction. In this way, the characteristics between the bit lines BL and BLB are consistent, and the operating stability and operating speed of the semiconductor memory device are improved.

[0118] It should be noted that the widths of the nanosheets 21, 23, 24, and 26 in the X direction are twice the widths of the nanosheets 22 and 25 in the X direction, but this is not limited thereto. The widths of the nanosheets 21 to 26 in the X direction (i.e., the gate widths of the respective transistors) can be determined as long as the operating stability of the single-port SRAM circuit is considered.

[0119] Some of the wirings 71 to 73 can be omitted, and at least one of these wirings is sufficient. In this way, the widths of the wirings 74 and 75 in the X direction can be enlarged, and thus the high-speed operation and the improvement of the writing characteristics of the semiconductor memory device can be realized.

[0120] Some of the power supply wirings 11 to 13 can be omitted, and at least one of these power supply wirings is sufficient.

[0121] (Variant Example 1)

[0122] Figure 5It is a top view showing another example of the layout structure of the single-port SRAM cell according to the first embodiment. Figure 5 It is a top view showing another example of the layout structure of the single-port SRAM cell according to the first embodiment. Specifically, Figure 5 (a) of shows the upper part of the cell, Figure 5 (b) of shows the lower part of the cell. Figure 6 (a) of shows a cross-section taken along line X6-X6', Figure 6 (b) of shows a cross-section taken along line X7-X7'. In Figure 5 , the surfaces of the respective nanosheets on the side opposite to that in in the X direction are exposed from the gate wiring. In addition, the power supply wiring 11 is omitted, and the arrangements of the power supply wirings 12 and 13 are different from those in Figure 1 . Figure 1

[0123] As Figure 5 shown in (b) of, when viewed from above, the gate wiring 33 overlaps with the nanosheets 22 and 23. When viewed from above, the gate wiring 34 overlaps with the nanosheets 24 and 25.

[0124] In Figure 5 , the gate wiring 33 serves as the gate of the load transistor PU1 and the drive transistor PD1. The gate wiring 34 serves as the gate of the drive transistor PD2 and the load transistor PU2.

[0125] The gate wiring 31 is connected to the gate wiring 31 of the single-port SRAM cell arranged on the left side of the drawing of this single-port SRAM cell via the bridge portion 133. The gate wiring 36 is connected to the gate wiring 36 of the single-port SRAM cell arranged on the right side of the drawing of this single-port SRAM cell via the bridge portion 134.

[0126] The wiring 76 is connected to the gate wiring 31 via the contact hole 87 and the bridge portion 133. The wiring 77 is connected to the gate wiring 36 via the contact hole 88 and the bridge portion 134.

[0127] Here, as Figure 6 shown in (a) of, Figure 6 shown in (b) of, the left-side surfaces of the nanosheets 21, 22, and 24 are not covered by the gate wirings 31, 33, and 34, respectively, and are exposed from the gate wirings 31, 33, and 34, respectively. The right-side surfaces of the nanosheets 23, 25, and 26 are not covered by the gate wirings 33, 34, and 36, respectively, and are exposed from the gate wirings 33, 34, and 36, respectively.

[0128] The nanosheets 21 and 24 are arranged at positions close to the cell boundary on the left side of the drawing. The nanosheets 23 and 26 are arranged at positions close to the cell boundary on the right side of the drawing. In Figure 5On both sides in the left - right direction of the drawing of the single - port SRAM cell, single - port SRAM cells obtained by inverting the single - port SRAM cell in the X - direction are arranged. That is, in the single - port SRAM cells arranged in the X - direction, the surfaces of the nanosheets 21 facing each other in the X - direction are exposed from the gate wiring 31. The surfaces of the nanosheets 23 facing each other in the X - direction are exposed from the gate wiring 33. The surfaces of the nanosheets 24 facing each other in the X - direction are exposed from the gate wiring 34. The surfaces of the nanosheets 26 facing each other in the X - direction are exposed from the gate wiring 36.

[0129] The nanosheet 22 is formed above the right side of the drawing of the nanosheet 25. That is, the surfaces of the nanosheets 22 and 25 facing each other in the X - direction are exposed from the gate wiring 33 and 34 respectively.

[0130] The right - hand side surfaces of the nanosheets 21, 22, and 24 in the drawing are covered by the gate wirings 31, 33, and 34 respectively and are not exposed from the gate wirings 31, 33, and 34. The left - hand side surfaces of the nanosheets 23, 25, and 26 in the drawing are covered by the gate wirings 33, 34, and 36 respectively and are not exposed from the gate wirings 33, 34, and 36.

[0131] That is, the surfaces of the nanosheets 22 and 23 facing each other in the X - direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24 and 25 facing each other in the X - direction are not exposed from the gate wiring 34.

[0132] In Figure 5 when viewed from above, the power supply wiring 12 is formed between the nanosheets 24 and 25. When viewed from above, the power supply wiring 13 is formed between the nanosheets 22 and 23.

[0133] According to Figure 5 the layout structure, in the single - port SRAM cells arranged in the X - direction, the surfaces of the nanosheets 21 facing each other in the X - direction are exposed from the gate wiring 31. The surfaces of the nanosheets 23 facing each other in the X - direction are exposed from the gate wiring 33. The surfaces of the nanosheets 24 facing each other in the X - direction are exposed from the gate wiring 34. The surfaces of the nanosheets 26 facing each other in the X - direction are exposed from the gate wiring 36. In this way, the distances d1 in the X - direction between the access transistors PG2, between the drive transistors PD1, between the drive transistors PD2, and between the access transistors PG1 can be reduced respectively. Therefore, miniaturization of the semiconductor memory device can be achieved.

[0134] The surfaces of the nanosheets 22 and 25 on the sides facing each other in the X direction are respectively exposed from the gate wirings 33 and 34. In this way, the distance d1 in the X direction between the load transistor PU1 and the load transistor PU2 can be reduced, and thus miniaturization of the semiconductor memory device can be achieved.

[0135] Power supply wirings 12 and 13 for supplying the power supply voltage VSS are formed in the buried wiring layer. In a plan view, the power supply wiring 12 is formed between the nanosheets 24 and 25. In a plan view, the power supply wiring 13 is formed between the nanosheets 22 and 23. In addition, the surfaces of the nanosheets 22 and 23 on the sides facing each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24 and 25 on the sides facing each other in the X direction are not exposed from the gate wiring 34. Therefore, the power supply wiring 12 is formed between the load transistor PU2 and the drive transistor PD2, and the distance in the X direction between the load transistor PU2 and the drive transistor PD2 is larger than the distance d1. The power supply wiring 13 is formed between the load transistor PU1 and the drive transistor PD1, and the distance in the X direction between the load transistor PU1 and the drive transistor PD1 is larger than the distance d1. That is, the power supply wiring 12 can be easily formed without expanding the pitch in the X direction between the load transistor PU2 and the drive transistor PD2. The power supply wiring 13 can be easily formed without expanding the pitch in the X direction between the load transistor PU1 and the drive transistor PD1. In this way, an increase in the area of the semiconductor memory device can be suppressed, and at the same time, high-speed operation of the semiconductor memory device can be achieved.

[0136] The same effect can also be obtained in other aspects. Figure 1 The same effect.

[0137] It should be noted that a power supply wiring for supplying the power supply voltage VDD may be formed instead of any one or both of the power supply wirings 12 and 13. In this case, the power supply wiring is connected to any one or both of the pads 46 and 49 via a local wiring and a contact hole.

[0138] In addition, only one of the power supply wirings 12 and 13 is sufficient.

[0139] (Modification Example 2)

[0140] Figure 7 It is a plan view showing another example of the layout structure of the single-port SRAM cell according to the first embodiment. Specifically, Figure 7 (a) shows the upper part of the cell, Figure 7 (b) shows the lower part of the cell. In Figure 7 , compared with Figure 1In contrast, the length of a part of the local wiring in the X direction becomes shorter, and the width of the shared contact hole in the X direction becomes smaller.

[0141] For example, in Figure 1 (b) of, the local wiring 51 is formed such that the left end of the drawing of the local wiring 51 is aligned with the left end of the drawing of the pad 40. In contrast, in Figure 7 (b) of, the local wiring 51 is formed such that the left end of the drawing of the local wiring 51 is near the center in the X direction of the pad 40. Therefore, compared with Figure 1 (b) of, in Figure 7 (b) of, the length of the local wiring 51 in the X direction becomes shorter. Similarly, other local wirings are also formed such that at least one of the two ends in the drawing is near the center of the drawing of the pad, that is, between the left end and the right end of the drawing of the pad. Therefore, compared with Figure 1 (b) of, in Figure 7 (b) of, the length of a part of the local wiring in the X direction becomes shorter.

[0142] In Figure 1 (b) of, the shared contact hole 61 is formed such that its left end and right end in the drawing are aligned with the left end and right end of the drawing of the pad 48. The shared contact hole 62 is formed such that its left end and right end in the drawing are aligned with the left end and right end of the drawing of the pad 47. In contrast, in Figure 7 (b) of, the shared contact hole 61 is formed such that its left end in the drawing is at a position on the right side of the drawing compared to the left end of the drawing of the pad 47; its right end in the drawing is at a position on the left side of the drawing compared to the right end of the drawing of the pad 47. The shared contact hole 62 is formed such that its left end in the drawing is at a position on the right side of the drawing compared to the left end of the drawing of the pad 48; its right end in the drawing is at a position on the left side of the drawing compared to the right end of the drawing of the pad 47. Therefore, compared with Figure 1 (b) of, in Figure 7 (b) of, the width of the shared contact holes 61 and 62 in the X direction becomes shorter.

[0143] According to the layout structure of Figure 7 , compared with Figure 1 , the length of a part of the local wiring (such as the local wiring 51, etc.) in the X direction becomes shorter. In addition, compared with Figure 1 , the width of the shared contact holes 61 and 62 in the X direction becomes shorter. In this way, the parasitic capacitance in the semiconductor integrated circuit can be reduced, and thus the high-speed operation of the semiconductor memory device can be achieved.

[0144] The same effect can also be obtained in other aspects as Figure 1 .

[0145] (Second Embodiment)

[0146] Figure 8 1 is a top view showing an example of the layout structure of a single-port SRAM cell according to the second embodiment. Figure 8 (a) shows the upper part of the unit, Figure 8 (b) shows the lower part of the unit. Figure 8 In the single-port SRAM cell, load transistors PU1, PU2 and transistors PD11, PD12, PD21, PD22, PG11, PG12, PG21, PG22 are formed. Figure 4 The single-port SRAM circuit shown in Figure 1 is Figure 8 In the embodiment, the driving transistors PD1 and PD2 and the access transistors PG1 and PG2 are respectively formed by two transistors. Specifically, the driving transistor PD1 is formed by transistors PD11 and PD12. The driving transistor PD2 is formed by transistors PD21 and PD22. The access transistor PG1 is formed by transistors PG11 and PG12. The access transistor PG2 is formed by transistors PG21 and PG22. Figure 8 On the left and right sides of the drawing of the single-port SRAM cell, there are arranged single-port SRAM cells which are obtained by inverting the single-port SRAM cell along the X direction.

[0147] like Figure 8 As shown in (b) of FIG. 1 , power supply wirings 11 to 13 are formed in the buried wiring layer.

[0148] Nanosheets 21a, 21b, 22, 23a, 23b, 24a, 24b, 25, 26a, 26b are also formed to extend in the X direction and the Y direction. Nanosheets 21a, 21b, 22, 23a, 23b are arranged in the order of nanosheets 21a, 21b, 22, 23a, 23b in the X direction. Nanosheets 24a, 24b, 25, 26a, 26b are arranged in the order of nanosheets 24a, 24b, 25, 26a, 26b. Nanosheets 21a and 24a are arranged in the Y direction. Nanosheets 21b and 24b are arranged in the Y direction. Nanosheets 23a and 26a are arranged in the Y direction. Nanosheets 23b and 26b are arranged in the Y direction.

[0149] The nanosheets 21a, 21b, 22, 23a, 23b, 24a, 24b, 25, 26a, and 26b all have the same width in the X direction.

[0150] exist Figure 8 In the figure, the nanosheets 21a, 21b, 23a, 23b, 24a, 24b, 26a, and 26b become channel portions of the transistors PG21, PG22, PD11, PD12, PD21, PD22, PG11, and PG12, respectively.

[0151] When viewed from above, the gate wiring 31 overlaps with the nanosheets 21a and 21b. When viewed from above, the gate wiring 32 overlaps with the nanosheet 22. When viewed from above, the gate wiring 33 overlaps with the nanosheets 23a and 23b. When viewed from above, the gate wiring 34 overlaps with the nanosheets 24a and 24b. When viewed from above, the gate wiring 35 overlaps with the nanosheet 25. When viewed from above, the gate wiring 36 overlaps with the nanosheets 26a and 26b.

[0152] In Figure 8 , the gate wiring 31 becomes the gate of the transistors PG21 and PG22. The gate wiring 32 becomes the gate of the load transistor PU1. The gate wiring 33 becomes the gate of the transistors PD11 and PD12. The gate wiring 34 becomes the gate of the transistors PD21 and PD22. The gate wiring 35 becomes the gate of the load transistor PU2. The gate wiring 36 becomes the gate of the transistors PG11 and PG12.

[0153] The gate wiring 31 is connected via the bridge portion 133 to the gate wiring 31 of the single-port SRAM cell arranged on the left side of the drawing of this single-port SRAM cell. The gate wirings 32 and 33 are connected to each other via the bridge portion 131. The gate wirings 34 and 35 are connected to each other via the bridge portion 132. The gate wiring 36 is connected via the bridge portion 134 to the gate wiring 36 of the single-port SRAM cell arranged on the right side of the drawing of this single-port SRAM cell.

[0154] On the upper side of the drawing surface of the nanosheet 21a, between the nanosheets 21a and 24a, on the lower side of the drawing surface of the nanosheet 24a, on the upper side of the drawing surface of the nanosheet 21b, between the nanosheets 21b and 24b, on the lower side of the drawing surface of the nanosheet 24b, on the upper side of the drawing surface of the nanosheet 23a, between the nanosheets 23a and 26a, on the lower side of the drawing surface of the nanosheet 26a, on the upper side of the drawing surface of the nanosheet 23b, between the nanosheets 23b and 26b, and on the lower side of the drawing surface of the nanosheet 26b, pads 40a, 41a, 42a, 40b, 41b, 42b, 43a, 44a, 45a, 43b, 44b, and 45b doped with an N-type semiconductor are respectively formed. The pads 40a and 41a constitute the nodes of the transistor PG21. The pads 41a and 42a constitute the nodes of the transistor PD21. The pads 40b and 41b constitute the nodes of the transistor PG22. The pads 41b and 42b constitute the nodes of the transistor PD22. The pads 43a and 44a constitute the nodes of the transistor PD11. The pads 44a and 45a constitute the nodes of the transistor PG11. The pads 43b and 44b constitute the nodes of the transistor PD12. The pads 44b and 45b constitute the nodes of the transistor PG12.

[0155] According to the above arrangement, in Figure 8In (b) thereof, each transistor is arranged to be point-symmetrical with respect to the center point of the cell. Specifically, the load transistors PU1 and PU2 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PD11 and PD22 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PD12 and PD21 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PG11 and PG22 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PG12 and PG21 are arranged to be point-symmetrical with respect to the center point of the cell.

[0156] The local wiring 51 is connected to the pads 40a and 40b. The local wiring 53 is connected to the pads 43a and 43b. The local wiring 54 is connected to the pads 41a, 41b, and 48. The local wiring 55 is connected to the pads 47, 44a, and 44b. The local wiring 56 is connected to the pads 42a and 42b. The local wiring 58 is connected to the pads 45a and 45b.

[0157] With Figure 7 being the same, a part of the local wirings 51 to 58 is formed such that at least one of the two ends in the drawing plane is located between the left end and the right end in the drawing plane of the connected pad. For example, the left end in the drawing plane of the local wiring 51 is located between the left end and the right end in the drawing plane of the pad 40a.

[0158] With Figure 7 being the same, the shared contact hole 61 is formed such that its left end in the drawing plane is located at a position on the right side in the drawing plane compared to the left end in the drawing plane of the pad 48; its right end in the drawing plane is located at a position on the left side in the drawing plane compared to the right end in the drawing plane of the pad 48. With Figure 7 being the same, the shared contact hole 62 is formed such that its left end in the drawing plane is located at a position on the right side in the drawing plane compared to the left end in the drawing plane of the pad 47; its right end in the drawing plane is located at a position on the left side in the drawing plane compared to the right end in the drawing plane of the pad 47.

[0159] Here, the left-side surfaces in the drawing plane of the nanosheets 21a, 23a, 24a, 25, and 26a are not covered by the gate wirings 31, 33, 34, 35, and 36, respectively, and are exposed from the gate wirings 31, 33, 34, 35, and 36, respectively. The right-side surfaces in the drawing plane of the nanosheets 21b, 22, 23b, 24b, and 26b are not covered by the gate wirings 31, 32, 33, 34, and 36, respectively, and are exposed from the gate wirings 31, 32, 33, 34, and 36, respectively.

[0160] That is to say, the surfaces on the sides facing each other in the X direction of the nanosheets 22 and 23a are exposed from the gate wirings 32 and 33, respectively. The surfaces on the sides facing each other in the X direction of the nanosheets 24b and 25 are exposed from the gate wirings 34 and 35, respectively.

[0161] The nanosheets 21a and 24a are formed at positions close to the cell boundary on the left side of the drawing plane. The nanosheets 23b and 26b are formed at positions close to the cell boundary on the right side of the drawing plane. At Figure 8 On the right side of the drawing plane of the single-port SRAM cell, a single-port SRAM cell obtained by inverting the single-port SRAM cell in the X direction is arranged. That is, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21a on the sides facing each other in the X direction are exposed from the gate wiring 31. The surfaces of the nanosheets 23b on the sides facing each other in the X direction are exposed from the gate wiring 33. The surfaces of the nanosheets 24a on the sides facing each other in the X direction are exposed from the gate wiring 34. The surfaces of the nanosheets 26b on the sides facing each other in the X direction are exposed from the gate wiring 36.

[0162] The right-side surfaces of the nanosheets 21a, 23a, 24a, 25, and 26a are respectively covered by the gate wirings 31, 33, 34, 35, and 36 and are not exposed from the gate wirings 31, 33, 34, 35, and 36, respectively. The left-side surfaces of the nanosheets 21b, 22, 23b, 24b, and 26b are respectively covered by the gate wirings 31, 32, 33, 34, and 36 and are not exposed from the gate wirings 31, 32, 33, 34, and 36, respectively.

[0163] That is, the surfaces of the nanosheets 21a and 21b on the sides facing each other in the X direction are not exposed from the gate wiring 31. The surfaces of the nanosheets 23a and 23b on the sides facing each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24a and 24b on the sides facing each other in the X direction are not exposed from the gate wiring 34. The surfaces of the nanosheets 26a and 26b on the sides facing each other in the X direction are not exposed from the gate wiring 36.

[0164] The nanosheet 22 is formed above the right side of the drawing plane of the nanosheet 25. That is, the surfaces of the nanosheets 22 and 25 on the sides facing each other in the X direction are not exposed from the gate wirings 32 and 35, respectively.

[0165] At Figure 8 In

[0166] When viewed from above, the power supply wiring 11 is formed between the nanosheets 22 and 25. When viewed from above, the power supply wiring 12 is formed between the nanosheets 21a and 21b and between the nanosheets 24a and 24b. When viewed from above, the power supply wiring 13 is formed between the nanosheets 23a and 23b and between the nanosheets 26a and 26b.With the above configuration, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are exposed from the gate wiring 31. The surfaces of the nanosheets 23b facing each other in the X direction are exposed from the gate wiring 33. The surfaces of the nanosheets 24a facing each other in the X direction are exposed from the gate wiring 34. The surfaces of the nanosheets 26b facing each other in the X direction are exposed from the gate wiring 36. In this way, the distances d1 in the X direction between the transistors PG21, between the transistors PD12, between the transistors PD21, and between the transistors PG12 can be reduced respectively, so that miniaturization of the semiconductor memory device can be achieved.

[0167] Since the power supply wiring 11 for supplying the power supply voltage VDD and the power supply wirings 12 and 13 for supplying the power supply voltage VSS are formed in the embedded wiring layer, the widths in the X direction of the wiring 71 for supplying the power supply voltage VDD and the widths in the X direction of the wirings 72 and 73 for supplying the power supply voltage VSS can be reduced respectively in the M1 wiring layer. Therefore, the widths in the X direction of the wirings 75 and 74 that become the bit lines BL and BLB can be expanded respectively. In this way, high-speed operation of the semiconductor memory device and improvement of the write characteristics can be achieved.

[0168] In a plan view, the power supply wiring 12 is formed between the nanosheets 21a and 21b and between the nanosheets 24a and 24b. In a plan view, the power supply wiring 13 is formed between the nanosheets 23a and 23b and between the nanosheets 26a and 26b. In addition, the surfaces of the nanosheets 21a and 21b on the side facing each other in the X direction are not exposed from the gate wiring 31. The surfaces of the nanosheets 23a and 23b on the side facing each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24a and 24b on the side facing each other in the X direction are not exposed from the gate wiring 34. The surfaces of the nanosheets 26a and 26b on the side facing each other in the X direction are not exposed from the gate wiring 36. Therefore, in a plan view, the power supply wiring 12 is formed between the transistors PG21 and PG22 and between the transistors PD21 and PD22, and the distance in the X direction between the transistors PG21 and PG22 and between the transistors PD21 and PD22 is larger than the distance d1. In a plan view, the power supply wiring 13 is formed between the transistors PD11 and PD12 and between the transistors PG11 and PG12, and the distance in the X direction between the transistors PD11 and PD12 and between the transistors PG11 and PG12 is larger than the distance d1. That is, the power supply wiring 12 can be easily formed without increasing the pitch in the X direction between the transistors PG21 and PG22 and the pitch in the X direction between the transistors PD21 and PD22. The power supply wiring 13 can be easily formed without increasing the pitch in the X direction between the transistors PD11 and PD12 and the pitch in the X direction between the transistors PG11 and PG12. In this way, an increase in the area of the semiconductor memory device can be suppressed.

[0169] Therefore, in a semiconductor memory device including a single-port SRAM cell using a cross-sheet transistor, an increase in area can be suppressed, and at the same time, high speed and improvement in write characteristics can be achieved.

[0170] The widths of the nanosheets 21a, 21b, 22, 23a, 23b, 24a, 24b, 25, 26a, and 26b in the X direction are all the same. In this way, the shape of the nanosheets of the semiconductor memory device can be made uniform, thereby improving the ease of manufacturing.

[0171] It should be noted that at least any one of the wirings 71 to 73 is sufficient. In this way, the widths of the wirings 74 and 75 in the X direction can be increased, and therefore, high speed and improvement in write characteristics of the semiconductor memory device can be achieved.

[0172] In addition, at least any one of the power supply wirings 11 to 13 is sufficient.

[0173] (Modified Example)

[0174] Figure 9 It is a top view showing another example of the layout structure of the single-port SRAM cell according to the second embodiment. Specifically, Figure 9 (a) of shows the upper part of the cell, Figure 9 (b) of shows the lower part of the cell. In Figure 9 , the surfaces of the respective nanosheets on the side opposite to that in the X direction in Figure 8 are exposed from the gate wiring. In addition, the arrangement of the power supply wiring formed in the embedded wiring layer is different.

[0175] Power supply wirings 11 to 14 extending in the Y direction are formed in the embedded wiring layer. The power supply wirings 11 and 14 supply the power supply voltage VDD. The power supply wirings 12 and 13 supply the power supply voltage VSS.

[0176] As shown in Figure 9 (b) of, gate wirings 31a, 31b, 32, 33a, 33b, 34a, 34b, 35, 36a, and 36b extending in the X and Z directions are formed. When viewed from above, the gate wiring 31a overlaps with the nanosheet 21a. When viewed from above, the gate wiring 31b overlaps with the nanosheet 21b. When viewed from above, the gate wiring 33a overlaps with the nanosheets 22 and 23a. When viewed from above, the gate wiring 33b overlaps with the nanosheet 23b. When viewed from above, the gate wiring 34a overlaps with the nanosheet 24a. When viewed from above, the gate wiring 34b overlaps with the nanosheets 24b and 25. When viewed from above, the gate wiring 36a overlaps with the nanosheet 26a. When viewed from above, the gate wiring 36b overlaps with the nanosheet 26b.

[0177] In Figure 9 , the gate wiring 31a becomes the gate of the transistor PG21. The gate wiring 31b becomes the gate of the transistor PG22. The gate wiring 33a becomes the gates of the load transistor PU1 and the transistor PD11. The gate wiring 33b becomes the gate of the transistor PD12. The gate wiring 34a becomes the gate of the transistor PD21. The gate wiring 34b becomes the gates of the transistor PD22 and the load transistor PU2. The gate wiring 36a becomes the gate of the transistor PG11. The gate wiring 36b becomes the gate of the transistor PG12.

[0178] The gate wirings 31a and 31b are connected to each other via the bridge portion 135. The gate wirings 32 and 33a are connected to each other via the bridge portion 131. The gate wirings 33a and 33b are connected to each other via the bridge portion 136. The gate wirings 34a and 34b are connected to each other via the bridge portion 137. The gate wirings 34b and 35 are connected to each other via the bridge portion 132. The gate wirings 36a and 36b are connected to each other via the bridge portion 138.

[0179] The local wiring 52 is connected to the power supply wiring 14 via the contact hole 115. The local wiring 57 is connected to the power supply wiring 11 via the contact hole 114.

[0180] The wiring 76 is connected to the gate wiring 31a via the contact hole 87. The wiring 77 is connected to the gate wiring 36b via the contact hole 88.

[0181] In Figure 9 the right-side surfaces of the nanosheets 21a, 23a, 24a, 25, and 26a in the drawing plane are not covered by the gate wirings 31a, 33a, 34a, 34b, and 36a, respectively, and are exposed from the gate wirings 31a, 33a, 34a, 34b, and 36a, respectively. The left-side surfaces of the nanosheets 21b, 22, 23b, 24b, and 26b in the drawing plane are not covered by the gate wirings 31b, 33a, 33b, 34b, and 36b, respectively, and are exposed from the gate wirings 31b, 33a, 33b, 34b, and 36b, respectively.

[0182] That is to say, the surfaces of the nanosheets 21a and 21b on the sides facing each other in the X direction are exposed from the gate wirings 31a and 31b, respectively. The surfaces of the nanosheets 23a and 23b on the sides facing each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of the nanosheets 24a and 24b on the sides facing each other in the X direction are exposed from the gate wirings 34a and 34b, respectively. The surfaces of the nanosheets 26a and 26b on the sides facing each other in the X direction are exposed from the gate wirings 36a and 36b, respectively.

[0183] The nanosheet 22 is formed above the right side of the nanosheet 25 in the drawing plane. That is to say, the surfaces of the nanosheets 22 and 25 on the sides facing each other in the X direction are exposed from the gate wirings 33a and 34b, respectively.

[0184] Here, the left-side surfaces of the nanosheets 21a, 23a, 24a, 25, and 26a in the drawing plane are covered by the gate wirings 31a, 33a, 34a, 34b, and 36a, respectively, and are not exposed from the gate wirings 31a, 33a, 34a, 34b, and 36a, respectively. The right-side surfaces of the nanosheets 21b, 22, 23b, 24b, and 26b in the drawing plane are covered by the gate wirings 31b, 33a, 33b, 34b, and 36b, respectively, and are not exposed from the gate wirings 31b, 33a, 33b, 34b, and 36b, respectively.

[0185] That is to say, the surfaces of the nanosheets 22 and 23a on the sides facing each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 24b and 25 on the sides facing each other in the X direction are not exposed from the gate wiring 34b.

[0186] The nanosheets 21a and 24a are arranged at positions close to the cell boundary on the left side of the drawing. The nanosheets 23b and 26b are arranged at positions close to the cell boundary on the right side of the drawing. On both sides of the drawing of the single-port SRAM cell in the left-right direction of the drawing, single-port SRAM cells obtained by inverting the single-port SRAM cell in the X direction are arranged. That is, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 23b facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 26b facing each other in the X direction are not exposed from the gate wiring 36b. Figure 9 In the single-port SRAM cell, single-port SRAM cells obtained by inverting the single-port SRAM cell in the X direction are arranged on both sides in the left-right direction of the drawing. That is, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 23b facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 26b facing each other in the X direction are not exposed from the gate wiring 36b.

[0187] In Figure 9 , in a plan view, the power supply wiring 11 is formed between the nanosheet 24b and the nanosheet 25. In a plan view, the power supply wiring 12 is formed at the cell boundary on the left side of the drawing. In a plan view, the power supply wiring 13 is formed at the cell boundary on the right side of the drawing. In a plan view, the power supply wiring 14 is formed between the nanosheet 22 and the nanosheet 23a.

[0188] According to Figure 9 's layout structure, the surfaces of the nanosheets 21a and 21b facing each other in the X direction are respectively exposed from the gate wirings 31a and 31b. The surfaces of the nanosheets 23a and 23b facing each other in the X direction are respectively exposed from the gate wirings 33a and 33b. The surfaces of the nanosheets 24a and 24b facing each other in the X direction are respectively exposed from the gate wirings 34a and 34b. The surfaces of the nanosheets 26a and 26b facing each other in the X direction are respectively exposed from the gate wirings 36a and 36b. In this way, the distances d1 in the X direction between the transistor PG21 and the transistor PG22, the distances d1 in the X direction between the transistor PD11 and the transistor PD12, the distances d1 in the X direction between the transistor PD21 and the transistor PD22, and the distances d1 in the X direction between the transistor PG11 and the transistor PG12 can be respectively reduced. Therefore, miniaturization of the semiconductor memory device can be achieved.

[0189] Power wirings 11 and 14 for supplying a power supply voltage VDD are formed in the embedded wiring layer. In a plan view, the power wiring 11 is formed between the nanosheets 24b and 25. In a plan view, the power wiring 14 is formed between the nanosheets 22 and 23a. In addition, the surfaces of the nanosheets 22 and 23a on the side facing each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 24b and 25 on the side facing each other are not exposed from the gate wiring 34b. Therefore, in a plan view, the power wiring 11 is formed between the transistor PD22 and the load transistor PU2, and the distance in the X direction between the transistor PD22 and the load transistor PU2 is larger than the distance d1. In a plan view, the power wiring 14 is formed between the load transistor PU1 and the transistor PD11, and the distance in the X direction between the load transistor PU1 and the transistor PD11 is larger than the distance d1. That is, the power wiring 11 can be easily formed without expanding the pitch in the X direction between the transistor PD22 and the load transistor PU2. The power wiring 14 can be easily formed without expanding the pitch in the X direction between the load transistor PU1 and the transistor PD11. In this way, an increase in the area of the semiconductor memory device can be suppressed, and at the same time, the semiconductor memory device can be made faster.

[0190] Power wirings 12 and 13 for supplying a power supply voltage VSS are formed in the embedded wiring layer. In a plan view, the power wirings 12 and 13 are respectively formed at the unit boundary on the left side of the drawing surface and the unit boundary on the right side of the drawing surface. In addition, in the single-port SRAM cells arranged along the X direction, the surfaces of the nanosheets 21a facing each other in the X direction do not protrude from the gate wiring 31a. The surfaces of the nanosheets 23b facing each other in the X direction do not protrude from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction do not protrude from the gate wiring 34a. The surfaces of the nanosheets 26b facing each other in the X direction do not protrude from the gate wiring 36b. Therefore, in a plan view, the power wiring 12 is formed between the transistors PG21 and between the transistors PD21, and the distance between the transistors PG21 and between the transistors PD21 is larger than the distance d1. In a plan view, the power wiring 13 is formed between the transistors PD12 and between the transistors PG12, and the distance between the transistors PD12 and between the transistors PG12 is larger than the distance d1. That is, the power wiring 12 can be easily formed without increasing the pitch in the X direction between the transistors PG21 and without increasing the pitch in the X direction between the transistors PD21. The power wiring 13 can be easily formed without increasing the pitch in the X direction between the transistors PD12 and without increasing the pitch in the X direction between the transistors PG12. In this way, an increase in the area of the semiconductor memory device can be suppressed, and at the same time, the high speed of the semiconductor memory device can be achieved.

[0191] The same effect can also be obtained in other aspects. Figure 8 The same effect.

[0192] It should be noted that at least one of the power wirings 11 to 14 is sufficient.

[0193] (Third Embodiment)

[0194] Figure 10 is a plan view showing an example of the layout structure of the single-port SRAM cell according to the third embodiment. Specifically, Figure 10 (a) shows the upper part of the cell, Figure 10 (b) shows the lower part of the cell. In the Figure 10 single-port SRAM cell, a single-port SRAM circuit shown in the figure is constituted by load transistors PU1, PU2 and transistors PD11, PD12, PD13, PD21, PD22, PD23, PG11, PG12, PG13, PG21, PG22, PG23. Figure 4 It should be noted that in the Figure 10In [the structure], the driving transistors PD1 and PD2, and the access transistors PG1 and PG2 are each composed of three transistors. Specifically, the driving transistor PD1 is composed of transistors PD11, PD12, and PD13. The driving transistor PD2 is composed of transistors PD21, PD22, and PD23. The access transistor PG1 is composed of transistors PG11, PG12, and PG13. The access transistor PG2 is composed of transistors PG21, PG22, and PG23. Additionally, on the left and right sides of the drawing of the single-port SRAM cell in Figure 10 single-port SRAM cells obtained by inverting the single-port SRAM cell in the X direction are arranged.

[0195] As Figure 10 (b) of [the figure] shows, power supply wirings 11 to 13, 15, and 16 extending in the Y direction are formed in the embedded wiring layer. The power supply wiring 11 supplies the power supply voltage VDD. The power supply wirings 12, 13, 15, and 16 supply the power supply voltage VSS.

[0196] Nanosheets 21a to 21c, 22, 23a to 23c, 24a to 24c, 25, and 26a to 26c that extend in the X direction and the Y direction are also formed. The nanosheets 21a to 21c, 22, 23a to 23c are arranged in the X direction in the order of nanosheets 21a, 21b, 21c, 22, 23a, 23b, and 23c. The nanosheets 24a to 24c, 25, and 26a to 26c are arranged in the X direction in the order of nanosheets 24a, 24b, 24c, 25, 26a, 26b, and 26c. The nanosheets 21a, 21b, 21c, 23a, 23b, and 23c are respectively arranged in the Y direction with the nanosheets 24a, 24b, 24c, 26a, 26b, and 26c.

[0197] In Figure 10 , the widths of the nanosheets 21a to 21c, 22, 23a to 23c, 24a to 24c, 25, and 26a to 26c in the X direction are all the same.

[0198] In Figure 10 , the nanosheets 21a, 21b, 21c, 23a, 23b, 23c, 24a, 24b, 24c, 26a, 26b, and 26c become the channel portions of the transistors PG21, PG22, PG23, PD11, PD12, PD13, PD21, PD22, PD23, PG11, PG12, and PG13 respectively.

[0199] When viewed from above, the gate wiring 31a overlaps with the nanosheet 21a. When viewed from above, the gate wiring 31b overlaps with the nanosheets 21b and 21c. When viewed from above, the gate wiring 32 overlaps with the nanosheet 22. When viewed from above, the gate wiring 33a overlaps with the nanosheets 23a and 23b. When viewed from above, the gate wiring 33b overlaps with the nanosheet 23c. When viewed from above, the gate wiring 34a overlaps with the nanosheet 24a. When viewed from above, the gate wiring 34b overlaps with the nanosheets 24b and 24c. When viewed from above, the gate wiring 35 overlaps with the nanosheet 25. When viewed from above, the gate wiring 36a overlaps with the nanosheets 26a and 26b. When viewed from above, the gate wiring 36b overlaps with the nanosheet 26c.

[0200] In Figure 10 this case, the gate wiring 31a becomes the gate of the transistor PG21. The gate wiring 31b becomes the gate of the transistors PG22 and PG23. The gate wiring 32 becomes the gate of the load transistor PU1. The gate wiring 33b becomes the gate of the transistors PD11 and PD12. The gate wiring 33b becomes the gate of the transistor PD13. The gate wiring 34a becomes the gate of the transistor PD21. The gate wiring 34b becomes the gate of the transistors PD22 and PD23. The gate wiring 35 becomes the gate of the transistor PU2. The gate wiring 36a becomes the gate of the transistors PG11 and PG12. The gate wiring 36b becomes the gate of the transistor PG13.

[0201] The gate wirings 31a and 31b are connected to each other via the bridge portion 135. The gate wirings 32 and 33a are connected to each other via the bridge portion 131. The gate wirings 33a and 33b are connected to each other via the bridge portion 136. The gate wirings 34a and 34b are connected to each other via the bridge portion 137. The gate wirings 34b and 35 are connected to each other via the bridge portion 132. The gate wirings 36a and 36b are connected to each other via the bridge portion 138.

[0202] On the upper side of the drawing plane of the nanosheet 21c, between the nanosheet 21c and the nanosheet 24c, on the lower side of the drawing plane of the nanosheet 24c, on the upper side of the drawing plane of the nanosheet 23c, between the nanosheet 23c and the nanosheet 26c, and on the lower side of the drawing plane of the nanosheet 26c, pads 40c, 41c, 42c, 43c, 44c, and 45c doped with an N-type semiconductor are respectively formed. The pads 40c and 41c constitute the nodes of the transistor PG23. The pads 41c and 42c constitute the nodes of the transistor PD23. The pads 43c and 44c constitute the nodes of the transistor PD13. The pads 44c and 45c constitute the nodes of the transistor PG13.

[0203] According to the above arrangement, in Figure 10In (b) thereof, each transistor is arranged to be point-symmetrical with respect to the center point of the cell. Specifically, the load transistors PU1 and PU2 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PD11 and PD23 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PD12 and PD22 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PD13 and PD21 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PG11 and PG23 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PG12 and PG22 are arranged to be point-symmetrical with respect to the center point of the cell. The transistors PG13 and PG21 are arranged to be point-symmetrical with respect to the center point of the cell.

[0204] The local wiring 51 is connected to the pads 40a, 40b, and 40c. The local wiring 53 is connected to the pads 43a, 43b, and 43c. The local wiring 54 is connected to the pads 41a, 41b, 41c, and 48. The local wiring 55 is connected to the pads 47, 44a, 44b, and 44c. The local wiring 56 is connected to the pads 42a, 42b, and 42c. The local wiring 58 is connected to the pads 45a, 45b, and 45c.

[0205] The local wiring 53 is connected to the power supply wiring 16 via the contact hole 116. The local wiring 56 is connected to the power supply wiring 15 via the contact hole 117.

[0206] Same as Figure 7 Same as, a part of the local wirings 51 to 58 is formed such that at least one of the left and right ends in the drawing lies between the left end and the right end in the drawing of the connected pad. For example, the left end in the drawing of the local wiring 51 lies between the left end and the right end in the drawing of the pad 40a.

[0207] Same as Figure 7 Same as, the shared contact hole 61 is formed such that its left end in the drawing lies at a position on the right side in the drawing compared to the left end in the drawing of the pad 48; its right end in the drawing lies at a position on the left side in the drawing compared to the right end in the drawing of the pad 48. Same as Figure 7 Same as, the shared contact hole 62 is formed such that its left end in the drawing lies at a position on the right side in the drawing compared to the left end in the drawing of the pad 47; its right end in the drawing lies at a position on the left side in the drawing compared to the right end in the drawing of the pad 47.

[0208] Here, the left side surfaces of the nanosheets 21b, 23a, 23c, 24b, 25, 26a, and 26c in the drawing are not covered by the gate wirings 31b, 33a, 33b, 34b, 35, 36a, and 36b, respectively, and are exposed from the gate wirings 31b, 33a, 33b, 34b, 35, 36a, and 36b, respectively. The right side surfaces of the nanosheets 21a, 21c, 22, 23b, 24a, 24c, and 26b in the drawing are not covered by the gate wirings 31a, 31b, 32, 33a, 34a, 34b, and 36a, respectively, and are exposed from the gate wirings 31a, 31b, 32, 33a, 34a, 34b, and 36a, respectively.

[0209] That is, the surfaces of the nanosheets 21a and 21b on the sides facing each other in the X direction are exposed from the gate wirings 31a and 31b, respectively. The surfaces of the nanosheets 22 and 23a on the sides facing each other in the X direction are exposed from the gate wirings 32 and 33a, respectively. The surfaces of the nanosheets 23b and 23c on the sides facing each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of the nanosheets 24a and 24b on the sides facing each other in the X direction are exposed from the gate wirings 34a and 34b, respectively. The surfaces of the nanosheets 24c and 25 on the sides facing each other in the X direction are exposed from the gate wirings 34b and 35, respectively. The surfaces of the nanosheets 26b and 26c on the sides facing each other in the X direction are exposed from the gate wirings 36a and 36b, respectively.

[0210] The right side surfaces of the nanosheets 21b, 23a, 23c, 24b, 25, 26a, and 26c in the drawing are covered by the gate wirings 31b, 33a, 33b, 34b, 35, 36a, and 36b, respectively, and are not exposed from the gate wirings 31b, 33a, 33b, 34b, 35, 36a, and 36b, respectively. The left side surfaces of the nanosheets 21a, 21c, 22, 23b, 24a, 24c, and 26b in the drawing are covered by the gate wirings 31a, 31b, 32, 33a, 34a, 34b, and 36a, respectively, and are not exposed from the gate wirings 31a, 31b, 32, 33a, 34a, 34b, and 36a, respectively.

[0211] That is, the surfaces of the nanosheets 21b and 21c on the sides facing each other in the X direction are not exposed from the gate wiring 31b. The surfaces of the nanosheets 23a and 23b on the sides facing each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 24b and 24c on the sides facing each other in the X direction are not exposed from the gate wiring 34b. The surfaces of the nanosheets 26a and 26b on the sides facing each other in the X direction are not exposed from the gate wiring 36a.

[0212] The nanosheet 22 is formed above the right side of the drawing plane of the nanosheet 25. That is, the surfaces of the nanosheets 22 and 25 on the sides facing each other in the X direction are not exposed from the gate wirings 32 and 35, respectively.

[0213] The nanosheets 21a and 24a are formed at positions near the cell boundary on the left side of the drawing plane. The nanosheets 23c and 26c are formed at positions near the cell boundary on the right side of the drawing plane. On Figure 10 both the left and right sides of the drawing plane of the single-port SRAM cell, single-port SRAM cells obtained by inverting the single-port SRAM cell in the X direction are arranged. That is, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 23c facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 26c facing each other in the X direction are not exposed from the gate wiring 36b.

[0214] In Figure 10 , when viewed from above, the power supply wiring 11 is formed between the nanosheet 22 and the nanosheet 25. When viewed from above, the power supply wiring 12 is formed between the nanosheet 21b and the nanosheet 21c and between the nanosheet 24b and the nanosheet 24c. When viewed from above, the power supply wiring 13 is formed between the nanosheet 23a and the nanosheet 23b and between the nanosheet 26a and the nanosheet 26b. When viewed from above, the power supply wiring 15 is formed at the cell boundary on the left side of the drawing plane. When viewed from above, the power supply wiring 16 is formed at the cell boundary on the right side of the drawing plane.

[0215] According to the above configuration, the surfaces of the nanosheets 21a and 21b facing each other in the X direction are exposed from the gate wirings 31a and 31b, respectively. The surfaces of the nanosheets 23b and 23c facing each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of the nanosheets 24a and 24b facing each other in the X direction are exposed from the gate wirings 34a and 34b, respectively. The surfaces of the nanosheets 26b and 26c facing each other in the X direction are exposed from the gate wirings 36a and 36b, respectively. In this way, the distances d1 in the X direction between the transistor PG21 and the transistor PG22, the distances d1 in the X direction between the transistor PD12 and the transistor PD13, the distances d1 in the X direction between the transistor PD21 and the transistor PD22, and the distances d1 in the X direction between the transistor PG12 and the transistor PG13 can be reduced respectively, and thus miniaturization of the semiconductor memory device can be achieved.

[0216] By forming the power supply wiring 11 for supplying the power supply voltage VDD and the power supply wirings 12, 13, 15, 16 for supplying the power supply voltage VSS in the buried wiring layer, in the M1 wiring layer, it is possible to reduce the width in the X direction of the wiring 71 for supplying the power supply voltage VDD and the width in the X direction of the wirings 72, 73 for supplying the power supply voltage VSS. In this way, it is possible to respectively expand the width in the X direction of the wirings 75, 74 that become the bit lines BL, BLB, and thus it is possible to achieve high speed operation of the semiconductor memory device and improvement of the write characteristics.

[0217] In a plan view, the power supply wirings 15, 16 are respectively formed at the unit boundary on the left side of the drawing plane and the unit boundary on the right side of the drawing plane. Further, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction do not protrude from the gate wiring 31a. The surfaces of the nanosheets 23c facing each other in the X direction do not protrude from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction do not protrude from the gate wiring 34a. The surfaces of the nanosheets 26c facing each other in the X direction do not protrude from the gate wiring 36b. Therefore, in a plan view, the power supply wiring 15 is formed between the transistors PG21 and between the transistors PD21, and the distance in the X direction between the transistors PG21 and between the transistors PD21 is larger than the distance d1. In a plan view, the power supply wiring 16 is formed between the transistors PD13 and between the transistors PG13, and the distance in the X direction between the transistors PD13 and between the transistors PG13 is larger than the distance d1. That is, it is possible to easily form the power supply wiring 15 without expanding the pitch in the X direction between the transistors PG21 and the pitch in the X direction between the transistors PD21. It is possible to easily form the power supply wiring 13 without expanding the pitch in the X direction between the transistors PD13 and the pitch in the X direction between the transistors PG13. In this way, it is possible to suppress an increase in the area of the semiconductor memory device.

[0218] Therefore, in a semiconductor memory device including single-port SRAM cells using cross-sheet transistors, it is possible to suppress an increase in area and at the same time achieve high speed operation and improvement of write characteristics.

[0219] It should be noted that some of the power supply wirings 11 to 13, 15, 16 can be omitted, and at least one of the power supply wirings is sufficient.

[0220] (Modification Example 1)

[0221] Figure 11It is a top view showing another example of the layout structure of the single-port SRAM cell according to the third embodiment. Specifically, Figure 11 (a) of Figure 11 shows the upper part of the cell, Figure 11 (b) of Figure 11 shows the lower part of the cell. In Figure 11 , the surfaces of the respective nanosheets on the side opposite to that in Figure 10 are exposed from the gate wiring. In addition, the arrangement of the wirings formed in the buried wiring layer is different.

[0222] Power wirings 11 to 14 are formed in the buried wiring layer. The power wirings 11 and 14 supply the power supply voltage VDD. The power wirings 12 and 13 supply the power supply voltage VSS.

[0223] As Figure 11 (b) of Figure 11 shows, gate wirings 31a, 31b, 32, 33a, 33b, 34a, 34b, 35, 36a, and 36b are formed. When viewed from above, the gate wiring 31a overlaps with the nanosheets 21a and 21b. When viewed from above, the gate wiring 31b overlaps with the nanosheet 21c. When viewed from above, the gate wiring 33a overlaps with the nanosheets 22 and 23a. When viewed from above, the gate wiring 33b overlaps with the nanosheets 23b and 23c. When viewed from above, the gate wiring 34a overlaps with the nanosheets 24a and 24b. When viewed from above, the gate wiring 34b overlaps with the nanosheets 24c and 25. When viewed from above, the gate wiring 36a overlaps with the nanosheet 26a. When viewed from above, the gate wiring 36b overlaps with the nanosheets 26b and 26c.

[0224] In Figure 11 , the gate wiring 31a becomes the gates of the transistors PG21 and PG22. The gate wiring 31b becomes the gate of the transistor PG23. The gate wiring 33a becomes the gates of the load transistor PU1 and the transistor PD11. The gate wiring 33b becomes the gates of the transistors PD12 and PD13. The gate wiring 34a becomes the gates of the transistors PD21 and PD22. The gate wiring 34b becomes the gates of the transistor PD23 and the load transistor PU2. The gate wiring 36a becomes the gate of the transistor PG11. The gate wiring 36b becomes the gates of the transistors PG12 and PG13.

[0225] The gate wiring 31a is connected to the gate wiring 31a of a single-port SRAM cell arranged on the left side of the drawing of this single-port SRAM cell via the bridge portion 133. The gate wirings 31a and 31b are connected to each other via the bridge portion 135. The gate wirings 32 and 33a are connected to each other via the bridge portion 131. The gate wirings 33a and 33b are connected to each other via the bridge portion 136. The gate wirings 34a and 34b are connected to each other via the bridge portion 137. The gate wiring 34b and 35 are connected to each other via the bridge portion 132. The gate wirings 36a and 36b are connected to each other via the bridge portion 138. The gate wiring 36b is connected to the gate wiring 36b of a single-port SRAM cell arranged on the right side of the drawing of this single-port SRAM cell via the bridge portion 134.

[0226] The wiring 76 is connected to the gate wiring 31a via the contact hole 87 and the bridge portion 133. The wiring 77 is connected to the gate wiring 36b via the contact hole 88 and the bridge portion 134.

[0227] In Figure 11 , the right-side surfaces of the nanosheets 21b, 23a, 23c, 24b, 25, 26a, and 26c are not covered by the gate wirings 31a, 33a, 33b, 34a, 34b, 36a, and 36b, respectively, and are exposed from the gate wirings 31a, 33a, 33b, 34a, 34b, 36a, and 36b, respectively. The left-side surfaces of the nanosheets 21a, 21c, 22, 23b, 24a, 24c, and 26b are not covered by the gate wirings 31a, 31b, 33a, 33b, 34a, 34b, and 36b, respectively, and are exposed from the gate wirings 31a, 31b, 33a, 33b, 34a, 34b, and 36b, respectively.

[0228] That is, the surfaces of the nanosheets 21b and 21c on the sides facing each other in the X direction are exposed from the gate wirings 31a and 31b, respectively. The surfaces of the nanosheets 23a and 23b on the sides facing each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of the nanosheets 24b and 24c on the sides facing each other in the X direction are exposed from the gate wirings 34a and 34b, respectively. The surfaces of the nanosheets 26a and 26b on the sides facing each other in the X direction are exposed from the gate wirings 36a and 36b, respectively.

[0229] The nanosheet 22 is formed above the right side of the drawing of the nanosheet 25. That is, the surfaces of the nanosheets 22 and 25 on the sides facing each other in the X direction are exposed from the gate wirings 33a and 34b, respectively.

[0230] The nanosheets 21a and 24a are arranged at positions close to the cell boundary on the left side of the drawing. The nanosheets 23c and 26c are arranged at positions close to the cell boundary on the right side of the drawing. In Figure 11On the left and right sides of the drawing of the single-port SRAM cell, single-port SRAM cells obtained by inverting the single-port SRAM cell along the X direction are arranged. That is, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are exposed from the gate wiring 31a. The surfaces of the nanosheets 23c facing each other in the X direction are exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are exposed from the gate wiring 34a. The surfaces of the nanosheets 26c facing each other in the X direction are exposed from the gate wiring 36b.

[0231] The left-side surfaces of the nanosheets 21b, 23a, 23c, 24b, 25, 26a, and 26c are respectively covered by the gate wirings 31a, 33a, 33b, 34a, 34b, 36a, and 36b and are not exposed from the gate wirings 31a, 33a, 33b, 34a, 34b, 36a, and 36b. The right-side surfaces of the nanosheets 21a, 21c, 22, 23b, 24a, 24c, and 26b are respectively covered by the gate wirings 31a, 31b, 33a, 33b, 34a, 34b, and 36b and are not exposed from the gate wirings 31a, 31b, 33a, 33b, 34a, 34b, and 36b.

[0232] That is, the surfaces of the nanosheets 21a and 21b facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 22 and 23a facing each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 23b and 23c facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a and 24b facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 24c and 25 facing each other in the X direction are not exposed from the gate wiring 34b. The surfaces of the nanosheets 26b and 26c facing each other in the X direction are not exposed from the gate wiring 36b.

[0233] In Figure 11 When viewed from above, the power supply wiring 12 is formed between the nanosheets 21a and 21b and between the nanosheets 24a and 24b. When viewed from above, the power supply wiring 11 is formed between the nanosheets 24c and 25. When viewed from above, the power supply wiring 14 is formed between the nanosheets 22 and 23a. When viewed from above, the power supply wiring 13 is formed between the nanosheets 23b and 23c and between the nanosheets 26b and 26c.

[0234] According to Figure 11In the layout structure, in the single-port SRAM cells arranged in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are exposed from the gate wiring 31a. The surfaces of the nanosheets 23c facing each other in the X direction are exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are exposed from the gate wiring 34a. The surfaces of the nanosheets 26c facing each other in the X direction are exposed from the gate wiring 36b. In this way, the distances d1 in the X direction between the transistors PG21, between the transistors PD13, between the transistors PD21, and between the transistors PG13 can be reduced respectively, so that miniaturization of the semiconductor memory device can be achieved.

[0235] Power wirings 12 and 13 for supplying a power supply voltage VSS are formed in the embedded wiring layer. In a plan view, the power wiring 12 is formed between the nanosheets 21a and 21b and between the nanosheets 24a and 24b. In a plan view, the power wiring 13 is formed between the nanosheets 23b and 23c and between the nanosheets 26b and 26c. In addition, the surfaces of the nanosheets 21a and 21b on the side facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 22 and 23a on the side facing each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 23b and 23c on the side facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a and 24b on the side facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 24c and 25 on the side facing each other in the X direction are not exposed from the gate wiring 34b. The surfaces of the nanosheets 26b and 26c on the side facing each other in the X direction are not exposed from the gate wiring 36b. Therefore, in a plan view, the power wiring 12 is formed between the transistors PG21 and PG22 and between the transistors PD21 and PD22, and the distance in the X direction between the transistors PG21 and PG22 and between the transistors PD21 and PD22 is larger than the distance d1. In a plan view, the power wiring 13 is formed between the transistors PD12 and PD13 and between the transistors PG12 and PG13, and the distance in the X direction between the transistors PD12 and PD13 and between the transistors PG12 and PG13 is larger than the distance d1. That is, the power wiring 12 can be easily formed without increasing the pitch in the X direction between the transistors PG21 and PG22 and between the transistors PD21 and PD22. The power wiring 13 can be easily formed without increasing the pitch in the X direction between the transistors PD12 and PD13 and between the transistors PG12 and PG13. In this way, an increase in the area of the semiconductor memory device can be suppressed, and at the same time, the semiconductor memory device can be made faster.

[0236] The same effect can also be obtained in other aspects. Figure 10 Same effect.

[0237] (Modification 2)

[0238] Figure 12 FIG. is a plan view showing another example of the layout structure of the single-port SRAM cell according to the third embodiment. Specifically, Figure 12 FIG. (a) shows the upper part of the cell, Figure 12 FIG. (b) shows the lower part of the cell. Compared with Figure 10 In Figure 12In this case, the access transistors PG1 and PG2 are each composed of two transistors.

[0239] In Figure 12 the nanosheets 21c, 26a and the pads 40c, 45a in Figure 10 are omitted. That is, the access transistor PG2 is composed of the transistors PG21 and PG22. The access transistor PG1 is composed of the transistors PG12 and PG13.

[0240] Through Figure 12 the layout structure of, the same effect as that of Figure 10 can be obtained.

[0241] (Modification 3)

[0242] Figure 13 is a top view showing another example of the layout structure of the single-port SRAM cell according to the third embodiment. Specifically, Figure 13 (a) of shows the upper part of the cell, Figure 13 (b) of shows the lower part of the cell. Compared with Figure 11 in, the access transistors PG1 and PG2 are each composed of two transistors. In addition, the gate wiring 31a and the gate wiring 31b are not connected. The gate wiring 36a and the gate wiring 36b are not connected. Figure 13

[0243] Figure 13 In Figure 11 the nanosheets 21c, 26a and the pads 40c, 45a in are omitted. That is, the access transistor PG2 is composed of the transistors PG21 and PG22. The access transistor PG1 is composed of the transistors PG12 and PG13.

[0244] Figure 11 The bridge portions 135 and 138 of are also omitted. That is, the gate wiring 31a and the gate wiring 31b are not connected. The gate wiring 36a and the gate wiring 36b are not connected.

[0245] Figure 13 According to the layout structure of, the gate wiring 31a and the gate wiring 31b are not connected. The gate wiring 36a and the gate wiring 36b are not connected. In this way, the gate wirings 31b and 31a that do not function as part of the transistor can be disconnected from the circuit constituting the single-port SRAM cell, so that the load capacitance of the word line can be suppressed.

[0246] Figure 11 In other aspects, the same effect as that of the layout structure of can be obtained.

[0247] ​It should be noted that in the above embodiments and variations, each transistor includes three nanosheets, but a part or all of the transistors may also include one, two, or more than four nanosheets.

[0248] In the above embodiments, the cross-sectional shape of the nanosheet is rectangular, but it is not limited thereto. For example, it may also be square, circular, elliptical, etc.

[0249] -Industrial Applicability-

[0250] In the present disclosure, in the layout structure of a single-port SRAM cell using a cross-sheet transistor, an increase in the area of the semiconductor memory device can be suppressed, and at the same time, high-speed operation and improved write characteristics of the semiconductor memory device can be achieved.

[0251] -Symbol Explanation-

[0252] 11 - 16 Power supply wiring

[0253] 21 - 26, 21a - 21c, 23a - 23c, 24a - 24c, 26a - 26c Nanosheets

[0254] 31 - 36, 31a, 31b, 33a, 33b, 34a, 34b, 36a, 36b Gate wiring

[0255] 40 - 49, 40a - 46a, 40b - 46b, 40c - 46c Pads

[0256] 51 - 58 Local wiring

[0257] 61, 62 Shared contact holes

[0258] 71 - 77, 91 - 93 Wiring

[0259] PU1, PU2 Load transistors

[0260] PD1, PD2 Drive transistors

[0261] PG1, PG2 Access transistors

[0262] PG11 - PG13, PG21 - PG23, PD11 - PD13, PD21 - PD23 Transistors

[0263] BL, BLB Bit lines

[0264] WL Word line

Claims

1. A semiconductor memory device includes a single-port SRAM cell, characterized in that: The single-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, One node of the first transistor is connected to a first power supply that supplies a first voltage, another node is connected to a first node, and the gate is connected to a second node, One node of the second transistor is connected to the first power supply, another node is connected to the second node, and the gate is connected to the first node, One node of the third transistor is connected to the first node, another node is connected to a second power supply that supplies a second voltage, the gate is connected to the second node, and the second voltage is different from the first voltage, One node of the fourth transistor is connected to the second node, another node is connected to the second power supply, and the gate is connected to the first node, One node of the fifth transistor is connected to a first bit line, another node is connected to the first node, and the gate is connected to a word line, One node of the sixth transistor is connected to a second bit line, another node is connected to the second node, and the gate is connected to the word line, and the second bit line and the first bit line form a complementary bit line pair, The first transistor includes a first nanosheet and a first gate wiring, the second transistor includes a second nanosheet and a second gate wiring, the third transistor includes a third nanosheet and a third gate wiring, the fourth transistor includes a fourth nanosheet and a fourth gate wiring, the fifth transistor includes a fifth nanosheet and a fifth gate wiring, and the sixth transistor includes a sixth nanosheet and a sixth gate wiring, The first nanosheet to the sixth nanosheet extend in a first direction, The first gate wiring surrounds the outer periphery of the first nanosheet in a second direction and a third direction, the second gate wiring surrounds the outer periphery of the second nanosheet in a second direction and a third direction, the third gate wiring surrounds the outer periphery of the third nanosheet in a second direction and a third direction, the fourth gate wiring surrounds the outer periphery of the fourth nanosheet in a second direction and a third direction, the fifth gate wiring surrounds the outer periphery of the fifth nanosheet in a second direction and a third direction, the sixth gate wiring surrounds the outer periphery of the sixth nanosheet in a second direction and a third direction, the second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and the second direction, The first nanosheet, the third nanosheet, and the sixth nanosheet are arranged in the second direction in the order of the sixth nanosheet, the first nanosheet, and the third nanosheet, The second nanosheet, the fourth nanosheet, and the fifth nanosheet are arranged in the second direction in the order of the fourth nanosheet, the second nanosheet, and the fifth nanosheet, A surface on either side of the first nanosheet in the second direction is exposed from the first gate wiring, a surface on either side of the second nanosheet in the second direction is exposed from the second gate wiring, a surface on either side of the third nanosheet in the second direction is exposed from the third gate wiring, a surface on either side of the fourth nanosheet in the second direction is exposed from the fourth gate wiring, a surface on either side of the fifth nanosheet in the second direction is exposed from the fifth gate wiring, and a surface on either side of the sixth nanosheet in the second direction is exposed from the sixth gate wiring. A first power supply wiring is formed in a lower layer below the first transistor to the sixth transistor. When viewed from above, the first power supply wiring extends in the first direction between the first nanosheet and the second nanosheet and supplies the first voltage. A surface of the second side, which is the side opposite to the first side of the first nanosheet in the second direction, is exposed from the first gate wiring, and the first power supply wiring is formed on the first side of the first nanosheet. A surface of the first side, which is the side opposite to the second side of the second nanosheet in the second direction, is exposed from the second gate wiring, and the first power supply wiring is formed on the second side of the second nanosheet.

2. The semiconductor memory device according to claim 1, wherein: The single-port SRAM cell further includes a first wiring and a second wiring. The first wiring extends in the first direction and serves as the first bit line. The second wiring extends in the first direction and serves as the second bit line. The first wiring and the second wiring are formed in the same first wiring layer, which is an upper layer above the first transistor to the sixth transistor. The width in the second direction of at least one of the first wiring and the second wiring is wider than the width of the wiring having the smallest width in the second direction among the wirings formed in the first wiring layer.

3. The semiconductor memory device according to claim 1, wherein: The single-port SRAM cell further includes a third wiring, a fourth wiring, and a fifth wiring. The third wiring extends in the second direction and supplies the second voltage. The fourth wiring extends in the second direction and supplies the second voltage. The fifth wiring extends in the second direction and serves as the word line. The third wiring to the fifth wiring are formed in a second wiring layer, which is an upper layer above the first transistor to the sixth transistor. When viewed from above, the fifth wiring is formed between the third wiring and the fourth wiring.

4. The semiconductor memory device according to claim 1, wherein: The single-port SRAM cell further includes a second power supply wiring and a third power supply wiring. The second power supply wiring is in a lower layer below the first transistor to the sixth transistor. When viewed from above, it extends in the first direction on the first side of the fourth nanosheet and supplies the second voltage. The third power supply wiring is in a lower layer than the first through sixth transistors, extends in the first direction along the second side of the third nanosheet in a plan view, and supplies the second voltage. The surface of the first side of the third nanosheet is exposed from the third gate wiring. The surface of the second side of the fourth nanosheet is exposed from the fourth gate wiring.

5. The semiconductor memory device according to claim 4, wherein: In a plan view, the second power supply wiring is formed at the unit boundary of the first side of the single-port SRAM cell. In a plan view, the third power supply wiring is formed at the unit boundary of the second side of the single-port SRAM cell. The fourth nanosheet and the sixth nanosheet are formed at positions close to the unit boundary of the first side of the single-port SRAM cell. The third nanosheet and the fifth nanosheet are formed at positions close to the unit boundary of the second side of the single-port SRAM cell. The surface of the first side of the fifth nanosheet is exposed from the fifth gate wiring. The surface of the second side of the sixth nanosheet is exposed from the sixth gate wiring.

6. The semiconductor memory device according to claim 5, wherein: The single-port SRAM cell includes local wiring that extends in the second direction and is connected to a node of any one of the first through sixth transistors. An end portion of the local wiring in the second direction is located between both ends of the connected node.

7. The semiconductor memory device according to claim 4, wherein: The third transistor further includes a seventh nanosheet, the fourth transistor further includes an eighth nanosheet, the fifth transistor further includes a ninth nanosheet, the sixth transistor further includes a tenth nanosheet, and the seventh through tenth nanosheets extend in the first direction. The third gate wiring surrounds the outer periphery of the seventh nanosheet in the second and third directions, the fourth gate wiring surrounds the outer periphery of the eighth nanosheet in the second and third directions, the fifth gate wiring surrounds the outer periphery of the ninth nanosheet in the second and third directions, and the sixth gate wiring surrounds the outer periphery of the tenth nanosheet in the second and third directions. The first nanosheet, the third nanosheet, the sixth nanosheet, the seventh nanosheet, and the tenth nanosheet are arranged in the second direction in the order of the tenth nanosheet, the sixth nanosheet, the first nanosheet, the third nanosheet, and the seventh nanosheet. The second nanosheet, the fourth nanosheet, the fifth nanosheet, the eighth nanosheet, and the ninth nanosheet are arranged in the second direction in the order of the eighth nanosheet, the fourth nanosheet, the second nanosheet, the fifth nanosheet, and the ninth nanosheet. When viewed from above, the second power supply wiring is formed between the sixth nanosheet and the tenth nanosheet, and between the fourth nanosheet and the eighth nanosheet. When viewed from above, the third power supply wiring is formed between the third nanosheet and the seventh nanosheet, and between the fifth nanosheet and the ninth nanosheet. The surface of the first side of the fifth nanosheet is exposed from the fifth gate wiring, the surface of the first side of the eighth nanosheet is exposed from the fourth gate wiring, and the surface of the first side of the tenth nanosheet is exposed from the sixth gate wiring. The surface of the second side of the sixth nanosheet is exposed from the sixth gate wiring, the surface of the second side of the seventh nanosheet is exposed from the third gate wiring, and the surface of the second side of the ninth nanosheet is exposed from the fifth gate wiring.

8. The semiconductor memory device according to claim 7, characterized in that: The single-port SRAM cell further includes a fourth power supply wiring and a fifth power supply wiring. The fourth power supply wiring is in a lower layer than the first transistor to the sixth transistor, extends along the first direction at the unit boundary of the first side of the single-port SRAM cell, and supplies the second voltage. The fifth power supply wiring is in a lower layer than the first transistor to the sixth transistor, extends along the first direction at the unit boundary of the second side of the single-port SRAM cell, and supplies the second voltage. The third transistor further includes an eleventh nanosheet, the fourth transistor further includes a twelfth nanosheet, the fifth transistor further includes a thirteenth nanosheet, the sixth transistor further includes a fourteenth nanosheet, and the eleventh nanosheet to the fourteenth nanosheet extend along the first direction. The third gate wiring surrounds the outer periphery of the eleventh nanosheet in the second direction and the third direction, the fourth gate wiring surrounds the outer periphery of the twelfth nanosheet in the second direction and the third direction, the fifth gate wiring surrounds the outer periphery of the thirteenth nanosheet in the second direction and the third direction, and the sixth gate wiring surrounds the outer periphery of the fourteenth nanosheet in the second direction and the third direction. The first nanosheet, the third nanosheet, the sixth nanosheet, the seventh nanosheet, the tenth nanosheet, the eleventh nanosheet, and the fourteenth nanosheet are arranged in the second direction in the order of the fourteenth nanosheet, the tenth nanosheet, the sixth nanosheet, the first nanosheet, the third nanosheet, the seventh nanosheet, and the eleventh nanosheet. The second nanosheet, the fourth nanosheet, the fifth nanosheet, the eighth nanosheet, the ninth nanosheet, the twelfth nanosheet, and the thirteenth nanosheet are arranged in the second direction in the order of the twelfth nanosheet, the eighth nanosheet, the fourth nanosheet, the second nanosheet, the fifth nanosheet, the ninth nanosheet, and the thirteenth nanosheet. The twelfth nanosheet is formed at a position near the cell boundary on the first side of the single-port SRAM cell, and the surface of the second side is exposed from the fourth gate wiring. The fourteenth nanosheet is formed at a position near the cell boundary on the first side of the single-port SRAM cell, and the surface of the second side is exposed from the sixth gate wiring. The eleventh nanosheet is formed at a position near the cell boundary on the second side of the single-port SRAM cell, and the surface of the first side is exposed from the third gate wiring. The thirteenth nanosheet is formed at a position near the cell boundary on the second side of the single-port SRAM cell, and the surface of the first side is exposed from the fifth gate wiring.

9. The semiconductor memory device according to claim 4, characterized in that: The third transistor further includes a seventh nanosheet and an eighth nanosheet extending along the first direction. The fourth transistor further includes a ninth nanosheet and a tenth nanosheet extending along the first direction. The fifth transistor further includes an eleventh nanosheet extending along the first direction. The sixth transistor further includes a twelfth nanosheet extending along the first direction. The third gate wiring surrounds the outer peripheries of the seventh nanosheet in the second and third directions and the outer peripheries of the eighth nanosheet in the second and third directions. The fourth gate wiring surrounds the outer peripheries of the ninth nanosheet in the second and third directions and the outer peripheries of the tenth nanosheet in the second and third directions. The fifth gate wiring surrounds the outer peripheries of the eleventh nanosheet in the second and third directions. The sixth gate wiring surrounds the outer peripheries of the twelfth nanosheet in the second and third directions. The first nanosheet, the third nanosheet, the sixth nanosheet, the seventh nanosheet, the eighth nanosheet, and the twelfth nanosheet are arranged in the second direction in the order of the twelfth nanosheet, the sixth nanosheet, the first nanosheet, the third nanosheet, the seventh nanosheet, and the eighth nanosheet. The second nanosheet, the fourth nanosheet, the fifth nanosheet, the ninth nanosheet, the tenth nanosheet, and the eleventh nanosheet are arranged in the second direction in the order of the tenth nanosheet, the ninth nanosheet, the fourth nanosheet, the second nanosheet, the fifth nanosheet, and the eleventh nanosheet. When viewed from above, the second power supply wiring is formed between the fourth nanosheet and the ninth nanosheet. When viewed from above, the third power supply wiring is formed between the third nanosheet and the seventh nanosheet. The tenth nanosheet and the twelfth nanosheet are formed at positions near the cell boundary on the first side of the single-port SRAM cell. The eighth nanosheet and the eleventh nanosheet are formed at positions near the cell boundary on the second side of the single-port SRAM cell. A fourth power supply wiring is formed in a lower layer below the first through sixth transistors. The fourth power supply wiring extends along the first direction at a unit boundary on the first side of the single-port SRAM cell and supplies the second voltage. A fifth power supply wiring is formed in a lower layer below the first through sixth transistors. The fifth power supply wiring extends along the first direction at a unit boundary on the second side of the single-port SRAM cell and supplies the second voltage. The surface on the first side of the sixth nanosheet is exposed from the sixth gate wiring, the surface on the first side of the eighth nanosheet is exposed from the third gate wiring, the surface on the first side of the ninth nanosheet is exposed from the fourth gate wiring, and the surface on the first side of the eleventh nanosheet is exposed from the fifth gate wiring. The surface on the second side of the fifth nanosheet is exposed from the fifth gate wiring, the surface on the second side of the seventh nanosheet is exposed from the third gate wiring, the surface on the second side of the tenth nanosheet is exposed from the fourth gate wiring, and the surface on the second side of the twelfth nanosheet is exposed from the sixth gate wiring.

10. The semiconductor memory device according to claim 9, wherein: the sixth nanosheet and the ninth nanosheet are formed at the same position in the second direction; the fifth nanosheet and the seventh nanosheet are formed at the same position in the second direction; the eighth nanosheet and the eleventh nanosheet are formed at the same position in the second direction; the tenth nanosheet and the twelfth nanosheet are formed at the same position in the second direction.

11. A semiconductor memory device including a single-port SRAM cell, wherein: the single-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; one node of the first transistor is connected to a first power supply that supplies a first voltage, another node is connected to the first node, and the gate is connected to the second node; one node of the second transistor is connected to the first power supply, another node is connected to the second node, and the gate is connected to the first node; one node of the third transistor is connected to the first node, another node is connected to a second power supply that supplies a second voltage, the gate is connected to the second node, and the second voltage is different from the first voltage; one node of the fourth transistor is connected to the second node, another node is connected to the second power supply, and the gate is connected to the first node; one node of the fifth transistor is connected to a first bit line, another node is connected to the first node, and the gate is connected to a word line; one node of the sixth transistor is connected to a second bit line, another node is connected to the second node, and the gate is connected to the word line, and the second bit line and the first bit line form a complementary bit line pair. The first transistor includes a first nanosheet and a first gate wiring, the second transistor includes a second nanosheet and a second gate wiring, the third transistor includes a third nanosheet and a third gate wiring, the fourth transistor includes a fourth nanosheet and a fourth gate wiring, the fifth transistor includes a fifth nanosheet and a fifth gate wiring, and the sixth transistor includes a sixth nanosheet and a sixth gate wiring. The first nanosheet to the sixth nanosheet extend in a first direction. The first gate wiring surrounds the outer periphery of the first nanosheet in a second direction and a third direction, the second gate wiring surrounds the outer periphery of the second nanosheet in the second direction and the third direction, the third gate wiring surrounds the outer periphery of the third nanosheet in the second direction and the third direction, the fourth gate wiring surrounds the outer periphery of the fourth nanosheet in the second direction and the third direction, the fifth gate wiring surrounds the outer periphery of the fifth nanosheet in the second direction and the third direction, and the sixth gate wiring surrounds the outer periphery of the sixth nanosheet in the second direction and the third direction. The second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and the second direction. The first nanosheet, the third nanosheet, and the sixth nanosheet are arranged in the second direction in the order of the sixth nanosheet, the first nanosheet, and the third nanosheet. The second nanosheet, the fourth nanosheet, and the fifth nanosheet are arranged in the second direction in the order of the fourth nanosheet, the second nanosheet, and the fifth nanosheet. Any side surface of the first nanosheet in the second direction is exposed from the first gate wiring, any side surface of the second nanosheet in the second direction is exposed from the second gate wiring, any side surface of the third nanosheet in the second direction is exposed from the third gate wiring, any side surface of the fourth nanosheet in the second direction is exposed from the fourth gate wiring, any side surface of the fifth nanosheet in the second direction is exposed from the fifth gate wiring, and any side surface of the sixth nanosheet in the second direction is exposed from the sixth gate wiring. The surface of the first side of the first nanosheet is exposed from the first gate wiring, and the first side is the side opposed to the second nanosheet in the second direction. The surface of the second side of the second nanosheet is exposed from the second gate wiring, and the second side is the side opposed to the first nanosheet in the second direction. A first power supply wiring is formed in a lower layer below the first transistor to the sixth transistor. When viewed from above, the first power supply wiring extends in the first direction along the second side of the first nanosheet and supplies the first voltage or the second voltage. A second power supply wiring is formed in a lower layer below the first transistor to the sixth transistor. When viewed from above, the second power supply wiring extends in the first direction along the second side of the second nanosheet and supplies the first voltage or the second voltage.

12. The semiconductor memory device according to claim 11, wherein: The single-port SRAM cell further includes a first wiring and a second wiring, The first wiring extends in the first direction and serves as the first bit line, The second wiring extends in the first direction and serves as the second bit line, The first wiring and the second wiring are formed in the same first wiring layer, which is an upper layer above the first transistor to the sixth transistor, The width of at least one of the first wiring and the second wiring in the second direction is smaller than the width of the wiring having the smallest width in the second direction among the wirings formed in the first wiring layer.

13. The semiconductor memory device according to claim 11, wherein: The single-port SRAM cell further includes a third wiring, a fourth wiring, and a fifth wiring, The third wiring extends in the second direction and supplies the second voltage, The fourth wiring extends in the second direction and supplies the second voltage, The fifth wiring extends in the second direction and serves as the word line, The third wiring to the fifth wiring are formed in a second wiring layer, which is an upper layer above the first transistor to the sixth transistor, When viewed from above, the fifth wiring is formed between the third wiring and the fourth wiring.

14. The semiconductor memory device according to claim 14, wherein: The surface of the first side of the fourth nanosheet is exposed from the fourth gate wiring, The surface of the second side of the third nanosheet is exposed from the third gate wiring, When viewed from above, the first power supply wiring is formed between the first nanosheet and the third nanosheet, When viewed from above, the second power supply wiring is formed between the second nanosheet and the fourth nanosheet.

15. The semiconductor memory device according to claim 14, wherein: The third transistor further includes a seventh nanosheet, the fourth transistor further includes an eighth nanosheet, the fifth transistor further includes a ninth nanosheet, the sixth transistor further includes a tenth nanosheet, and the seventh nanosheet to the tenth nanosheet extend in the first direction, The third gate wiring surrounds the outer periphery of the seventh nanosheet in the second direction and the third direction, the fourth gate wiring surrounds the outer periphery of the eighth nanosheet in the second direction and the third direction, the fifth gate wiring surrounds the outer periphery of the ninth nanosheet in the second direction and the third direction, and the sixth gate wiring surrounds the outer periphery of the tenth nanosheet in the second direction and the third direction. The first nanosheet, the third nanosheet, the sixth nanosheet, the seventh nanosheet, and the tenth nanosheet are arranged in the second direction in the order of the tenth nanosheet, the sixth nanosheet, the first nanosheet, the third nanosheet, and the seventh nanosheet. The second nanosheet, the fourth nanosheet, the fifth nanosheet, the eighth nanosheet, and the ninth nanosheet are arranged in the second direction in the order of the eighth nanosheet, the fourth nanosheet, the second nanosheet, the fifth nanosheet, and the ninth nanosheet. A third power supply wiring is formed in a lower layer below the first transistor to the sixth transistor. When viewed from above, the third power supply wiring extends in the first direction along the first side of the eighth nanosheet and the tenth nanosheet and supplies the second voltage. A fourth power supply wiring is formed in a lower layer below the first transistor to the sixth transistor. When viewed from above, the fourth power supply wiring extends in the first direction along the second side of the seventh nanosheet and the ninth nanosheet and supplies the second voltage. The surface of the first side of the sixth nanosheet is exposed from the sixth gate wiring, the surface of the first side of the seventh nanosheet is exposed from the third gate wiring, and the surface of the first side of the ninth nanosheet is exposed from the fifth gate wiring. The surface of the second side of the fifth nanosheet is exposed from the fifth gate wiring, the surface of the second side of the eighth nanosheet is exposed from the fourth gate wiring, and the surface of the second side of the tenth nanosheet is exposed from the sixth gate wiring.

16. The semiconductor memory device according to claim 15, wherein: The eighth nanosheet and the tenth nanosheet are formed at positions close to the unit boundary on the first side of the single-port SRAM cell. The seventh nanosheet and the ninth nanosheet are formed at positions close to the unit boundary on the second side of the single-port SRAM cell. When viewed from above, the third power supply wiring is formed at the unit boundary on the first side of the single-port SRAM cell. When viewed from above, the fourth power supply wiring is formed at the unit boundary on the second side of the single-port SRAM cell.

17. The semiconductor memory device according to claim 15, wherein: The third transistor further includes an eleventh nanosheet, the fourth transistor further includes a twelfth nanosheet, the fifth transistor further includes a thirteenth nanosheet, the sixth transistor further includes a fourteenth nanosheet, and the eleventh nanosheet to the fourteenth nanosheet extend in the first direction. The third gate wiring surrounds the outer peripheries of the eleventh nanosheet in the second direction and the third direction, the fourth gate wiring surrounds the outer peripheries of the twelfth nanosheet in the second direction and the third direction, the fifth gate wiring surrounds the outer peripheries of the thirteenth nanosheet in the second direction and the third direction, and the sixth gate wiring surrounds the outer peripheries of the fourteenth nanosheet in the second direction and the third direction. The first nanosheet, the third nanosheet, the sixth nanosheet, the seventh nanosheet, the tenth nanosheet, the eleventh nanosheet, and the fourteenth nanosheet are arranged in the second direction in the order of the fourteenth nanosheet, the tenth nanosheet, the sixth nanosheet, the first nanosheet, the third nanosheet, the seventh nanosheet, and the eleventh nanosheet. The second nanosheet, the fourth nanosheet, the fifth nanosheet, the eighth nanosheet, the ninth nanosheet, the twelfth nanosheet, and the thirteenth nanosheet are arranged in the second direction in the order of the twelfth nanosheet, the eighth nanosheet, the fourth nanosheet, the second nanosheet, the fifth nanosheet, the ninth nanosheet, and the thirteenth nanosheet. When viewed from above, the third power supply wiring is formed between the eighth nanosheet and the twelfth nanosheet and between the tenth nanosheet and the fourteenth nanosheet. When viewed from above, the fourth power supply wiring is formed between the seventh nanosheet and the eleventh nanosheet and between the ninth nanosheet and the thirteenth nanosheet. The surface of the first side of the twelfth nanosheet is exposed from the fourth gate wiring, and the surface of the first side of the fourteenth nanosheet is exposed from the sixth gate wiring. The surface of the second side of the eleventh nanosheet is exposed from the third gate wiring, and the surface of the second side of the thirteenth nanosheet is exposed from the fifth gate wiring.

18. The semiconductor memory device according to claim 14, characterized in that: The third transistor further includes a seventh nanosheet and an eighth nanosheet extending in the first direction. The fourth transistor further includes a ninth nanosheet and a tenth nanosheet extending in the first direction. The fifth transistor further includes an eleventh nanosheet extending in the first direction. The sixth transistor further includes a twelfth nanosheet extending in the first direction. The third gate wiring surrounds the outer peripheries of the seventh nanosheet in the second direction and the third direction and the outer peripheries of the eighth nanosheet in the second direction and the third direction. The fourth gate wiring surrounds the outer peripheries of the ninth nanosheet in the second direction and the third direction and the outer peripheries of the tenth nanosheet in the second direction and the third direction. The fifth gate wiring surrounds the outer peripheries of the eleventh nanosheet in the second direction and the third direction. The sixth gate wiring surrounds the outer peripheries of the twelfth nanosheet in the second direction and the third direction. The first nanosheet, the third nanosheet, the sixth nanosheet, the seventh nanosheet, the eighth nanosheet, and the twelfth nanosheet are arranged in the second direction in the order of the twelfth nanosheet, the sixth nanosheet, the first nanosheet, the third nanosheet, the seventh nanosheet, and the eighth nanosheet. The second nanosheet, the fourth nanosheet, the fifth nanosheet, the ninth nanosheet, the tenth nanosheet, and the eleventh nanosheet are arranged in the second direction in the order of the tenth nanosheet, the ninth nanosheet, the fourth nanosheet, the second nanosheet, the fifth nanosheet, and the eleventh nanosheet. A third power supply wiring is formed in a lower layer below the first transistor to the sixth transistor. The third power supply wiring extends in the first direction between the sixth nanosheet and the twelfth nanosheet and between the ninth nanosheet and the tenth nanosheet, and supplies the second voltage. A fourth power supply wiring is formed in a lower layer below the first transistor to the sixth transistor. The fourth power supply wiring extends in the first direction between the fifth nanosheet and the eleventh nanosheet and between the seventh nanosheet and the eighth nanosheet, and supplies the second voltage. The surface of the first side of the fifth nanosheet is exposed from the fifth gate wiring. The surface of the first side of the seventh nanosheet is exposed from the third gate wiring. The surface of the first side of the tenth nanosheet is exposed from the fourth gate wiring. The surface of the first side of the twelfth nanosheet is exposed from the sixth gate wiring. The surface of the second side of the sixth nanosheet is exposed from the sixth gate wiring. The surface of the second side of the eighth nanosheet is exposed from the third gate wiring. The surface of the second side of the ninth nanosheet is exposed from the fourth gate wiring. The surface of the second side of the eleventh nanosheet is exposed from the fifth gate wiring.

19. A semiconductor memory device includes a single-port SRAM cell. It is characterized in that: The single-port SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. One node of the first transistor is connected to a first power supply that supplies a first voltage, another node is connected to the first node, and the gate is connected to the second node. One node of the second transistor is connected to the first power supply, another node is connected to the second node, and the gate is connected to the first node. One node of the third transistor is connected to the first node, another node is connected to a second power supply that supplies a second voltage, the gate is connected to the second node, and the second voltage is different from the first voltage. One node of the fourth transistor is connected to the second node, another node is connected to the second power supply, and the gate is connected to the first node. One node of the fifth transistor is connected to a first bit line, another node is connected to the first node, and the gate is connected to a word line. One node of the sixth transistor is connected to the second bit line, another node is connected to the second node, and the gate is connected to the word line. The second bit line and the first bit line form a complementary bit line pair. The first transistor includes a first nanosheet and a first gate wiring, and the second transistor includes a second nanosheet and a second gate wiring. The first nanosheet and the second nanosheet extend in a first direction. The first gate wiring surrounds the outer periphery of the first nanosheet in a second direction and a third direction. The second gate wiring surrounds the outer periphery of the second nanosheet in the second direction and the third direction. The second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and the second direction. The third transistor includes a third gate wiring and a plurality of third nanosheets, the fourth transistor includes a fourth gate wiring and a plurality of fourth nanosheets, the fifth transistor includes a fifth gate wiring and a plurality of fifth nanosheets, and the sixth transistor includes a sixth gate wiring and a plurality of sixth nanosheets. The plurality of third nanosheets to the plurality of sixth nanosheets extend in the first direction. The third gate wiring surrounds the outer periphery of the plurality of third nanosheets in the second direction and the third direction. The fourth gate wiring surrounds the outer periphery of the plurality of fourth nanosheets in the second direction and the third direction. The fifth gate wiring surrounds the outer periphery of the plurality of fifth nanosheets in the second direction and the third direction. The sixth gate wiring surrounds the outer periphery of the plurality of sixth nanosheets in the second direction and the third direction. The first nanosheet, the plurality of third nanosheets, and the plurality of sixth nanosheets are arranged in the second direction in the order of the plurality of sixth nanosheets, the first nanosheet, and the plurality of third nanosheets. The second nanosheet, the plurality of fourth nanosheets, and the plurality of fifth nanosheets are arranged in the second direction in the order of the plurality of fourth nanosheets, the second nanosheet, and the plurality of fifth nanosheets. One side surface of the first nanosheet in the second direction exposes from the first gate wiring, and one side surface of the second nanosheet in the second direction exposes from the second gate wiring. One side surface of each of the plurality of third nanosheets in the second direction exposes from the third gate wiring. One side surface of each of the plurality of fourth nanosheets in the second direction exposes from the fourth gate wiring. One side surface of each of the plurality of fifth nanosheets in the second direction exposes from the fifth gate wiring. One side surface of each of the plurality of sixth nanosheets in the second direction exposes from the sixth gate wiring. A plurality of power supply wirings are formed in a lower layer below the first transistor to the sixth transistor. The plurality of power supply wirings extend in the first direction and supply the second voltage. Among the plurality of the third nanosheets, there is included a third nanosheet in which, when viewed from above, at least one power supply wiring among the plurality of power supply wirings is formed on a side opposite to the side from which the third gate wiring is exposed in the second direction. Among the plurality of the fourth nanosheets, there is included a fourth nanosheet in which, when viewed from above, at least one power supply wiring among the plurality of power supply wirings is formed on a side opposite to the side from which the fourth gate wiring is exposed in the second direction. Among the plurality of the fifth nanosheets, there is included a fifth nanosheet in which, when viewed from above, at least one power supply wiring among the plurality of power supply wirings is formed on a side opposite to the side from which the fifth gate wiring is exposed in the second direction. Among the plurality of the sixth nanosheets, there is included a sixth nanosheet in which, when viewed from above, at least one power supply wiring among the plurality of power supply wirings is formed on a side opposite to the side from which the sixth gate wiring is exposed in the second direction.

20. The semiconductor memory device according to claim 19, wherein: the first nanosheet, the second nanosheet, and the plurality of the third nanosheets to the plurality of the sixth nanosheets have the same width in the second direction.

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