Driving circuit, driving method and display panel

Abstract

The present application provides a driving circuit, a driving method and a display panel. The driving circuit includes: a driving transistor, a writing module, a compensation module, a light-emitting control module and a light-emitting device. The first gate of the driving transistor is electrically connected to the first node, the second gate of the driving transistor is electrically connected to the second node, the source of the driving transistor is electrically connected to the first power supply terminal, and the drain of the driving transistor is electrically connected to the third node; the writing module is connected to a data signal, a first control signal and a first scanning signal, and is electrically connected to the first node and the third node; the compensation module is connected to the second control signal and the second scanning signal, and is electrically connected to the first node, the second node and the third node; the light-emitting control module is connected to the second scanning signal, and is electrically connected to the third node and the fourth node; the anode of the light-emitting device is electrically connected to the fourth node, and the cathode of the light-emitting device is electrically connected to the second power supply terminal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit, a driving method and a display panel. Background Art

[0002] Organic light-emitting diodes have the characteristics of self-luminescence, high brightness, wide viewing angle, high contrast, flexibility, and low energy consumption. Therefore, they have received widespread attention and have gradually replaced traditional liquid crystal displays as a new generation of display methods. They are widely used in mobile phone screens, computer monitors, full-color TVs, etc. Organic light-emitting diode large-size TVs are currently the goal pursued by major panel manufacturers.

[0003] Each pixel of an organic light-emitting diode display includes: a driving transistor and at least one switching transistor, wherein the driving transistor is mainly used to control the organic light-emitting diode current, and the switching transistor is mainly used to drive the gate-source voltage of the driving transistor. The pixel brightness is proportional to the driving current. In an organic light-emitting diode display, the driving transistor varies due to process differences. Over time, the gate voltage of the driving transistor is subjected to different stresses, resulting in differences in the threshold voltages of the driving transistors in the panel. Since the pixel brightness is proportional to the driving current, differences in the threshold voltage of the driving transistor will also lead to differences in pixel brightness, causing the problem of uneven brightness of the display panel.

[0004] Therefore, how to provide a light-emitting driving circuit that can achieve internal compensation of the threshold voltage of the driving transistor to improve the uniformity of the brightness of the display panel. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a driving circuit, a driving method and a display panel, which can realize internal compensation of the threshold voltage of the driving transistor and improve the uniformity of the brightness of the display panel.

[0006] On the one hand, an embodiment of the present application provides a driving circuit, including: a driving transistor, a writing module, a compensation module, a light-emitting control module and a light-emitting device, wherein the first gate of the driving transistor is electrically connected to the first node, the second gate of the driving transistor is electrically connected to the second node, the source of the driving transistor is electrically connected to the first power supply terminal, and the drain of the driving transistor is electrically connected to the third node; the writing module is connected to a data signal, a first control signal and a first scanning signal, and is electrically connected to the first node and the third node, and the writing module is used to transmit the data signal to the first node under the control of the first scanning signal; the writing module is also used to transmit the first control signal to the third node under the control of the first scanning signal; the compensation module is connected to the second control signal. The first node, the second node and the third node are electrically connected to the first control signal and the second scan signal, and the compensation module is used to reset the first node, the third node and the second node under the control of the second control signal and the second scan signal, and the compensation module is also used to compensate for the threshold voltage of the driving transistor under the control of the second control signal and the second scan signal; the light-emitting control module is connected to the second scan signal and is electrically connected to the third node and the fourth node, and the light-emitting control module is used to control the conduction or disconnection between the third node and the fourth node under the control of the second scan signal; the anode of the light-emitting device is electrically connected to the fourth node, and the cathode of the light-emitting device is electrically connected to the second power supply terminal.

[0007] Optionally, in some embodiments of the present application, the write module includes a first transistor and a second transistor, the gate of the first transistor is connected to the first scan signal, the source of the first transistor is connected to the data signal, and the drain of the first transistor is electrically connected to the first node; the gate of the second transistor is connected to the first scan signal, the source of the second transistor is connected to the first control signal, and the drain of the second transistor is electrically connected to the third node.

[0008] Optionally, in some embodiments of the present application, the compensation module includes a third transistor, a fourth transistor, a first capacitor and a second capacitor, the gate of the third transistor is connected to the second scanning signal, the source of the third transistor is electrically connected to the first node, and the drain of the third transistor is electrically connected to the third node; the gate of the fourth transistor is connected to the second scanning signal, the source of the fourth transistor is connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node; one end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the third node; one end of the second capacitor is electrically connected to the second node, and the other end of the second capacitor is electrically connected to the third node.

[0009] Optionally, in some embodiments of the present application, the light emitting control module includes a fifth transistor, the gate of the fifth transistor is connected to the second scanning signal, the source of the fifth transistor is electrically connected to the third node, and the drain of the fifth transistor is electrically connected to the fourth node.

[0010] Optionally, in some embodiments of the present application, the driving transistor, the first transistor, the second transistor, the third transistor and the fourth transistor are N-type transistors, and the fifth transistor is a P-type transistor.

[0011] Optionally, in some embodiments of the present application, the light emitting control module further includes an inverter, an input end of the inverter is connected to the second scanning signal, and an output end of the inverter is electrically connected to the gate of the fifth transistor.

[0012] Optionally, in some embodiments of the present application, the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are transistors of the same type.

[0013] The present application also provides a driving method, which is used to drive the driving circuit as described above, wherein the driving circuit includes: a light-emitting device, a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a second capacitor, wherein the light-emitting device is connected in series to a light-emitting circuit formed by a first power supply terminal and a second power supply terminal; the first gate of the driving transistor is electrically connected to a first node, the second gate of the driving transistor is electrically connected to a second node, the source of the driving transistor is electrically connected to the first power supply terminal, and the drain of the driving transistor is electrically connected to a third node; the gate of the first transistor is connected to the first scanning signal, the source of the first transistor is connected to the data signal, and the first transistor is electrically connected to the data signal. The drain of the transistor is electrically connected to the first node; the gate of the second transistor is connected to the first scan signal, the source of the second transistor is connected to the first control signal, and the drain of the second transistor is electrically connected to the third node; the gate of the third transistor is connected to the second scan signal, the source of the third transistor is electrically connected to the first node, and the drain of the third transistor is electrically connected to the third node; the gate of the fourth transistor is connected to the second scan signal, the source of the fourth transistor is connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node; the gate of the fifth transistor is connected to the second scan signal, the source of the fifth transistor is electrically connected to the first node, and the drain of the third transistor is electrically connected to the third node. The first transistor and the second transistor are connected to the third node, the drain of the fifth transistor is electrically connected to the fourth node; one end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the third node; one end of the second capacitor is electrically connected to the second node, and the other end of the second capacitor is electrically connected to the third node; the driving method comprises: in a reset stage, the first transistor and the second transistor are turned on under the control of the first scan signal, the fifth transistor is turned on under the control of the second scan signal, the data signal is transmitted to the first node, the first control signal is output to the third node, and the first node and the third node maintain the same potential; the third transistor and the fourth transistor are turned on under the control of the second scan signal. In the threshold compensation stage, the third transistor and the fourth transistor remain turned on under the control of the second scan signal, the second control signal continues to be output to the second node, the first transistor and the second transistor are turned off under the control of the first scan signal, the fifth transistor is turned off under the control of the second scan signal, the first node and the third node maintain the same potential, and the first power supply end charges the third node until the voltage difference between the second node and the third node is equal to the threshold voltage of the driving transistor and the third node is turned off;In the writing phase, the first transistor and the second transistor are turned on under the control of the first scanning signal, the fifth transistor is turned on under the control of the second scanning signal, the data signal is output to the first node, and the first control signal is output to the third node; in the light emitting phase, the light emitting device emits light. ;

[0014] Optionally, in some embodiments of the present application, the reset phase includes a first reset phase and a second reset phase; in the first reset phase, the first transistor and the second transistor are turned on under the control of the first scan signal, the fifth transistor is turned on under the control of the second scan signal, the data signal is transmitted to the first node, the first control signal is output to the third node, the light-emitting device is reset, and the third transistor and the fourth transistor are turned off under the control of the second scan signal; in the second reset phase, the third transistor and the fourth transistor are turned on under the control of the second scan signal, the fifth transistor is turned off under the control of the second scan signal, the second control signal is output to the second node, the first node and the third node maintain the same potential, the first transistor and the second transistor are turned on under the control of the first scan signal, and the first control signal continues to be output to the third node.

[0015] On the other hand, the embodiment of the present application further provides a display panel, comprising a plurality of pixel units arranged in an array, each of the pixel units comprising the driving circuit as described above.

[0016] In the driving circuit, driving method and display panel provided in the embodiment of the present application, a driving transistor, a writing module, a compensation module, a light-emitting control module and a light-emitting device are included. The driving circuit provided in the present application internally compensates the threshold voltage of the driving transistor through the compensation module, and resets the first node, the second node and the third node, so as to avoid the threshold voltage drift of the driving transistor affecting the brightness of the light-emitting device, thereby improving the uniformity of the brightness displayed by the display panel. At the same time, it is beneficial to reduce the use of scanning signal lines and improve the resolution of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the structure of a driving circuit provided in an embodiment of the present application;

[0019] Figure 2 A circuit diagram of a driving circuit provided in the first embodiment of the present application;

[0020] Figure 3 is a timing diagram of a driving circuit provided in an embodiment of the present application;

[0021] Figure 4 is a circuit diagram of a driving circuit provided in the second embodiment of the present application;

[0022] Figure 5 A schematic diagram of a driving method according to an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of the structure of a backlight module provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0026] The transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiment of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the accompanying drawings, the middle end of the switching transistor is specified as the gate, the signal input end is the source, and the output end is the drain. In addition, the transistors used in the embodiments of the present application are N-type transistors and P-type transistors, wherein the N-type transistor is turned on when the gate is at a high potential and is cut off when the gate is at a low potential, and the P-type transistor is turned on when the gate is at a low potential and is cut off when the gate is at a high potential. In the embodiment of the present application, the light-emitting device D can be a micro light-emitting diode (MicroLight EmittingDiode, Micro-LED) or a mini light-emitting diode (Mini Light EmittingDiode, Mini-LED).

[0027] See also Figure 1 , Figure 1 Schematic diagram of the structure of the driving circuit provided in the embodiment of the present application. Figure 1As shown, the driving circuit provided in the embodiment of the present application includes a light emitting device D, a driving transistor T0, a writing module 101, a compensation module 102 and a light emitting control module 103. It should be noted that the light emitting device D can be a mini light emitting diode, a micro light emitting diode or an organic light emitting diode.

[0028] The first gate of the driving transistor T0 is electrically connected to the first node G, the second gate of the driving transistor T0 is electrically connected to the second node P, the source of the driving transistor T0 is electrically connected to the first power supply terminal VDD, and the drain of the driving transistor T0 is electrically connected to the third node S. The writing module 101 is connected to the data signal DATA, the first control signal VINI and the first scanning signal SCAN, and is electrically connected to the first node G and the third node S. The compensation module 102 is connected to the second control signal VREF and the second scanning signal SENSE, and is electrically connected to the first node G, the second node P and the third node S. The light control module 103 is connected to the second scanning signal SENSE, and is electrically connected to the third node S and the fourth node N. The anode of the light emitting device D is electrically connected to the fourth node N, and the cathode of the light emitting device D is electrically connected to the second power supply terminal VSS. Specifically, the first power supply terminal VDD and the second power supply terminal VSS are both DC voltage sources.

[0029] Specifically, the driving transistor T0 is used to control the current flowing through the driving circuit. The writing module 101 is used to transmit the data signal DATA to the first node G under the control of the first scanning signal SCAN; the writing module 101 is also used to transmit the first control signal VINI to the third node S under the control of the first scanning signal SCAN. The compensation module 102 is used to reset the first node G and the first control signal VINI end under the control of the second control signal VREF and the second scanning signal SENSE. The compensation module 102 is also used to compensate the threshold voltage of the driving transistor T0 under the control of the second control signal VREF and the second scanning signal SENSE. The light emitting control module 103 is used to control the conduction or disconnection between the third node S and the fourth node N based on the second scanning signal SENSE.

[0030] The potential of the data signal is between 0 volts and 10 volts, the potential of the first scan signal is between -10 volts and 20 volts, the potential of the second scan signal is between -10 volts and 20 volts, the potential of the first power supply terminal is between 15 volts and 20 volts, the potential of the first control signal is between 1 volt and 2 volts, preferably, the potential of the first control signal is 1.5 volts; the potential of the second control signal is between 5 volts and 10 volts, preferably, the potential of the second control signal is 6 volts. The specific potential value can be adjusted by those skilled in the art as needed, and this application does not limit it here.

[0031] The driving circuit provided in the embodiment of the present application can internally compensate the threshold voltage of the driving transistor T0 through the compensation module 102, and reset the first node G, the second node P and the third node S, so as to avoid the threshold voltage of the driving transistor T0 affecting the brightness of the light-emitting device D, thereby improving the uniformity of the brightness displayed by the display panel. At the same time, it is beneficial to reduce the use of scanning signal lines and improve the resolution of the display panel.

[0032] See also Figure 2 and Figure 1 , Figure 2 FIG. 1 is a circuit diagram of a driving circuit provided in the first embodiment of the present application. Figure 1 and Figure 2 As shown, the driving circuit provided in the embodiment of the present application includes: a driving transistor T0, a writing module 101, a compensation module 102, a light-emitting control module 103 and a light-emitting device D. Among them, the writing module 101 includes a first transistor T1 and a second transistor T2; the compensation module 102 includes a third transistor T3, a fourth transistor T4, a first capacitor C1 and a second capacitor C2; the light-emitting control module 103 includes a fifth transistor T5.

[0033] Among them, the driving transistor T0 is used to control the current flowing through the driving circuit, the first gate of the driving transistor T0 is electrically connected to the first node G, the second gate of the driving transistor T0 is electrically connected to the second node P, the source of the driving transistor T0 is electrically connected to the first power supply terminal VDD, and the drain of the driving transistor T0 is electrically connected to the third node S.

[0034] Among them, the gate of the first transistor T1 is connected to the first scan signal SCAN, the source of the first transistor T1 is connected to the data signal DATA, and the drain of the first transistor T1 is electrically connected to the first node G; the gate of the second transistor T2 is connected to the first scan signal SCAN, the source of the second transistor T2 is connected to the first control signal VINI, and the drain of the second transistor T2 is electrically connected to the third node S.

[0035] Among them, the gate of the third transistor T3 is connected to the second scanning signal SENSE, the source of the third transistor T3 is electrically connected to the first node G, and the drain of the third transistor T3 is electrically connected to the third node S; the gate of the fourth transistor T4 is connected to the second scanning signal SENSE, the source of the fourth transistor T4 is connected to the second control signal VREF, and the drain of the fourth transistor T4 is electrically connected to the second node P; one end of the first capacitor C1 is electrically connected to the first node G, and the other end of the first capacitor C1 is electrically connected to the third node S; one end of the second capacitor C2 is electrically connected to the second node P, and the other end of the second capacitor C2 is electrically connected to the third node S.

[0036] The gate of the fifth transistor T5 is connected to the second scan signal SENSE, the source of the fifth transistor T5 is electrically connected to the third node S, and the drain of the fifth transistor T5 is electrically connected to the fourth node N.

[0037] The anode of the light emitting device D is electrically connected to the fourth node N, and the cathode of the light emitting device D is electrically connected to the second power supply terminal VSS.

[0038] It should be noted that both the first power signal and the second power signal are used to output a preset voltage value. In addition, in the embodiment of the present application, the potential of the first power signal is greater than the potential of the second power signal. Specifically, the potential of the second power signal can be the potential of the ground terminal. Of course, it can be understood that the potential of the second power signal can also be other.

[0039] It should be noted that the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be one or more of a low-temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, or an amorphous silicon thin film transistor. Preferably, the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all low-temperature polysilicon thin film transistors.

[0040] In the embodiment of the present application, the driving transistor T0 , the first transistor T1 , the second transistor T2 , the third transistor T3 , and the fourth transistor T4 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0041] See also Figure 3 , Figure 3 is a timing diagram of the driving circuit provided in the embodiment of the present application. Figure 3 As shown, the combination of the first scanning signal SCAN and the second scanning signal SENSE corresponds to the reset stage t1, the threshold compensation stage t2, the writing stage t3 and the light-emitting stage t4 in sequence; that is, within one frame time, the driving control timing of the driving circuit provided in the embodiment of the present application includes the reset stage t1, the threshold compensation stage t2, the writing stage t3 and the light-emitting stage t4. It should be noted that the light-emitting device D emits light in the light-emitting stage t4.

[0042] Specifically, Figure 2 and Figure 3 As shown, in the reset phase t1 , the first scan signal SCAN is at a high level, and the second scan signal SENSE is at a low level.

[0043] The first transistor T1 and the second transistor T2 are turned on under the high potential control of the first scan signal SCAN. The second scan signal SENSE is at a low potential, and the fifth transistor T5 is turned on under the low potential control of the second scan signal SENSE. At this time, the power supply voltage provided by the first power supply terminal VDD resets the first node G and the third node S through the first transistor T1 and the second transistor T2.

[0044] Then, the second scan signal SENSE turns to a high level, and the first scan signal SCAN also turns to a high level.

[0045] The third transistor T3 and the fourth transistor T4 are turned on under the high potential control of the second scanning signal SENSE. The fifth transistor T5 is turned off under the high potential control of the second scanning signal SENSE. At this time, the control voltage V provided by the second control signal VREF ref The second node P is reset by the third transistor T3 and the fourth transistor T4.

[0046] In the threshold compensation stage t2 , the first scan signal SCAN is at a low level, and the second scan signal SENSE is at a high level.

[0047] The third transistor T3 and the fourth transistor T4 are turned on under the control of the high potential of the second scanning signal SENSE. At this time, the driving transistor T0 is driven by the control voltage V provided by the second control signal terminal VREF. ref Under the control, the drain potential of the driving transistor T0 is raised or lowered until the current of the driving transistor T0 is zero. At this time, the potential value V th Stored on the second capacitor C2, that is:

[0048] V th =V th0 -a*(V ref -V s )=0

[0049] Among them, V th0 is the initial potential value of the driving transistor T0, V s is the drain potential of the driving transistor T0 after the threshold compensation phase t2 ends, V ref is to adjust the voltage value, and a is a parameter related to the film structure of the driving transistor T0.

[0050] In the writing phase t3 , the first scanning signal SCAN is at a high level, and the second scanning signal SENSE is at a low level.

[0051] The first transistor T1 and the second transistor T2 are turned on under the control of the high potential of the first scan signal SCAN. The second scan signal SENSE is at a low potential, and the fifth transistor T5 is turned on under the control of the low potential of the second scan signal SENSE.

[0052] In the light emitting stage t4 , the first scanning signal SCAN is at a low level, and the second scanning signal SENSE is at a low level.

[0053] The fifth transistor T5 is turned on under the control of the low potential of the second scanning signal SENSE. The driving transistor T0 maintains the turned-on state due to the potential stored in the first capacitor C1 and the second capacitor C2. The light emitting device D emits light.

[0054] As a specific implementation of this application, please refer to Figure 4 , Figure 4 is a circuit diagram of a driving circuit provided in the second embodiment of the present application. Figure 4 As shown, the light control module 103 further includes an inverter, an input end of the inverter is connected to the second scan signal SENSE, and an output end of the inverter is electrically connected to the gate of the fifth transistor T5.

[0055] The first gate of the driving transistor T0 is electrically connected to the first node G, the second gate of the driving transistor T0 is electrically connected to the second node P, the source of the driving transistor T0 is electrically connected to the first power supply terminal VDD, and the drain of the driving transistor T0 is electrically connected to the third node S. The gate of the first transistor T1 is connected to the first scan signal SCAN, the source of the first transistor T1 is connected to the data signal DATA, and the drain of the first transistor T1 is electrically connected to the first node G; the gate of the second transistor T2 is connected to the first scan signal SCAN, the source of the second transistor T2 is connected to the first control signal VINI, and the drain of the second transistor T2 is electrically connected to the third node S. The gate of the third transistor T3 is connected to the second scan signal SENSE, the source of the third transistor T3 is electrically connected to the first node G, and the drain of the third transistor T3 is electrically connected to the third node S; the gate of the fourth transistor T4 is connected to the second scan signal SENSE, the source of the fourth transistor T4 is connected to the second control signal VREF, and the drain of the fourth transistor T4 is electrically connected to the second node P; one end of the first capacitor C1 is electrically connected to the first node G, and the other end of the first capacitor C1 is electrically connected to the third node S; one end of the second capacitor C2 is electrically connected to the second node P, and the other end of the second capacitor C2 is electrically connected to the third node S. The gate of the fifth transistor T5 is connected to the second scan signal SENSE, the source of the fifth transistor T5 is electrically connected to the third node S, and the drain of the fifth transistor T5 is electrically connected to the fourth node N. The anode of the light emitting device D is electrically connected to the fourth node N, and the cathode of the light emitting device D is electrically connected to the second power supply terminal VSS.

[0056] Among them, the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are transistors of the same type. Specifically, the transistors in the driving circuit provided in the embodiment of the present application are all P-type transistors or N-type transistors, which is conducive to avoiding the influence of the differences between different types of transistors on the driving circuit. Preferably, the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all N-type transistors. Since the inverter in this embodiment has the same effect as the P-type transistor in the previous embodiment, the timing of this embodiment is the same as that of the previous embodiment.

[0057] It should be noted that both the first power signal and the second power signal are used to output a preset voltage value. In addition, in the embodiment of the present application, the potential of the first power signal is greater than the potential of the second power signal. Specifically, the potential of the second power signal can be the potential of the ground terminal. Of course, it can be understood that the potential of the second power signal can also be other.

[0058] It should be noted that the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be one or more of a low-temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, or an amorphous silicon thin film transistor. Preferably, the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all low-temperature polysilicon thin film transistors.

[0059] See also Figure 5 , Figure 5 The present application also provides a driving method for the above-mentioned driving circuit, and the driving method includes:

[0060] S10, reset stage, the first transistor and the second transistor are turned on under the control of the first scan signal, the fifth transistor is turned on under the control of the second scan signal, the data signal is transmitted to the first node, the first control signal is output to the third node, the first node and the third node maintain the same potential; the third transistor and the fourth transistor are turned on under the control of the second scan signal, the fifth transistor is turned off under the control of the second scan signal, and the second control signal is output to the second node.

[0061] S20, threshold compensation stage, the third transistor and the fourth transistor remain turned on under the control of the second scanning signal, the second control signal continues to be output to the second node, the first transistor and the second transistor are turned off under the control of the first scanning signal, the fifth transistor is turned off under the control of the second scanning signal, the first node and the third node maintain the same potential, the first power supply end charges the third node until the voltage difference between the second node and the third node is equal to the threshold voltage of the driving transistor.

[0062] S30, writing stage, the first transistor and the second transistor are turned on under the control of the first scanning signal, the fifth transistor is turned on under the control of the second scanning signal, the data signal is output to the first node, and the first control signal is output to the third node.

[0063] S40, light emitting stage, the light emitting device emits light.

[0064] Specifically, the reset stage S10 includes a first reset stage and a second reset stage;

[0065] In the first reset stage, the first transistor and the second transistor are turned on under the control of the first scan signal, the fifth transistor is turned on under the control of the second scan signal, the data signal is transmitted to the first node, the first control signal is output to the third node, the light emitting device is reset, and the third transistor and the fourth transistor are turned off under the control of the second scan signal;

[0066] In the second reset phase, the third transistor and the fourth transistor are turned on under the control of the second scan signal, the fifth transistor is turned off under the control of the second scan signal, the second control signal is output to the second node, the first node and the third node maintain the same potential, the first transistor and the second transistor are turned on under the control of the first scan signal, and the first control signal continues to be output to the third node.

[0067] See also Figure 6 , Figure 6 A schematic diagram of the structure of a backlight module provided in an embodiment of the present application. The embodiment of the present application also provides a backlight module 100, which includes a data line 20, a first scan line 30, a second scan line 40, a first control signal line 50, a second control signal line 60 and the above drive circuit 10. Among them, the data line 20 is used to provide a data signal DATA. The first scan line 30 is used to provide a first scan signal SCAN. The second scan line 40 is used to provide a second scan signal SENSE. The drive circuit 10 is connected to the data line 20, the first scan line 30, the second scan line 40, the first control signal line 50, and the second control signal line 60. Among them, the light-emitting device D can be Mini-LED or Micro-LED. The drive circuit 10 can be specifically referred to the above description of the drive circuit, which will not be repeated here.

[0068] See also Figure 7 , Figure 7 The present invention also provides a display panel 200, including a plurality of pixel units 210 arranged in an array, each pixel unit 210 including the above driving circuit 10, wherein the light emitting device D may be a Mini-LED or a Micro-LED. For details, please refer to the above description of the driving circuit 10, which will not be described in detail here.

[0069] The display panel can be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0070] In the driving circuit, driving method and display panel provided in the embodiment of the present application, a light emitting device D, a driving transistor T0, a writing module 101, a compensation module 102 and a light emitting control module 103 are included. The compensation module 102 can compensate the threshold voltage of the driving transistor T0 and reset the first node G, the second node P and the third node S, so as to compensate the threshold voltage of the driving transistor T0, and at the same time, it is beneficial to reduce the use of scanning signal lines and improve the resolution of the display panel.

[0071] The above is a detailed introduction to a driving circuit, a driving method and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A driving method for driving a driving circuit, It is characterized in that The driving circuit includes: a light-emitting device, a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a second capacitor, wherein the light-emitting device is connected in series to a light-emitting circuit formed by a first power supply terminal and a second power supply terminal; the first gate of the driving transistor is electrically connected to a first node, the second gate of the driving transistor is electrically connected to a second node, the source of the driving transistor is electrically connected to the first power supply terminal, and the drain of the driving transistor is electrically connected to a third node; the gate of the first transistor is connected to a first scanning signal, the source of the first transistor is connected to a data signal, and the drain of the first transistor is electrically connected to the first node; the gate of the second transistor is connected to the first scanning signal, the source of the second transistor is connected to a first control signal, and the drain of the second transistor is electrically connected to at the third node; the gate of the third transistor is connected to the second scan signal, the source of the third transistor is electrically connected to the first node, and the drain of the third transistor is electrically connected to the third node; the gate of the fourth transistor is connected to the second scan signal, the source of the fourth transistor is connected to the second control signal, and the drain of the fourth transistor is electrically connected to the second node; the gate of the fifth transistor is connected to the second scan signal, the source of the fifth transistor is electrically connected to the third node, and the drain of the fifth transistor is electrically connected to the fourth node; one end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the third node; one end of the second capacitor is electrically connected to the second node, and the other end of the second capacitor is electrically connected to the third node; the driving method includes: In a reset phase, the first transistor and the second transistor are turned on under the control of the first scan signal, the fifth transistor is turned on under the control of the second scan signal, the data signal is transmitted to the first node, the first control signal is output to the third node, and the first node and the third node maintain the same potential; the third transistor and the fourth transistor are turned on under the control of the second scan signal, the fifth transistor is turned off under the control of the second scan signal, and the second control signal is output to the second node; In the threshold compensation stage, the third transistor and the fourth transistor remain turned on under the control of the second scan signal, the second control signal continues to be output to the second node, the first transistor and the second transistor are turned off under the control of the first scan signal, the fifth transistor is turned off under the control of the second scan signal, the first node and the third node maintain the same potential, and the first power supply end charges the third node until the voltage difference between the second node and the third node is equal to the threshold voltage of the driving transistor, and then the transistor is turned off; In the writing phase, the first transistor and the second transistor are turned on under the control of the first scanning signal, the fifth transistor is turned on under the control of the second scanning signal, the data signal is output to the first node, and the first control signal is output to the third node; In the light emitting stage, the light emitting device emits light.

2. The driving method according to claim 1, It is characterized in that The reset stage includes a first reset stage and a second reset stage; In the first reset stage, the first transistor and the second transistor are turned on under the control of the first scan signal, the fifth transistor is turned on under the control of the second scan signal, the data signal is transmitted to the first node, the first control signal is output to the third node, the light emitting device is reset, and the third transistor and the fourth transistor are turned off under the control of the second scan signal; In the second reset phase, the third transistor and the fourth transistor are turned on under the control of the second scan signal, the fifth transistor is turned off under the control of the second scan signal, the second control signal is output to the second node, the first node and the third node maintain the same potential, the first transistor and the second transistor are turned on under the control of the first scan signal, and the first control signal continues to be output to the third node.

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