Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device comprises: a multi-layer substrate, which is formed with a wiring pattern and a grounding pattern; a plurality of semiconductor elements, which are mounted on the multi-layer substrate; an insulating seal, which is arranged on the multi-layer substrate and covers the plurality of semiconductor elements; a metal film, which is arranged on the insulating seal; an in-groove metal, which is arranged in contact with a plurality of grooves extending from the upper end of the side surface of the insulating seal to the lower end of the side surface of the multi-layer substrate; and an in-hole metal, which is arranged on the inner wall of a hole in contact with the metal film and the grounding pattern, and the hole passes through the insulating seal to reach the multi-layer substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] For example, in semiconductor devices operating in high frequency bands, in order to suppress interference caused by unnecessary radio wave radiation from the package, it is effective to use a package structure covered by a conductive shielding film, etc., as miniaturization and high density are achieved. In addition, as the semiconductor package product itself is miniaturized and the performance of the semiconductor element installed in the package is improved, it is possible that cavity resonance in the package or interference between semiconductors caused by electromagnetic shielding may occur easily.

[0003] Patent document 1 discloses a high-frequency integrated circuit device, in which an insulating resin is formed on a substrate on which a plurality of high-frequency components are mounted, separation grooves are provided from the upper surface in portions between the high-frequency components of the insulating resin, and a metal film is formed on the upper surface and side surfaces including the separation grooves.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2005-340656

[0005] In the structure of Patent Document 1, the electromagnetic shielding layer is formed after the package is singulated, so it is necessary to perform a shielding film forming step on the singulated package. In this case, the thickness of the electromagnetic shielding layer varies between package products. Summary of the invention

[0006] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device suitable for improving the quality of a semiconductor device having an electromagnetic shielding function and a method for manufacturing the semiconductor device.

[0007] The semiconductor device disclosed in the present application is characterized in that it comprises: a multi-layer substrate, on which a wiring pattern and a grounding pattern are formed; a plurality of semiconductor elements mounted on the multi-layer substrate; an insulating sealant, which is arranged on the multi-layer substrate and covers the plurality of semiconductor elements; a metal film, which is arranged on the insulating sealant; metal in the groove, which is arranged in contact with a plurality of grooves extending from the upper end of the side surface of the insulating sealant to the lower end of the side surface of the multi-layer substrate; and metal in the hole, which is arranged on the inner wall of the hole in contact with the metal film and the grounding pattern, and the hole passes through the insulating sealant to reach the multi-layer substrate.

[0008] The manufacturing method of the semiconductor device disclosed in the present application is characterized in that it comprises: mounting a plurality of semiconductor elements on a multilayer substrate having a wiring pattern and a grounding pattern, forming an insulating sealant covering the plurality of semiconductor elements on the multilayer substrate, forming a plurality of separation through holes that penetrate the insulating sealant and the multilayer substrate in a manner that surrounds the plurality of semiconductor elements when viewed from above, forming a hole that penetrates the insulating sealant and reaches the multilayer substrate at a position surrounded by the plurality of separation through holes when viewed from above, forming: a metal film on the insulating sealant, a metal portion that is arranged in the plurality of separation through holes and connected to the metal film and the grounding pattern, and an in-hole metal that is arranged on the inner wall of the hole and connected to the metal film and the grounding pattern, separating the multilayer substrate and the insulating sealant along the plurality of separation through holes to monolithically form the semiconductor device.

[0009] Other features of the present disclosure will be set forth below.

[0010] According to the present disclosure, since metal for electromagnetic shielding, suppression of cavity resonance and interference between elements is formed before the semiconductor device is singulated, a semiconductor device suitable for improving quality and a method for manufacturing the semiconductor device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a perspective view of the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a perspective view of a semiconductor device that visualizes its structure.

[0013] Figure 3 It is a flow chart.

[0014] Figure 4 This is a diagram showing the mounting of a semiconductor element.

[0015] Figure 5 It is a figure which shows the formation of a hole and a through-hole for separation.

[0016] Figure 6 Yes Figure 5 An internal visualization of the diagram.

[0017] Figure 7 is a cross-sectional view of a semiconductor device before singulation.

[0018] Figure 8 is a cross-sectional view of a semiconductor device before singulation.

[0019] Fig. 9 is a cross-sectional view of a semiconductor device according to a modified example.

[0020] Fig.10This is a perspective view of a semiconductor device according to a second embodiment.

[0021] Fig.11 is a cross-sectional view of a semiconductor device before singulation.

[0022] Fig.12 is a cross-sectional view of a semiconductor device before singulation.

[0023] Fig.13 is a cross-sectional view of a semiconductor device according to a modified example. DETAILED DESCRIPTION

[0024] A semiconductor device and a method for manufacturing a semiconductor device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and duplicate descriptions may be omitted.

[0025] Implementation method 1.

[0026] Figure 1 1 is a perspective view of a semiconductor device according to Embodiment 1. The semiconductor device 10 includes a multilayer substrate 12 on which a wiring pattern and a grounding pattern are formed. The wiring pattern or the grounding pattern is formed on the surface, the back surface, and the inside of the multilayer substrate 12. The multilayer substrate 12 may be, for example, a ceramic substrate or a glass epoxy substrate.

[0027] A plurality of semiconductor elements are mounted on the multilayer substrate 12. According to one example, the plurality of semiconductor elements are semiconductor wafers. An insulating sealant 13 covering the plurality of semiconductor elements is provided on the multilayer substrate 12. The insulating sealant 13 is, for example, a molded resin. A metal film 14A is provided on the insulating sealant 13.

[0028] A plurality of grooves 16 are formed on the side surface of the insulating seal 13 and the side surface of the multilayer substrate 12, extending from the upper end of the insulating seal 13 to the lower end of the multilayer substrate 12. As a result, the side surface of the insulating seal 13 and the side surface of the multilayer substrate 12 include a plurality of grooves 16 and a flat surface located between the grooves. In-groove metal 14B is provided in the plurality of grooves 16. As a result of the formation of the in-groove metal 14B in the groove 16, the in-groove metal 14B extends from the upper end of the side surface of the insulating seal 13 to the lower end of the side surface of the multilayer substrate 12. Therefore, the in-groove metal 14B and the insulating seal 13 are exposed on the side surface of the semiconductor device 10. The in-groove metal 14B is in contact with the metal film 14A and the grounding pattern of the multilayer substrate 12.

[0029] The semiconductor device 10 is provided with a hole 15 that penetrates the insulating seal 13 and reaches the multi-layer substrate 12. The hole 15 may penetrate the multi-layer substrate 12, or may be formed to the middle of the multi-layer substrate 12 without penetrating the multi-layer substrate 12. A hole metal 14E is formed on the inner wall of the hole 15. The hole metal 14E is in contact with the metal film 14A and the grounding pattern of the multi-layer substrate 12.

[0030] As the material of the metal film 14A, the in-groove metal 14B, and the in-hole metal 14E, for example, a low-resistance metal such as gold or nickel can be used.

[0031] Figure 2 Yes means Figure 1 A perspective view of the internal structure of the semiconductor device 10. Figure 2 in, omit Figure 1 The metal film 14A, the metal in the groove 14B, and the metal in the hole 14E are shown, and only the outer shape of the insulating seal 13 is shown, so that the interior of the semiconductor device can be visualized. A plurality of semiconductor elements 22 are mounted on the multilayer substrate 12. According to one example, the plurality of semiconductor elements 22 include a first semiconductor element 22a and a second semiconductor element 22b. According to another example, three or more semiconductor elements can be mounted on the multilayer substrate 12.

[0032] The multi-layer substrate 12 includes a wiring pattern 32 on the upper surface side. The wires 18 connect the plurality of semiconductor elements 22 and the wiring pattern 32 of the multi-layer substrate 12 .

[0033] Figure 3 1 is a flowchart showing a method for manufacturing a semiconductor device according to Embodiment 1. The method for manufacturing a semiconductor device will be described according to this flowchart. First, in step S1, a plurality of semiconductor elements are mounted on a multilayer substrate. Figure 4 1 is a top view of a multilayer substrate on which semiconductor elements are mounted. A first semiconductor element 22a and a second semiconductor element 22b are mounted on a multilayer substrate 12. The first semiconductor element 22a and the second semiconductor element 22b are connected to a wiring pattern 32 or a connection terminal 19 via a wire 18. The connection terminal 19 is a pattern for transmitting input and output power of the semiconductor device.

[0034] exist Figure 4 The dotted line in FIG. 2 indicates the separation position 20. The separation position 20 is a virtual line that will serve as a separation position when the multilayer substrate is separated in the future to separate the semiconductor device into individual pieces. Figure 4 4 semiconductor devices before segmentation are shown in FIG.

[0035] Next, the process proceeds to step S2. In step S2, the insulating sealing member 13 is formed on the multilayer substrate 12 to cover the plurality of semiconductor elements 22 and the wires 18. According to one example, the insulating sealing member 13 is formed on the entire upper surface of the multilayer substrate 12.

[0036] Next, the process proceeds to step S3. In step S3, a plurality of separation through holes 21 and holes 15 are formed. Figure 5 1 is a top view of a semiconductor device having isolation through holes 21 and holes 15 formed therein. A plurality of isolation through holes 21 are formed along the isolation position 20. The plurality of isolation through holes 21 are formed to surround a plurality of semiconductor elements when viewed from above. The plurality of isolation through holes 21 penetrate the insulating sealing member 13 and the multilayer substrate 12.

[0037] The hole 15 is formed at a position surrounded by the plurality of separation through holes 21 in a plan view. One hole 15 may be formed in a region surrounded by the plurality of separation through holes 21 formed in an annular shape, or a plurality of holes 15 may be formed. Figure 5 In the example of FIG. 1 , two holes 15 are formed in a region surrounded by a plurality of isolation through holes 21 formed in an annular shape. The holes 15 penetrate the insulating seal 13 and reach the multilayer substrate 12. In this example, the holes 15 penetrate the insulating seal 13 and the multilayer substrate 12.

[0038] Figure 6 Yes Figure 5 The insulating seal 13 is transparent in the figure. At least a part of the hole 15 is located between the plurality of semiconductor elements when viewed from above. In this example, there are two holes 15 between the first semiconductor element 22a and the second semiconductor element 22b. According to other examples, the hole 15 can be formed at any position surrounded by the ring-shaped separation through hole 21.

[0039] As a method for forming the hole 15 and the separation through hole 21, a mechanical method, laser processing or a mold can be used. According to an example, the diameter of the separation through hole 21 can be made consistent with that of the hole 15. In this case, the diameters of all the separation through holes 21 and all the holes 15 are the same. In this way, when a mechanical method or a mold is used, all the separation through holes 21 and all the holes 15 can be formed with one processing tool, and when laser processing is used, all the separation through holes 21 and all the holes 15 can be formed at once with a single process.

[0040] Next, the process proceeds to step S4 . In step S4 , metal is formed on the upper surface of the insulating sealing member 13 , in the isolation through-hole 21 , and in the hole 15 . Figure 7 , 8 is a cross-sectional view showing an example of a semiconductor device after metal formation. Figure 71 is a cross-sectional view of the semiconductor device including the position of the isolation through-hole 21 . Figure 7 is with Figure 6 A cross-sectional view corresponding to the position of line AA′.

[0041] Figure 7 The multilayer substrate 12 in the example includes an insulating layer 34, a wiring pattern 32, a back ground pattern 17, and an internal ground pattern 30. In this example, the back ground pattern 17 exposed on the back surface of the multilayer substrate 12 and the internal ground pattern 30 provided inside the multilayer substrate 12 are provided as ground patterns. According to other examples, three or more ground patterns can be provided on different layers of the multilayer substrate.

[0042] exist Figure 7 2 shows the metal film 14A on the insulating seal 13 and the metal portion 14B′ provided in the isolation through hole 21. The metal portion 14B′ is in contact with the metal film 14A, the back surface ground pattern 17, and the internal ground pattern 30.

[0043] Figure 8 It is a cross-sectional view of the semiconductor device including the position of the hole 15 . Figure 8 is with Figure 6 A cross-sectional view of the position corresponding to the BB′ line of FIG. 15 is formed with a hole metal 14E on the inner wall of the hole 15. The hole 15 passes through the insulating seal 13 and the multilayer substrate 12. The hole metal 14E is connected to the metal film 14A, the back grounding pattern 17, and the internal grounding pattern 30.

[0044] The metal film 14A, the metal portion 14B' and the in-hole metal 14E are formed at once by, for example, vapor deposition or plating. Such a collective formation contributes to the simplification of the process.

[0045] Next, the process proceeds to step S5. In step S5, the multilayer substrate 12 and the insulating sealing member 13 are separated along the plurality of separation through holes 21 to separate the semiconductor device into individual pieces. Figure 1 The groove 16 shown in FIG. 1 is formed on the inner wall of the isolation through hole 21. Figure 1 The metal 14B in the groove is shown. Figure 1 , 2 The semiconductor device shown.

[0046] The metal in the groove 14B functions as an electromagnetic shield for the semiconductor device. The spacing of the metal in the groove 14B contributes to the performance of the electromagnetic shield. In order to ensure the electromagnetic shielding property of the semiconductor device 10, the spacing of the isolation through-holes 21 can be set to be less than 1 / 4 wavelength of the high frequency band in which the semiconductor device 10 operates.

[0047] There is a situation where a high-order harmonic power such as a 2-fold wave, a 3-fold wave, or an n-fold wave (n is an integer) is generated from the semiconductor element 22. Therefore, the spacing of the metal 14B in the slot can be determined in a manner that not only shields the fundamental power but also shields the high-order harmonic power. As an insulating seal 13, for example, a molding material with a relative dielectric constant Er of 5 is used, and the 1 / 4 wavelength when the operating frequency band of the semiconductor device is 10GHz is 4mm. In order to improve the shielding of high-order harmonic power, the spacing between two adjacent slots of the plurality of slots 16 can be set to 0.6mm to 1mm. In this case, the spacing of the metal 14B in the slot is also 0.6mm to 1mm. In addition, when the processing accuracy of the separation through hole 21 is approximately 0.3mm, the position of a certain slot 16 is offset by a maximum of 0.3mm from the preset position, and the position of the slot 16 adjacent to the slot is also offset by a maximum of 0.3mm from the preset position. Therefore, as described above, by setting the spacing of the plurality of slots 16 to 0.6mm to 1mm, it is possible to avoid the two slots from being connected, and the spacing of the slots can be reduced. By reducing the intervals between the metals 14B in the slots, it is possible to improve the shielding properties of harmonic power.

[0048] As described above, although the position of providing the grounding pattern is arbitrary, for example, the grounding pattern can be formed on the surface, back surface, and inside of the multilayer substrate 12. By exposing the grounding pattern on the inner wall of the separation through hole 21, the metal portion 14B' is formed only in the separation through hole 21, and the metal portion 14B' can be easily connected to the grounding pattern.

[0049] In the above-mentioned method for manufacturing a semiconductor device, since the metal film 14A, the metal portion 14B′, and the in-hole metal 14E are formed before the semiconductor device is separated into single pieces, compared with the case where these are formed after the semiconductor device is singulated, it is suitable for reducing the manufacturing cost caused by the reduction in the number of steps and reducing the deviation of the electromagnetic shielding film.

[0050] The metal in the hole 14E is provided to suppress malfunction caused by resonance in the cavity of the semiconductor device 10. By setting the position of the hole 15 to a position between the semiconductor wafers 6 when viewed from above, interference between semiconductor elements can be suppressed. In other words, at least a portion of the metal in the hole 14E is located between the first semiconductor element 22a and the second semiconductor element 22b when viewed from above to suppress interference between semiconductor elements. According to other examples, the hole 15 can be set at an arbitrary position. The number of holes 15 is not particularly limited. In the case of forming a plurality of holes 15, considering the processing accuracy of the holes 15, the two holes 15 should not be connected. The processing deviation of the hole 15 is, for example, 0.1 mm. In order to suppress resonance in the cavity, the radius of the hole 15 can be increased or the number of holes 15 can be increased.

[0051] Fig. 9 4 is a cross-sectional view of a semiconductor device showing an example of a metal in a hole according to a modification. Fig. 9 The hole 15 shown penetrates the insulating seal 13 and extends to the middle of the multi-layer substrate 12, and thus does not penetrate the multi-layer substrate 12. The hole 15 is provided in such a manner that the internal grounding pattern 30 is exposed. By forming the hole metal 14E' in the hole 15, the hole metal 14E' can be brought into contact with the internal grounding pattern 30. The hole metal 14E' is also in contact with the metal film 14A. The hole metal 14E' suppresses the resonance in the cavity. The hole 15 does not penetrate the multi-layer substrate 12, and thus the strength of the semiconductor device 10 can be improved compared to the case where the hole 15 penetrates the multi-layer substrate 12.

[0052] The variations, modifications, or alternatives described in Embodiment 1 can be applied to the semiconductor device and the method for manufacturing the semiconductor device in the following embodiments. The semiconductor device and the method for manufacturing the semiconductor device in the following embodiments are mainly described with respect to the differences from Embodiment 1.

[0053] Implementation method 2.

[0054] Fig.10 1 is a perspective view of a semiconductor device 50 according to Embodiment 2. The width of the plurality of grooves 52 decreases from the upper surface of the insulating seal 13 to the lower surface of the multilayer substrate 12. That is, the grooves 52 are tapered downward. The hole 15 is tapered in shape with a diameter decreasing as it approaches the lower surface of the multilayer substrate 12 from the upper surface of the insulating seal 13. The inner wall of the hole 15 is formed with a hole metal 14F.

[0055] Fig.11 2 is a cross-sectional view of the separation through hole 21. The separation through hole 21 is formed in a conical shape along the separation position 20. The separation through hole 21 is a hole whose diameter gradually decreases from the upper surface to the lower surface of the semiconductor device. In this example, the separation through hole 21 penetrates the multilayer substrate 12. The metal portion 14B′ formed on the inner wall of the separation through hole 21 is connected to the metal film 14A, the back grounding pattern 17, and the internal grounding pattern 30.

[0056] Fig.12 2 is a cross-sectional view of the hole 15. The hole 15 is also a hole whose diameter gradually decreases from the upper surface to the lower surface of the semiconductor device, similarly to the isolation through hole 21. The metal 14F in the hole is connected to the metal film 14A, the back ground pattern 17, and the internal ground pattern 30.

[0057] like Fig.11 , 12 As shown in the example, the plurality of isolation through holes 21 and the hole 15 have a tapered shape in which the diameter decreases as the diameter approaches the lower surface of the multilayer substrate 12 from the upper surface of the insulating sealing material 13 .

[0058] Such tapered separation through holes 21 and holes 15 can easily thicken the metal portion 14B' and the metal in the hole 14F at their lowest part and its vicinity. As an example, if the metal portion 14B' and the metal in the hole 14F are formed by evaporation, it is easy to thicken the lower end portion and its vicinity. Since the thickening of the metal portion 14B' and the metal in the hole 14F reliably makes them contact with the grounding pattern, it is possible to achieve electromagnetic shielding and suppress cavity resonance regardless of process deviation.

[0059] Fig.13 1 is a cross-sectional view of a metal hole 14F of a modified example. When the hole 15 extends to the middle of the multi-layer substrate 12 without penetrating the multi-layer substrate 12, the metal hole 14F can be brought into contact with the built-in grounding pattern 30. Since the hole 15 does not penetrate the multi-layer substrate 12, the strength of the semiconductor device can be improved compared to the case where the hole 15 penetrates the multi-layer substrate 12.

[0060] The shapes, depths, and arrangements of the isolation through holes 21 and the holes 15 in the first and second embodiments and their modifications can be changed according to the application of the semiconductor device.

[0061] Description of Reference Numerals

[0062] 10...semiconductor device; 12...multilayer substrate; 13...insulating seal; 14A...metal film; 14B...metal in groove; 14B′...metal portion; 14E, 14F...metal in hole; 15...hole; 17...back grounding pattern; 21...through hole for separation; 30...internal grounding pattern.

Claims

1. A semiconductor device, characterized in that: have: A multilayer substrate having a wiring pattern and a grounding pattern formed thereon; a plurality of semiconductor elements mounted on the multi-layer substrate; An insulating sealant is disposed on the multi-layer substrate and covers the plurality of semiconductor elements; A metal film, disposed on the insulating seal; In-groove metal is provided to be in contact with a plurality of grooves extending from an upper end of a side surface of the insulating seal member to a lower end of a side surface of the multi-layer substrate; and The metal in the hole is provided on the inner wall of the hole in contact with the metal film and the grounding pattern, and the hole passes through the insulating seal member to reach the multi-layer substrate. The plurality of grooves are arranged at intervals.

2. The semiconductor device according to claim 1, wherein: The grounding pattern includes a back-surface grounding pattern exposed on the back surface of the multi-layer substrate. The hole penetrates the insulating seal and the multi-layer substrate. The metal in the hole is in contact with the back surface grounding pattern.

3. The semiconductor device according to claim 1, wherein: The ground pattern includes an internal ground pattern provided inside the multi-layer substrate. The hole passes through the insulating seal and extends to the middle of the multi-layer substrate, but does not pass through the multi-layer substrate. The metal in the hole is in contact with the built-in grounding pattern.

4. The semiconductor device according to any one of claims 1 to 3, wherein: A conductive wire is provided for connecting the plurality of semiconductor elements to the wiring pattern.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The widths of the plurality of grooves decrease from an upper surface of the insulating seal to a lower surface of the multi-layer substrate.

6. The semiconductor device according to any one of claims 1 to 3, wherein: The hole is formed in a tapered shape whose diameter decreases as it approaches from the upper surface of the insulating sealant to the lower surface of the multi-layer substrate.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that The interval between two adjacent grooves of the plurality of grooves is 0.6 mm to 1 mm.

8. The semiconductor device according to any one of claims 1 to 3, wherein: The plurality of semiconductor elements include a first semiconductor element and a second semiconductor element. When viewed from above, at least a portion of the metal in the hole is located between the first semiconductor element and the second semiconductor element.

9. The semiconductor device according to any one of claims 1 to 3, characterized in that: A plurality of holes and a plurality of metals in the holes are provided.

10. A method for manufacturing a semiconductor device, characterized in that: have: A plurality of semiconductor elements are mounted on a multilayer substrate having a wiring pattern and a grounding pattern. forming an insulating sealing member covering the plurality of semiconductor elements on the multi-layer substrate, A plurality of separation through holes penetrating the insulating sealing member and the multilayer substrate are formed so as to surround the plurality of semiconductor elements in a plan view, A hole penetrating the insulating sealant and reaching the multilayer substrate is formed at a position surrounded by the plurality of separation through holes in a plan view. forming: a metal film on the insulating seal, a metal portion provided in the plurality of isolation through holes and in contact with the metal film and the grounding pattern, and an in-hole metal provided on the inner wall of a hole formed at a position surrounded by the plurality of isolation through holes in contact with the metal film and the grounding pattern, and The stacked layers consisting of the adjacent plurality of multilayer substrates and the insulating sealing member are separated along the plurality of separation through holes to separate the semiconductor devices.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: In a plan view, at least a portion of the hole formed at a position surrounded by the plurality of isolation through holes is located between the plurality of semiconductor elements.

12. The method for manufacturing a semiconductor device according to claim 10 or 11, characterized in that: The holes formed at positions surrounded by the plurality of separation through holes penetrate the multilayer substrate.

13. The method for manufacturing a semiconductor device according to claim 10 or 11, characterized in that: The hole formed at a position surrounded by the plurality of isolation through holes extends to the middle of the multilayer substrate without penetrating the multilayer substrate.

14. The method for manufacturing a semiconductor device according to claim 10 or 11, characterized in that: The plurality of separation through holes have the same diameter as a hole formed at a position surrounded by the plurality of separation through holes.

15. The method for manufacturing a semiconductor device according to claim 10 or 11, characterized in that: The metal film, the metal portion, and the metal in the hole are formed collectively by vapor deposition or plating.

16. The method for manufacturing a semiconductor device according to claim 10 or 11, characterized in that: The plurality of isolation through holes and the holes formed at positions surrounded by the plurality of isolation through holes are formed in a tapered shape whose diameters decrease as they approach from the upper surface of the insulating sealing member to the lower surface of the multilayer substrate.

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