Method, device, chip, equipment and medium for inter-core interrupt program operation

Abstract

The disclosed embodiment discloses a method, device, chip, equipment and medium for running an interrupt program between cores, the method comprising: in response to the current running state of the first processing core being an interrupt nesting state, determining the running state of the interrupt program on the first processing core; in response to the high-priority first interrupt program on the first processing core being running, the low-priority second interrupt program being suspended, and the running time of the first interrupt program being greater than or equal to a preset time threshold, determining a second processing core whose current running state is an idle state among multiple processing cores; controlling the second processing core and the first processing core to poll and run the second interrupt program for a preset time until it ends. The disclosed technical solution improves the processing efficiency of the interrupt program by polling and running the low-priority interrupt program between cores, thereby improving the program processing efficiency of the CPU.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a method, device, chip, equipment and medium for running an interrupt program between cores. Background Art

[0002] Interrupt nesting refers to the process in which when the central processing unit (CPU) is executing an interrupt program and another interrupt program with a higher priority makes an interrupt request, the CPU will temporarily suspend the currently running interrupt program with a lower priority and process the interrupt program with a higher priority. After the processing is completed, the CPU will return to the interrupted interrupt program to continue running.

[0003] Currently, when interrupt nesting occurs in the CPU, low-priority interrupt programs need to wait for high-priority interrupt programs to be completed by the CPU before they can continue to run. If the high-priority interrupt program occupies the CPU for a long time, the low-priority interrupt program may be in a waiting state and cannot be completed. In a multi-core CPU, that is, a CPU has multiple CPU cores, since each CPU core will run a program and each CPU core may have interrupt nesting, when interrupt nesting occurs in multiple CPU cores, the CPU program processing efficiency will be greatly reduced, reducing chip performance.

[0004] Therefore, how to improve the program processing efficiency of the CPU has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] In order to solve the problems in the related art, the embodiments of the present disclosure provide a method, apparatus, chip, device and medium for executing an interrupt program between cores.

[0006] In a first aspect, an embodiment of the present disclosure provides a method for executing an interrupt program between cores.

[0007] Specifically, the method for inter-core execution of an interrupt program is applied to a processor including multiple processing cores, and the method includes:

[0008] In response to the current running state of the first processing core being an interrupt nesting state, determining the running state of the interrupt program on the first processing core;

[0009] In response to a first interrupt program with a high priority being executed on the first processing core, a second interrupt program with a low priority being suspended, and a running time of the first interrupt program being greater than or equal to a preset time threshold, determining a second processing core whose current running state is an idle state among the multiple processing cores;

[0010] The second processing core and the first processing core are controlled to poll and run the second interrupt program for a preset time length until the second interrupt program finishes running.

[0011] In one implementation of the present disclosure, the method further includes:

[0012] In response to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold, and no second processing core whose current running state is idle is determined among the multiple processing cores, the first processing core is controlled to continue running the first interrupt program.

[0013] In one implementation of the present disclosure, the method further includes:

[0014] In response to the time between when the first processing core continues to start running the first interrupt program and when the first interrupt program ends, a second processing core whose current running state is idle is determined among the multiple processing cores, and the second processing core and the first processing core are controlled to poll and run the second interrupt program for a preset time until the second interrupt program ends.

[0015] In an implementation of the present disclosure, controlling the second processing core and the first processing core to poll and run the second interrupt program for a preset time length includes:

[0016] In response to the second interrupt program polling the second processing core, obtaining a corresponding relationship table of the corresponding relationship between the program identifier, the stack identifier and the storage address recorded locally;

[0017] Acquire a first storage address of the second interrupt program in a first stack corresponding to the first processing core based on the correspondence table;

[0018] Controlling the second processing core to read and restore the on-site cache data of the second interrupt program from the first stack corresponding to the first processing core based on the first storage address;

[0019] Based on the on-site cache data of the second interrupt program, running the second interrupt program for a preset duration;

[0020] or,

[0021] In response to the second interrupt program polling the first processing core, obtaining the corresponding relationship table;

[0022] Acquire a second storage address of the second interrupt program in a second stack corresponding to the second processing core based on the correspondence table;

[0023] Controlling the first processing core to read and restore the on-site cache data of the second interrupt program from a second stack corresponding to the second processing core based on the second storage address;

[0024] Based on the on-site cache data of the second interrupt program, running the second interrupt program for a preset duration;

[0025] Among them, the program identifier is the identifier of the interrupt program whose operation is suspended by the processing core, the stack identifier is the identifier of the corresponding stack that stores the on-site cache data of the interrupt program, and the storage address is the corresponding address where the on-site cache data of the interrupt program is stored in the corresponding stack.

[0026] In one implementation of the present disclosure, the method further includes:

[0027] In response to the second interrupt program about to poll the second processing core, controlling the first processing core to suspend the second interrupt program and obtain current on-site cache data of the second interrupt program;

[0028] Controlling the first processing core to store the current on-site cache data into a first stack corresponding to the first processing core;

[0029] Determine a program identifier of the second interrupt program, a stack identifier of the first stack, and a first storage address where the current live cache data is stored in the first stack;

[0030] Recording the program identifier of the second interrupt program, the stack identifier of the first stack, and the first storage address in the corresponding relationship table;

[0031] or,

[0032] In response to the second interrupt program about to poll the first processing core, controlling the second processing core to suspend the execution of the second interrupt program and obtaining current on-site cache data of the second interrupt program;

[0033] Controlling the second processing core to store the current on-site cache data into a second stack corresponding to the second processing core;

[0034] Determine a program identifier of the second interrupt program, a stack identifier of the second stack, and a second storage address where the current live cache data is stored in the second stack;

[0035] The correspondence between the program identifier of the second interrupt program, the stack identifier of the second stack and the second storage address is recorded in the correspondence table.

[0036] In one implementation of the present disclosure, the method further includes:

[0037] In response to the second processing core whose current program running state is not determined to be an idle state among the multiple processing cores between the moment when the first processing core continues to start running the first interrupt program and the moment when the first interrupt program ends running, the first processing core is controlled to run the second interrupt program.

[0038] In one implementation of the present disclosure, the method further includes:

[0039] In response to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold, and no second processing core whose current running state is idle is determined among the multiple processing cores, the first processing core is controlled to poll and run the first interrupt program and the second interrupt program for a preset time.

[0040] In one implementation of the present disclosure, the method further includes:

[0041] While the second processing core and the first processing core are polling and running the second interrupt program for a preset duration, in response to the current running state of the second processing core entering a busy state or an interrupt nested state, the first processing core is controlled to poll and run the second interrupt program and the first interrupt program for the preset duration.

[0042] In one implementation of the present disclosure, the method further includes:

[0043] In response to the first interrupt program on the first processing core being completed within the preset time threshold, the first processing core is controlled to execute the second interrupt program.

[0044] In an implementation of the present disclosure, before controlling the second processing core and the first processing core to poll and run the second interrupt program for a preset time length, the method further includes:

[0045] determining an application program being run by the second processing core;

[0046] In response to the second processing core running an application, the application is suspended.

[0047] In one implementation of the present disclosure, the method further includes:

[0048] In response to the second interrupt program currently being polled and executed on the first processing core, or the second interrupt program being finished executing, the second processing core is controlled to continue executing the application program.

[0049] In one implementation of the present disclosure, the method further includes:

[0050] In response to the second interrupt program currently being polled and executed on the second processing core, or the second interrupt program being finished executing, the first processing core is controlled to continue executing the first interrupt program.

[0051] In a second aspect, an apparatus for executing an interrupt program between cores is provided in an embodiment of the present disclosure.

[0052] Specifically, the device for inter-core execution interrupt program is applied to a processor including multiple processing cores, and the device includes:

[0053] A first determining module is configured to determine the running state of the interrupt program on the first processing core in response to the current running state of the first processing core being an interrupt nesting state;

[0054] A second determining module is configured to determine a second processing core whose current running state is an idle state among the multiple processing cores in response to the first interrupt program with a high priority being running on the first processing core, the second interrupt program with a low priority being suspended, and the running time of the first interrupt program being greater than or equal to a preset time threshold;

[0055] The inter-core polling module is configured to control the second processing core and the first processing core to poll and run the second interrupt program for a preset time length until the second interrupt program ends.

[0056] In one implementation of the present disclosure, the device further includes:

[0057] The running module is configured to control the first processing core to continue running the first interrupt program in response to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold and no second processing core whose current running state is idle is determined among the multiple processing cores.

[0058] In one implementation of the present disclosure, the inter-core polling module is also configured to determine, in response to the time between the moment when the first processing core continues to start running the first interrupt program and the moment when the first interrupt program ends, a second processing core whose current running state is idle among the multiple processing cores, and control the second processing core and the first processing core to poll and run the second interrupt program for a preset time length until the second interrupt program ends.

[0059] In one implementation of the present disclosure, the inter-core polling module is further configured to, in response to the second interrupt program polling the second processing core, obtain a correspondence table of correspondences between locally recorded program identifiers, stack identifiers, and storage addresses; obtain a first storage address of the second interrupt program in the first stack corresponding to the first processing core based on the correspondence table; control the second processing core to read and restore the on-site cache data of the second interrupt program from the first stack corresponding to the first processing core based on the first storage address; run the second interrupt program for a preset duration based on the on-site cache data of the second interrupt program; or,

[0060] In response to the second interrupt program polling the first processing core, the corresponding relationship table is obtained; based on the corresponding relationship table, a second storage address of the second interrupt program in the second stack corresponding to the second processing core is obtained; based on the second storage address, the first processing core is controlled to read and restore the on-site cache data of the second interrupt program from the second stack corresponding to the second processing core; based on the on-site cache data of the second interrupt program, the second interrupt program is run for a preset duration;

[0061] Among them, the program identifier is the identifier of the interrupt program whose operation is suspended by the processing core, the stack identifier is the identifier of the corresponding stack that stores the on-site cache data of the interrupt program, and the storage address is the corresponding address where the on-site cache data of the interrupt program is stored in the corresponding stack.

[0062] In one implementation of the present disclosure, the device further includes:

[0063] A recording module is configured to, in response to the second interrupt program about to poll the second processing core, control the first processing core to suspend the second interrupt program and obtain the current on-site cache data of the second interrupt program; control the first processing core to store the current on-site cache data in a first stack corresponding to the first processing core; determine the program identifier of the second interrupt program, the stack identifier of the first stack and the first storage address at which the current on-site cache data is stored in the first stack; record the program identifier of the second interrupt program, the stack identifier of the first stack and the first storage address in the corresponding relationship table; or,

[0064] In response to the second interrupt program about to poll the first processing core, the second processing core is controlled to suspend the running of the second interrupt program and obtain the current on-site cache data of the second interrupt program; the second processing core is controlled to store the current on-site cache data in a second stack corresponding to the second processing core; the program identifier of the second interrupt program, the stack identifier of the second stack and the second storage address where the current on-site cache data is stored in the second stack are determined; and the correspondence between the program identifier of the second interrupt program, the stack identifier of the second stack and the second storage address is recorded in the correspondence table.

[0065] In one implementation of the present disclosure, the running module is further configured to control the first processing core to run the second interrupt program in response to a second processing core whose current program running state is not determined to be an idle state among the multiple processing cores between the moment when the first processing core continues to start running the first interrupt program and the moment when the first interrupt program ends.

[0066] In one implementation of the present disclosure, the device further includes:

[0067] The single-core polling module is configured to respond to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold, and no second processing core whose current running state is idle is determined among the multiple processing cores, and the first processing core polls and runs the first interrupt program and the second interrupt program for a preset time.

[0068] In one implementation of the present disclosure, the single-core polling module is also configured to control the first processing core to poll and run the second interrupt program and the first interrupt program for a preset time length in response to the current running state of the second processing core entering a busy state or an interrupt nested state during the period when the second processing core and the first processing core are polling and running the second interrupt program for a preset time length, thereby controlling the first processing core to poll and run the second interrupt program and the first interrupt program for the preset time length.

[0069] In an implementation of the present disclosure, the running module is further configured to control the first processing core to run the second interrupt program in response to the first interrupt program on the first processing core finishing running within the preset time threshold.

[0070] In one implementation of the present disclosure, the device further includes:

[0071] The suspension module is configured to determine the application program being run by the second processing core; and in response to the second processing core being run by the application program, suspend the running of the application program.

[0072] In one implementation of the present disclosure, the running module is further configured to control the second processing core to continue running the application in response to the second interrupt program currently being polled and running on the first processing core, or the second interrupt program finishing running.

[0073] In one implementation of the present disclosure, the inter-core polling module is further configured to control the first processing core to continue running the first interrupt program in response to the second interrupt program currently being polled to run on the second processing core, or the second interrupt program finishing running.

[0074] In a third aspect, the present application provides a chip, the chip including a processor, the processor being used to call a computer program in a memory to execute the above-mentioned method of inter-core running interrupt program.

[0075] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, comprising a memory and at least one processor, wherein the memory is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the method in the above-mentioned first aspect and any possible implementation manner of the first aspect.

[0076] In a fifth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method in the first aspect and any possible implementation manner of the first aspect.

[0077] The technical effects provided by the embodiments of the present disclosure may include the following beneficial effects:

[0078] In the above technical solution, when it is determined that the first interrupt program with a high priority is running on the first processing core, the second interrupt program with a low priority is suspended, and the running time of the first interrupt program is greater than or equal to the preset time threshold, the second processing core whose current running state is idle is determined among the multiple processing cores, and then the second processing core and the first processing core are controlled to poll and run the second interrupt program for a preset time until the second interrupt program ends. The technical solution provided by the present disclosure runs the low-priority interrupt program that has not been processed for a long time by means of inter-core polling, which avoids the low-priority interrupt program from waiting all the time and improves the processing efficiency of the interrupt program. Moreover, during the inter-core polling, when the low-priority interrupt program is running on any one of the processing cores, the remaining processing cores can continue to run other programs, so that each processing core is always in a working state, which improves the utilization rate of each processing core, ensures the balance of CPU resource utilization, improves the CPU program processing efficiency, and guarantees chip performance.

[0079] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0081] Figure 1 A flowchart showing a method for executing an inter-core interrupt program according to an embodiment of the present disclosure;

[0082] Figure 2 A structural block diagram showing a device for inter-core execution interrupt program according to an embodiment of the present disclosure;

[0083] Figure 3 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0084] Figure 4 It is a structural diagram of a computer system suitable for implementing a method for executing an inter-core interrupt program according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0085] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0086] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0087] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0088] As mentioned above, when interrupt nesting occurs in the CPU, the low-priority interrupt program needs to wait for the high-priority interrupt program to be completed by the CPU before it can continue to run. If the high-priority interrupt program occupies the CPU for a long time, the low-priority interrupt program may be in a waiting state and cannot be completed. In a multi-core CPU scenario, since each CPU core will run an application, each CPU core may have interrupt nesting. When interrupt nesting occurs on multiple CPU cores, the CPU program processing efficiency will be greatly reduced, reducing chip performance.

[0089] In view of the above defects, the technical solution provided by the embodiment of the present disclosure is that when it is determined that the first interrupt program with a high priority on the first processing core is running, the second interrupt program with a low priority is suspended, and the running time of the first interrupt program is greater than or equal to the preset time threshold, the second processing core whose current running state is idle is determined among multiple processing cores, and then the second processing core and the first processing core are controlled to poll and run the second interrupt program for a preset time until the second interrupt program is finished. The low-priority interrupt program that has not been processed for a long time is run by inter-core polling, which avoids the low-priority interrupt program from waiting all the time and improves the processing efficiency of the interrupt program. Moreover, during the inter-core polling period, when the low-priority interrupt program is running on any one of the processing cores, the remaining processing cores can continue to run other programs, so that each processing core is always in a working state, the utilization rate of each processing core is improved, and the balance of CPU resource utilization is ensured, thereby improving the CPU program processing efficiency and ensuring chip performance.

[0090] Figure 1 A flowchart of a method for executing an interrupt program between cores according to an embodiment of the present disclosure is shown. Figure 1 As shown, the method for inter-core execution interrupt program includes the following steps S101-S103.

[0091] In step 101, in response to the current running state of a first processing core being an interrupt nesting state, the running state of an interrupt program on the first processing core is determined.

[0092] In step 102, in response to the fact that a high-priority first interrupt program is running on the first processing core, a low-priority second interrupt program is suspended, and the running time of the first interrupt program is greater than or equal to a preset time threshold, a second processing core whose current running state is an idle state is determined among the multiple processing cores.

[0093] In step 103, the second processing core and the first processing core are controlled to poll and run the second interrupt program for a preset time length until the second interrupt program finishes running.

[0094] The above-mentioned method of inter-core running interrupt program can be implemented by a processor including multiple processing cores, such as a multi-core CPU, or can be executed by a physical device that can provide the function of the processor, or can be executed by a component (such as a chip, etc.) configured in a physical device, or can also be executed by a module that can implement part or all of the processor functions, etc., and the present application does not limit this. For ease of understanding, the present disclosure takes a processor including multiple processing cores as an example to describe the method provided by the present disclosure. It should be understood that when the processor is a CPU, each CPU core is equivalent to a processing core.

[0095] In this embodiment, for any one of the multiple processing cores, the processing core may have three different operating states: an idle state, a busy state, or an interrupt nesting state.

[0096] The idle state means that the processing core does not run any application program, or only runs one application program. In short, the processing core does not run any interrupt program in the idle state.

[0097] The busy state means that when the processing core is running an application, an emergency program (that is, an interrupt program) comes, and the processor stops running the application and runs the interrupt program instead. Then the state of the processing core is busy. In short, the processing core runs an interrupt program in the busy state.

[0098] The interrupt nesting state means that when the processing core is running an application, an emergency program (that is, an interrupt program) comes, and the processor pauses running the application and runs the interrupt program instead. While running the emergency program, another more urgent program (that is, another interrupt program) comes, and the processor pauses running the emergency program and runs the new more urgent interrupt program instead. The state of the processing core is the interrupt nesting state. In short, the processing core runs two interrupt programs in the interrupt nesting state.

[0099] In some embodiments, the first processing core may be any processing core of the plurality of processing cores whose current running state is the interrupt nesting state. The running state of the interrupt program may at least include: the running time of the interrupt program and whether the interrupt program is suspended.

[0100] In some embodiments, the processor may record the current running state of each processing core in real time, and the current running state of each processing core may change as the program running by the processing core changes. The processor may also record the identity document (ID) of the program running by each processing core in the current running state.

[0101] In one embodiment of the present disclosure, the processor may record the priority of each interrupt program.

[0102] In one embodiment of the present disclosure, the processor is deployed with the same number of counters as the processing cores, and each counter corresponds to a processing core. The counter is used to monitor the running time of the interrupt program, and each counter corresponds to a preset time threshold. When the running time of the interrupt program reaches the preset time threshold, the counter is cleared and a timeout signal is output.

[0103] It should be understood that those skilled in the art may set the preset duration threshold of the counter corresponding to each processing core according to actual needs, and the preset duration thresholds of multiple counters may be the same or different.

[0104] In one embodiment of the present disclosure, the first interrupt program is a high-priority interrupt program on the first processing core, and the second interrupt program is a low-priority interrupt program on the first processing core.

[0105] In one embodiment of the present disclosure, the second processing core may be any one of the multiple processing cores whose current running state is an idle state.

[0106] When the processor determines that the current running state of a processing core is an interrupt nesting state, the processing core can be used as the first processing core, and the running time of two interrupt programs on the first processing core, whether the two interrupt programs are currently being run, and the priority of each interrupt program can be determined. If it is determined that the first interrupt program with a high priority on the first processing core is currently being run, and the second interrupt program with a low priority is currently suspended, and the running time of the first interrupt program is greater than or equal to the preset time threshold, it means that the running time of the first interrupt program has been very long. In order to run the second interrupt program in time and avoid the second interrupt program waiting for a long time, any processing core whose current running state is an idle state can be determined from multiple processing cores, and the processing core can be used as the second processing core, and the first processing core and the second processing core are controlled to poll and run the second interrupt program for a preset time until the second interrupt program is polled and run. Wherein, when the second interrupt program with a low priority polls the second processing core, the first processing core can continue to run the first interrupt program with a high priority locally. When the second interrupt program with a low priority level polls the first processing core, and an application program has been suspended before running on the second processing core, the second processing core can continue to run the application program locally.

[0107] It should be understood that those skilled in the art may set a preset polling duration (eg, 0.5 seconds) according to actual needs, and the present disclosure does not impose any limitation on this, and all of this is within the scope of protection.

[0108] In the disclosed embodiment, a low-priority interrupt program that has not been processed for a long time is run through inter-core polling, thereby avoiding the low-priority interrupt program from waiting and improving the processing efficiency of the interrupt program. Moreover, during the inter-core polling, when a low-priority interrupt program is running on any one of the processing cores, the remaining processing cores can continue to run other programs, so that each processing core is always in a working state, improving the utilization rate of each processing core, ensuring the balance of CPU resource utilization, and further improving the CPU program processing efficiency and ensuring chip performance.

[0109] In an optional implementation of this embodiment, the following process may also be included:

[0110] In response to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold, and no second processing core whose current running state is idle is determined among the multiple processing cores, the first processing core is controlled to continue running the first interrupt program.

[0111] In this optional implementation, when the processor determines the running state of the interrupt program on the first processing core, if it is determined that the high-priority first interrupt program is running, the low-priority second interrupt program is currently suspended, and the running time of the first interrupt program is greater than or equal to the preset time threshold, but the second processing core whose current running state is idle is not determined from the multiple processing cores, it means that there is no processing core that can realize inter-core polling of the second interrupt program with the first processing core. Then, the first processing core can be controlled to continue running the high-priority first interrupt program to continue waiting for the emergence of the second processing core in the idle state.

[0112] In an optional implementation of this embodiment, the following process may also be included:

[0113] In response to the time between when the first processing core continues to start running the first interrupt program and when the first interrupt program ends, a second processing core whose current running state is idle is determined among the multiple processing cores, and the second processing core and the first processing core are controlled to poll and run the second interrupt program for a preset time until the second interrupt program ends.

[0114] In this optional implementation, the processor monitors the running status of each processing core in real time while continuing to run the first interrupt program. If a processing core in an idle state is determined before the first interrupt program is completed, the processing core will be used as the second processing core, and the first processing core and the second processing core will be controlled to poll and run the second interrupt program for a preset time until the second interrupt program is polled and run.

[0115] In some embodiments, if the second processing core is also running an application program before running the second interrupt program with a low priority, the second processing core may continue to run the application program after the inter-core polling of the second interrupt program ends.

[0116] In some embodiments, after the inter-core polling of the low-priority second interrupt program ends, if the first interrupt program has not yet been executed to completion, the first processing core may continue to execute the first interrupt program.

[0117] Because the long-unprocessed, low-priority second interrupt program is timely run through inter-core polling before the first interrupt program ends, the long waiting time of the low-priority second interrupt program is avoided to a certain extent, and the processing efficiency of the interrupt program is improved. Moreover, during the inter-core polling period, when the low-priority interrupt program is running on any one of the processing cores, the remaining processing cores can continue to run other programs, so that each processing core is always in a working state, the utilization rate of each processing core is improved, the balance of CPU resource utilization is ensured, and the chip performance is guaranteed.

[0118] In an optional implementation of this embodiment, the aforementioned step of controlling the second processing core and the first processing core to poll and run the second interrupt program for a preset time length may further include the following process:

[0119] In response to the second interrupt program polling the second processing core, obtaining a corresponding relationship table of the corresponding relationship between the program identifier, the stack identifier and the storage address recorded locally;

[0120] Acquire a first storage address of the second interrupt program in a first stack corresponding to the first processing core based on the correspondence table;

[0121] Controlling the second processing core to read and restore the on-site cache data of the second interrupt program from the first stack corresponding to the first processing core based on the first storage address;

[0122] Based on the on-site cache data of the second interrupt program, running the second interrupt program for a preset duration;

[0123] or,

[0124] In response to the second interrupt program polling the first processing core, obtaining the corresponding relationship table;

[0125] Acquire a second storage address of the second interrupt program in a second stack corresponding to the second processing core based on the correspondence table;

[0126] Controlling the first processing core to read and restore the on-site cache data of the second interrupt program from a second stack corresponding to the second processing core based on the second storage address;

[0127] Based on the on-site cache data of the second interrupt program, running the second interrupt program for a preset duration;

[0128] Among them, the program identifier is the identifier of the interrupt program whose operation is suspended by the processing core, the stack identifier is the identifier of the corresponding stack that stores the on-site cache data of the interrupt program, and the storage address is the corresponding address where the on-site cache data of the interrupt program is stored in the corresponding stack.

[0129] In this optional implementation, each program also has a corresponding program identifier. Each processing core also corresponds to a stack, and each stack has a corresponding stack identifier. Each stack can be used to store the on-site cache data of the program (suspended application or interrupt program) suspended by the corresponding processing core, and the location where each on-site cache data is stored in the corresponding stack is called the storage address of the on-site cache data in the stack. Among them, the on-site cache data can, for example, at least include: an instruction counter (program counter, PC) pointer, and the value of a general register.

[0130] In some embodiments, the processor may update and record the correspondence between the program identifier, stack identifier, and storage address of the program interrupted by each processing core at any time, thereby obtaining a correspondence table. It is understandable that when any processing core suspends any program and stores the on-site cache data of the program at a certain location in the corresponding stack, the processor will update the correspondence table.

[0131] When the processor controls the first processing core and the second processing core to poll and run the second interrupt program for a preset duration, if the processor determines that the second interrupt program is the second processing core, the processor can obtain the latest local correspondence table, and determine based on the correspondence table the specific location of the second interrupt program's on-site cache data stored by the first processing core in the corresponding stack when the second interrupt program was last run on the first processing core, that is, determine the first storage address of the second interrupt program in the first stack corresponding to the first processing core. Afterwards, the processor can control the second processing core to read and restore the on-site cache data corresponding to the second interrupt program when it was last suspended by the first processing core from the first storage address in the first stack corresponding to the first processing core, and then continue to run the second interrupt program for a preset duration based on the restored on-site cache data.

[0132] Correspondingly, if the processor determines that the first interrupt program is to be executed on the first processing core, the processor can also obtain the latest local correspondence table, and determine based on the correspondence table the specific location of the second interrupt program's on-site cache data stored by the second processing core in the corresponding stack when the second interrupt program was last executed on the second processing core, that is, determine the second storage address of the second interrupt program in the second stack corresponding to the second processing core. Afterwards, the processor can control the first processing core to read and restore the on-site cache data corresponding to the second interrupt program when it was last suspended by the second processing core from the second storage address in the second stack corresponding to the second processing core, and then continue to run the second interrupt program for a preset duration based on the restored on-site cache data.

[0133] In some embodiments, those skilled in the art may allocate a portion of the processor's memory according to actual needs to temporarily cache the on-site cache data read from the stack by the processing core.

[0134] In this way, the second interrupt program can be continuously run in turn by the first processing core and the second processing core until it is completed. Since the second interrupt program with a low priority that has not been processed for a long time is run in time through the polling between cores, the second interrupt program with a low priority is avoided from waiting for too long, the processing efficiency of the interrupt program is improved, and then the program processing efficiency of the CPU is improved, and the chip performance is guaranteed.

[0135] In an optional implementation of this embodiment, the following process may also be included:

[0136] In response to the second interrupt program about to poll the second processing core, controlling the first processing core to suspend the second interrupt program and obtain current on-site cache data of the second interrupt program;

[0137] Controlling the first processing core to store the current on-site cache data into a first stack corresponding to the first processing core;

[0138] Determine a program identifier of the second interrupt program, a stack identifier of the first stack, and a first storage address where the current live cache data is stored in the first stack;

[0139] Recording the program identifier of the second interrupt program, the stack identifier of the first stack, and the first storage address in the corresponding relationship table;

[0140] or,

[0141] In response to the second interrupt program about to poll the first processing core, controlling the second processing core to suspend the execution of the second interrupt program and obtaining current on-site cache data of the second interrupt program;

[0142] Controlling the second processing core to store the current on-site cache data into a second stack corresponding to the second processing core;

[0143] Determine a program identifier of the second interrupt program, a stack identifier of the second stack, and a second storage address where the current live cache data is stored in the second stack;

[0144] The correspondence between the program identifier of the second interrupt program, the stack identifier of the second stack and the second storage address is recorded in the correspondence table.

[0145] In this optional implementation, during the process of the processor controlling the first processing core and the second processing core to poll and run the second interrupt program for a preset time length, if the processor determines that the second interrupt program is currently running on the first processing core and is about to run on the second processing core, the first processing core can be controlled to suspend the running of the second interrupt program, and after obtaining the current on-site cache data of the second interrupt program, the current on-site cache data of the second interrupt program is stored in a certain position in the first stack corresponding to the first processing core, and the position is referred to as the first storage address. Afterwards, the processor can record the correspondence between the program identifier of the second interrupt program, the stack identifier of the first stack, and the first storage address of the current on-site cache data of the second interrupt program in the first stack in a correspondence table, so that the second processing core can obtain the on-site cache data of the second interrupt program based on the correspondence table to continue running the second interrupt program.

[0146] Accordingly, if the processor determines that the second interrupt program is currently running on the second processing core and is about to run on the first processing core, the second processing core can be controlled to suspend the running of the second interrupt program, and after obtaining the current on-site cache data of the second interrupt program, the current on-site cache data of the second interrupt program is stored in a certain position in the second stack corresponding to the second processing core, and the position is referred to as the second storage address. Afterwards, the processor can record the correspondence between the program identifier of the first interrupt program, the stack identifier of the second stack, and the second storage address of the current on-site cache data of the second interrupt program in the second stack in a correspondence table, so that the first processing core can obtain the on-site cache data of the second interrupt program based on the correspondence table to continue running the second interrupt program.

[0147] Since both the first processing core and the second processing core are polling and updating the corresponding relationship table during the process of polling and running the second interrupt program, it can be ensured that the on-site cache data of the second interrupt program obtained by any one of the two processing cores is always kept up to date.

[0148] In some embodiments, when recording the correspondence between the program identifier, stack identifier and storage address, the time of storing the on-site cache data can also be recorded in the correspondence table to ensure the accuracy of the on-site cache data of the second interrupt program obtained by any one of the two processing cores.

[0149] In an optional implementation of this embodiment, the following process may also be included:

[0150] In response to the second processing core whose current program running state is not determined to be an idle state among the multiple processing cores between the moment when the first processing core continues to start running the first interrupt program and the moment when the first interrupt program ends running, the first processing core is controlled to run the second interrupt program.

[0151] In this optional implementation, the processor monitors the operating status of each processing core in real time while continuing to run the first interrupt program. If there is no idle processing core when the first interrupt program ends, the first processing core will continue to run the second interrupt program.

[0152] Since the running state of the first interrupt program is the interrupt nesting state, it means that there was an application program running locally before the first interrupt program, but the application program was suspended after the second interrupt program came. Therefore, after the first processing core finishes running the second interrupt program, it can continue to run the local application program.

[0153] In some embodiments, after the first processing core finishes running the first interrupt program, it can also locally poll and run the second interrupt program and the local application program for a preset time. In this way, the second interrupt program is prevented from waiting all the time, and the local application program is prevented from waiting all the time, ensuring that each program can be run in a short time, so that the first processing core is always in a working state, improving its utilization rate, ensuring the balance of CPU resource utilization, improving the CPU program processing efficiency, and ensuring chip performance.

[0154] In an optional implementation of this embodiment, the following process may also be included:

[0155] In response to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold, and no second processing core whose current running state is idle is determined among the multiple processing cores, the first processing core polls and runs the first interrupt program and the second interrupt program for the preset time.

[0156] In this optional implementation, when the processor determines the running state of the interrupt program on the first processing core, if it is determined that the first interrupt program with a high priority is running, the second interrupt program with a low priority is currently suspended, and the running time of the first interrupt program is greater than or equal to the preset time threshold, but the second processing core whose current running state is idle is not determined from the multiple processing cores, that is, the current running states of the remaining processing cores except the first processing core are all busy or interrupt nested, then it means that there is no processing core that can realize inter-core polling of the second interrupt program with the first processing core. At this time, the first processing core can poll and run the first interrupt program with a high priority and the second interrupt program with a low priority for a preset time, that is, alternately run the first interrupt program and the second interrupt program by local polling. For the second interrupt program with a low priority, the second interrupt program is prevented from waiting all the time by local polling. For the first interrupt program with a high priority, it is also avoided that the second interrupt program is running for a long time, causing the first interrupt program to wait all the time. This ensures that each interrupt program can be executed in a short time, so that the first processing core is always in working state, improves its utilization rate, ensures balanced CPU resource utilization, improves CPU program processing efficiency, and ensures chip performance.

[0157] In an optional implementation of this embodiment, the following process may also be included:

[0158] While the second processing core and the first processing core are polling and running the second interrupt program for a preset time length, in response to the current running state of the second processing core entering a busy state or an interrupt nested state, the first processing core is controlled to poll and run the second interrupt program and the first interrupt program for a preset time length.

[0159] In this optional implementation, during the period when the first processing core and the second processing core poll and run the second interrupt program, if the running state of the second processing core changes from an idle state to a busy state, for example, when the second interrupt program polls the first processing core, a third interrupt program with a higher priority than the second interrupt program comes to the second processing core, then the second processing core shall give priority to running the third interrupt program with a higher priority. If the first processing core is allowed to run the second interrupt program with a low priority all the time, the first interrupt program with a high priority may be kept waiting.

[0160] Alternatively, if the running state of the second processing core changes from a busy state to an interrupt nested state, for example, when the second interrupt program polls the second processing core, a third interrupt program with a higher priority than the second interrupt program arrives on the second processing core, then the second processing core should also give priority to running the third interrupt program with a higher priority. If the second interrupt program is suspended on the second processing core to wait for the third interrupt program to finish running, the second interrupt program may keep waiting.

[0161] Therefore, in order to avoid the above situation, the processor can control the first processing core to locally poll and run the first interrupt program and the second interrupt program, ensuring that each interrupt program can be run in a short time, so that the first processing core is always in a working state, improving its utilization rate, ensuring the balance of CPU resource utilization, improving the CPU program processing efficiency, and ensuring chip performance.

[0162] In an optional implementation of this embodiment, the following process may also be included:

[0163] In response to the first interrupt program on the first processing core being completed within the preset time threshold, the first processing core is controlled to execute the second interrupt program.

[0164] In this optional implementation, when the processor determines the running status of the interrupt program on the first processing core, if it is determined that the high-priority first interrupt program on the first processing core is completed within a preset time threshold, it means that the time the first interrupt program occupies the first processing core is not very long, and the waiting time of the low-priority second interrupt program is not very long either, then the second interrupt program can continue to run after the first interrupt program is completed.

[0165] In an optional implementation of this embodiment, before controlling the second processing core and the first processing core to poll and run the second interrupt program for a preset time length, the method further includes:

[0166] determining an application program being run by the second processing core;

[0167] In response to the second processing core running an application, the application is suspended.

[0168] In this optional implementation, after the processor determines the idle second processing core that implements inter-core polling operation with the first processing core, before controlling the first processing core and the second processing core to perform inter-core polling on the second interrupt program, it can first determine whether the second processing core is currently running an application. If an application is running on the second processing core, the inter-core polling is performed after the application is suspended; if no application is running on the second processing core, the inter-core polling is performed directly.

[0169] In an optional implementation of this embodiment, the following process may also be included:

[0170] In response to the second interrupt program currently being polled and executed on the first processing core, or the second interrupt program being finished executing, the second processing core is controlled to continue executing the application program.

[0171] In this optional implementation, during the process of the first processing core and the second processing core polling to run the second interrupt program, when the second interrupt program polls and runs on the first processing core, the running state of the second processing core can be changed from a busy state to an idle state, and the second processing core can continue to run the local application. Alternatively, once the second interrupt program ends, the second processing core can immediately continue to run the local application. In this way, there are always programs running on the processing core, which avoids the idleness of the processing core, improves the utilization rate of the processing core, ensures the balance of CPU resource utilization, improves the CPU program processing efficiency, and avoids the waste of CPU resources.

[0172] In an optional implementation of this embodiment, the following process may also be included:

[0173] In response to the second interrupt program currently being polled and executed on the second processing core, or the second interrupt program being finished executing, the first processing core is controlled to continue executing the first interrupt program.

[0174] In this optional implementation, during the process of the first processing core and the second processing core polling to run the second interrupt program, when the second interrupt program polls and runs on the second processing core, the running state of the first processing core can be changed from the interrupt nesting state to the busy state, and the first processing core can continue to run the first interrupt program. Alternatively, once the second interrupt program ends running, the first processing core can immediately continue to run the first interrupt program. In this way, there are always programs running on the processing cores, which avoids the idleness of the processing cores, improves the utilization rate of the processing cores, ensures the balance of CPU resource utilization, improves the CPU program processing efficiency, and avoids the waste of CPU resources.

[0175] In an optional implementation of the present embodiment, for any processing core, as long as the processing core pauses a program (application or interrupt program) currently running locally, it can execute the following steps: storing the current on-site cache data of the program into the stack corresponding to the processing core, recording the program identifier of the program, storing the correspondence between the stack identifier of the stack corresponding to the on-site cache data of the program and the storage address of the on-site cache data of the program in the corresponding stack, and updating the running status of the processing core.

[0176] In an optional implementation of this embodiment, for any processing core, the continued running of the suspended program can be achieved through the following two methods.

[0177] In one way, when the processing core running the program before the suspension operation is performed is different from the processing core running the program after the suspension operation is performed, the processor can obtain the storage address where the program was stored in the previous suspension from the correspondence table based on the program identifier of the program, and then read and cache the on-site cache data of the program from the corresponding stack based on the storage address, and control the processing core to read the on-site cache data to restore the on-site of the suspended program, thereby controlling the processing core to continue running the program. By introducing the stack and the correspondence table, the processing core can accurately obtain the on-site cache data, thereby ensuring the accurate operation of the program.

[0178] In another way, when the processing core running the program before the pause operation is performed is the same as the processing core running the program after the pause operation is performed, the processor can control the processing core to directly read the on-site cache data of the paused program from the stack corresponding to the processing core and restore the scene, thereby controlling the processing core to continue running the program based on the restored on-site cache data. Compared with the first way, this way does not need to use a corresponding relationship table, so that the processing core can obtain the on-site cache data based on the corresponding stack, which improves the convenience of program operation.

[0179] The following are embodiments of the apparatus of the present disclosure, which can be used to execute embodiments of the method of the present disclosure.

[0180] Figure 2 The structure block diagram of the device for inter-core operation interrupt program according to one embodiment of the present disclosure is shown. The device can be implemented as part or all of the electronic device through software, hardware or a combination of both. Figure 2 As shown, the device for inter-core operation interrupt program includes:

[0181] A first determining module 210 is configured to determine the running state of the interrupt program on the first processing core in response to the current running state of the first processing core being the interrupt nesting state;

[0182] The second determining module 220 is configured to determine a second processing core whose current running state is an idle state among the multiple processing cores in response to the first interrupt program with a high priority being running on the first processing core, the second interrupt program with a low priority being suspended, and the running time of the first interrupt program being greater than or equal to a preset time threshold;

[0183] The inter-core polling module 230 is configured to control the second processing core and the first processing core to poll and run the second interrupt program for a preset time length until the second interrupt program is finished.

[0184] In an optional implementation of the present disclosure, the device further includes:

[0185] The running module is configured to control the first processing core to continue running the first interrupt program in response to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold and no second processing core whose current running state is idle is determined among the multiple processing cores.

[0186] In an optional implementation of the present disclosure, the inter-core polling module is also configured to, in response to the time between the moment when the first processing core continues to start running the first interrupt program and the moment when the first interrupt program ends, determine a second processing core among the multiple processing cores whose current running state is an idle state, and control the second processing core and the first processing core to poll and run the second interrupt program for a preset time length until the second interrupt program ends.

[0187] In an optional implementation of the present disclosure, the inter-core polling module is further configured to obtain a correspondence table of correspondences between locally recorded program identifiers, stack identifiers, and storage addresses in response to the second interrupt program polling the second processing core; obtain a first storage address of the second interrupt program in the first stack corresponding to the first processing core based on the correspondence table; control the second processing core to read and restore the on-site cache data of the second interrupt program from the first stack corresponding to the first processing core based on the first storage address; run the second interrupt program for a preset duration based on the on-site cache data of the second interrupt program; or,

[0188] In response to the second interrupt program polling the first processing core, the corresponding relationship table is obtained; based on the corresponding relationship table, a second storage address of the second interrupt program in the second stack corresponding to the second processing core is obtained; based on the second storage address, the first processing core is controlled to read and restore the on-site cache data of the second interrupt program from the second stack corresponding to the second processing core; based on the on-site cache data of the second interrupt program, the second interrupt program is run for a preset duration;

[0189] Among them, the program identifier is the identifier of the interrupt program whose operation is suspended by the processing core, the stack identifier is the identifier of the corresponding stack that stores the on-site cache data of the interrupt program, and the storage address is the corresponding address where the on-site cache data of the interrupt program is stored in the corresponding stack.

[0190] In an optional implementation of the present disclosure, the device further includes:

[0191] A recording module is configured to, in response to the second interrupt program about to poll the second processing core, control the first processing core to suspend the second interrupt program and obtain the current on-site cache data of the second interrupt program; control the first processing core to store the current on-site cache data in a first stack corresponding to the first processing core; determine the program identifier of the second interrupt program, the stack identifier of the first stack and the first storage address at which the current on-site cache data is stored in the first stack; record the program identifier of the second interrupt program, the stack identifier of the first stack and the first storage address in the corresponding relationship table; or,

[0192] In response to the second interrupt program about to poll the first processing core, the second processing core is controlled to suspend the running of the second interrupt program and obtain the current on-site cache data of the second interrupt program; the second processing core is controlled to store the current on-site cache data in a second stack corresponding to the second processing core; the program identifier of the second interrupt program, the stack identifier of the second stack and the second storage address where the current on-site cache data is stored in the second stack are determined; and the correspondence between the program identifier of the second interrupt program, the stack identifier of the second stack and the second storage address is recorded in the correspondence table.

[0193] In an optional implementation of the present disclosure, the running module is further configured to control the first processing core to run the second interrupt program in response to a second processing core whose current program running state is not determined to be an idle state among the multiple processing cores between the moment when the first processing core continues to start running the first interrupt program and the moment when the first interrupt program ends.

[0194] In an optional implementation of the present disclosure, the device further includes:

[0195] The single-core polling module is configured to respond to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold, and no second processing core whose current running state is idle is determined among the multiple processing cores, and the first processing core polls and runs the first interrupt program and the second interrupt program for a preset time.

[0196] In an optional implementation of the present disclosure, the single-core polling module is further configured to control the first processing core to poll and run the second interrupt program and the first interrupt program for a preset time length in response to the current running state of the second processing core entering a busy state or an interrupt nested state during the period when the second processing core and the first processing core are polling and running the second interrupt program for a preset time length, thereby controlling the first processing core to poll and run the second interrupt program and the first interrupt program for the preset time length.

[0197] In an optional implementation of the present disclosure, the running module is further configured to control the first processing core to run the second interrupt program in response to the first interrupt program on the first processing core finishing running within the preset time threshold.

[0198] In an optional implementation of the present disclosure, the device further includes:

[0199] The suspension module is configured to determine the application program being run by the second processing core; and in response to the second processing core being run by the application program, suspend the running of the application program.

[0200] In an optional implementation of the present disclosure, the running module is further configured to control the second processing core to continue running the application in response to the second interrupt program currently being polled and running on the first processing core, or the second interrupt program finishing running.

[0201] In an optional implementation of the present disclosure, the inter-core polling module is further configured to control the first processing core to continue running the first interrupt program in response to the second interrupt program currently being polled to run on the second processing core, or the second interrupt program finishing running.

[0202] The device for running an interrupt program between cores in this embodiment corresponds to the method for running an interrupt program between cores described above. For specific details, please refer to the description of the method for running an interrupt program between cores described above, which will not be repeated here.

[0203] The present disclosure also discloses an electronic device, Figure 3 FIG. 1 shows a structural block diagram of an electronic device according to an embodiment of the present disclosure. Figure 3 As shown, the electronic device 300 includes a memory 301 and a processor 302; wherein,

[0204] The memory 301 is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor 302 to implement the above method.

[0205] Figure 4 It is a structural diagram of a computer system suitable for implementing a method for executing an inter-core interrupt program according to an embodiment of the present disclosure.

[0206] like Figure 4As shown, the computer system 400 includes a processing unit 401, which can perform various processes in the above-mentioned embodiments according to a program stored in a read-only memory (ROM) 402 or a program loaded from a storage part 408 into a random access memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the computer system 400 are also stored. The processing unit 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0207] The following components are connected to the I / O interface 405: an input section 406 including a keyboard, a mouse, etc.; an output section 407 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN card, a modem, etc. The communication section 409 performs communication processing via a network such as the Internet. The drive 410 is also connected to the I / O interface 405 as needed. Removable media 411, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 410 as needed, so that the computer program read therefrom is installed into the storage section 408 as needed. Among them, the processing unit 401 can be implemented as a processing unit such as a CPU, a GPU, a TPU, an FPGA, an NPU, etc.

[0208] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the road map or block diagram can represent a part of a module, program segment or code, and the part of the module, program segment or code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a different order from the order marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0209] The units or modules involved in the embodiments described in the present disclosure may be implemented by software or hardware. The units or modules described may also be set in a processor, and the names of these units or modules do not constitute limitations on the units or modules themselves in some cases.

[0210] As another aspect, the present disclosure further provides a chip, which includes at least one processor and can be used to implement the functions involved in the processor in the above method embodiment.

[0211] In one possible design, the chip also includes a memory, which is used to store program instructions and data, and the memory is located inside or outside the processor.

[0212] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be a computer-readable storage medium included in the device described in the above embodiment; or a computer-readable storage medium that exists independently and is not assembled into the device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the method described in the present disclosure.

[0213] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A method for inter-core execution of an interrupt program, characterized in that: The method is applied to a processor including a plurality of processing cores, and the method includes: In response to the current running state of the first processing core being an interrupt nesting state, determining the running state of the interrupt program on the first processing core; In response to a first interrupt program with a high priority being executed on the first processing core, a second interrupt program with a low priority being suspended, and a running time of the first interrupt program being greater than or equal to a preset time threshold, determining a second processing core whose current running state is an idle state among the multiple processing cores; Controlling the second processing core and the first processing core to poll and run the second interrupt program for a preset time length until the second interrupt program finishes running; The controlling the second processing core and the first processing core to poll and run the second interrupt program for a preset time length includes: In response to the second interrupt program polling the second processing core, obtaining a corresponding relationship table of the corresponding relationship between the program identifier, the stack identifier and the storage address recorded locally; Acquire a first storage address of the second interrupt program in a first stack corresponding to the first processing core based on the correspondence table; Controlling the second processing core to read and restore the on-site cache data of the second interrupt program from the first stack corresponding to the first processing core based on the first storage address; Based on the on-site cache data of the second interrupt program, running the second interrupt program for a preset duration; Among them, the program identifier is the identifier of the interrupt program whose operation is suspended by the processing core, the stack identifier is the identifier of the corresponding stack that stores the on-site cache data of the interrupt program, and the storage address is the corresponding address where the on-site cache data of the interrupt program is stored in the corresponding stack.

2. The method according to claim 1, characterized in that Also includes: In response to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold, and no second processing core whose current running state is idle is determined among the multiple processing cores, the first processing core is controlled to continue running the first interrupt program.

3. The method according to claim 2, characterized in that Also includes: In response to the time between when the first processing core continues to start running the first interrupt program and when the first interrupt program ends, a second processing core whose current running state is idle is determined among the multiple processing cores, and the second processing core and the first processing core are controlled to poll and run the second interrupt program for a preset time until the second interrupt program ends.

4. The method according to claim 1, characterized in that: Also includes: In response to the second interrupt program about to poll the second processing core, controlling the first processing core to suspend the second interrupt program and obtain current on-site cache data of the second interrupt program; Controlling the first processing core to store the current on-site cache data into a first stack corresponding to the first processing core; Determine a program identifier of the second interrupt program, a stack identifier of the first stack, and a first storage address where the current live cache data is stored in the first stack; Recording the program identifier of the second interrupt program, the stack identifier of the first stack, and the first storage address in the corresponding relationship table; or, In response to the second interrupt program about to poll the first processing core, controlling the second processing core to suspend the execution of the second interrupt program and obtaining current on-site cache data of the second interrupt program; Controlling the second processing core to store the current on-site cache data into a second stack corresponding to the second processing core; Determine a program identifier of the second interrupt program, a stack identifier of the second stack, and a second storage address where the current live cache data is stored in the second stack; The correspondence between the program identifier of the second interrupt program, the stack identifier of the second stack and the second storage address is recorded in the correspondence table.

5. The method according to claim 3, characterized in that: Also includes: In response to the second processing core whose current program running state is not determined to be an idle state among the multiple processing cores between the moment when the first processing core continues to start running the first interrupt program and the moment when the first interrupt program ends running, the first processing core is controlled to run the second interrupt program.

6. The method according to claim 1, characterized in that Also includes: In response to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold, and no second processing core whose current running state is idle is determined among the multiple processing cores, the first processing core is controlled to poll and run the first interrupt program and the second interrupt program for a preset time.

7. The method according to claim 1 or 3, characterized in that: Also includes: While the second processing core and the first processing core are polling and running the second interrupt program for a preset time length, in response to the current running state of the second processing core entering a busy state or an interrupt nested state, the first processing core is controlled to poll and run the second interrupt program and the first interrupt program for a preset time length.

8. The method according to claim 1, characterized in that Also includes: In response to the first interrupt program on the first processing core being completed within the preset time threshold, the first processing core is controlled to execute the second interrupt program.

9. The method according to claim 1 or 3, characterized in that: Before controlling the second processing core and the first processing core to poll and run the second interrupt program for a preset time length, the method further includes: determining an application program being run by the second processing core; In response to the second processing core running an application, the application is suspended.

10. The method according to claim 9, characterized in that Also includes: In response to the second interrupt program currently being polled and executed on the first processing core, or the second interrupt program being finished executing, the second processing core is controlled to continue executing the application program.

11. The method according to claim 1 or 3, characterized in that: Also includes: In response to the second interrupt program currently being polled and executed on the second processing core, or the second interrupt program being finished executing, the first processing core is controlled to continue executing the first interrupt program.

12. A device for inter-core operation interrupt program, characterized in that: The device is applied to a processor including multiple processing cores, and the device includes: A first determining module is configured to determine the running state of the interrupt program on the first processing core in response to the current running state of the first processing core being an interrupt nesting state; A second determining module is configured to determine a second processing core whose current running state is an idle state among the multiple processing cores in response to the first interrupt program with a high priority being running on the first processing core, the second interrupt program with a low priority being suspended, and the running time of the first interrupt program being greater than or equal to a preset time threshold; an inter-core polling module, configured to control the second processing core and the first processing core to poll and run the second interrupt program for a preset time length until the second interrupt program finishes running; The inter-core polling module is also configured to obtain a correspondence table of the correspondence between the locally recorded program identifier, stack identifier and storage address in response to the second interrupt program polling the second processing core; obtain the first storage address of the second interrupt program in the first stack corresponding to the first processing core based on the correspondence table; control the second processing core to read and restore the on-site cache data of the second interrupt program from the first stack corresponding to the first processing core based on the first storage address; and run the second interrupt program for a preset duration based on the on-site cache data of the second interrupt program; wherein the program identifier is the identifier of the interrupt program suspended by the processing core, the stack identifier is the identifier of the corresponding stack that stores the on-site cache data of the interrupt program, and the storage address is the corresponding address where the on-site cache data of the interrupt program is stored in the corresponding stack.

13. The device according to claim 12, characterized in that Also includes: The running module is configured to control the first processing core to continue running the first interrupt program in response to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold and no second processing core whose current running state is idle is determined among the multiple processing cores.

14. The device according to claim 13, characterized in that The inter-core polling module is also configured to, in response to the time between the moment when the first processing core continues to start running the first interrupt program and the moment when the first interrupt program ends, determine a second processing core whose current running state is an idle state among the multiple processing cores, and control the second processing core and the first processing core to poll and run the second interrupt program for a preset time length until the second interrupt program ends.

15. The device according to claim 12, characterized in that Also includes: The recording module is configured to, in response to the second interrupt program about to poll the second processing core, control the first processing core to suspend the second interrupt program and obtain the current on-site cache data of the second interrupt program; control the first processing core to store the current on-site cache data into a first stack corresponding to the first processing core; Determine a program identifier of the second interrupt program, a stack identifier of the first stack, and a first storage address where current live cache data is stored in the first stack; Recording the program identifier of the second interrupt program, the stack identifier of the first stack, and the first storage address in the corresponding relationship table; or, In response to the second interrupt program about to poll the first processing core, controlling the second processing core to suspend the execution of the second interrupt program and obtaining current on-site cache data of the second interrupt program; Controlling the second processing core to store the current on-site cache data into a second stack corresponding to the second processing core; Determine the program identifier of the second interrupt program, the stack identifier of the second stack and the second storage address at which the current on-site cache data is stored in the second stack; and record the correspondence between the program identifier of the second interrupt program, the stack identifier of the second stack and the second storage address in the correspondence table.

16. The device according to claim 13, characterized in that The running module is also configured to control the first processing core to run the second interrupt program in response to a second processing core whose current program running state is not determined to be an idle state among the multiple processing cores between the moment when the first processing core continues to start running the first interrupt program and the moment when the first interrupt program ends.

17. The device according to claim 12, characterized in that Also includes: The single-core polling module is configured to respond to the running time of the first interrupt program running on the first processing core being greater than or equal to the preset time threshold, and no second processing core whose current running state is idle is determined among the multiple processing cores, and the first processing core polls and runs the first interrupt program and the second interrupt program for a preset time.

18. The device according to claim 17, characterized in that The single-core polling module is also configured to control the first processing core to poll and run the second interrupt program and the first interrupt program for a preset time length in response to the current running state of the second processing core entering a busy state or an interrupt nested state during the period when the second processing core and the first processing core poll and run the second interrupt program for a preset time length.

19. The device according to claim 13, characterized in that The running module is further configured to control the first processing core to run the second interrupt program in response to the first interrupt program on the first processing core finishing running within the preset time threshold.

20. The device according to claim 12 or 14, characterized in that Also includes: a pause module, configured to determine an application program currently being run by the second processing core; In response to the second processing core running an application, the application is suspended.

21. The device according to claim 20, characterized in that The running module is further configured to control the second processing core to continue running the application in response to the second interrupt program currently being polled and running on the first processing core, or the second interrupt program finishing running.

22. The device according to claim 12 or 14, characterized in that The inter-core polling module is further configured to control the first processing core to continue running the first interrupt program in response to the second interrupt program currently being polled to run on the second processing core, or the second interrupt program finishing running.

23. A chip, characterized in that: The chip comprises a processor, and the processor is used to implement the method according to any one of claims 1 to 11 when calling a computer program in a memory.

24. An electronic device, characterized in that: include: A memory and at least one processor; wherein the memory is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the method as described in any one of claims 1 to 11.

25. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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