A gallium oxide diode and a method for preparing the same

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a gallium oxide diode. The gallium oxide diode comprises a gallium oxide wafer, a cathode electrode, an anode electrode and a P-type semiconductor. The gallium oxide wafer comprises a gallium oxide substrate layer and a gallium oxide epitaxial layer. The P-type semiconductor is n layers, where n is the number of layers and n≥2. The present invention provides a multilayer P-type semiconductor, and one end of the P-type semiconductor forms a PN junction with the gallium oxide epitaxial layer, and the PN junction can compensate for the charge on the depletion side. Through the depletion effect of the PN junction, non-ideal factors such as dangling bonds introduced by etching and fixed charges introduced by etching damage in the gallium oxide diode can be passivated, thereby reducing the resistance degradation caused thereby and improving the stability of the device. At the same time, the other end of the P-type semiconductor is connected to the anode electrode to form an equipotential body, which can promote the depletion of the side PN junction, and can also disperse the high electric field of the device from the original side to the end face, thereby achieving the purpose of reducing the electric field strength of the entire device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium oxide diode and a preparation method thereof. Background Art

[0002] As a new type of ultra-wide bandgap semiconductor material, gallium oxide has a bandgap width of up to 4.8eV, and the measured breakdown field strength has reached 5.5MV / cm, which exceeds the theoretical limits of gallium nitride and silicon carbide. Therefore, gallium oxide has great application prospects under high-power conditions. Power semiconductor devices based on gallium oxide have developed rapidly in recent years, among which gallium oxide diodes have the highest commercial value. However, the gallium oxide diode devices in the prior art will have an electric field concentration effect, which will cause the peak electric field of the gallium oxide diode device to be high and the electric field distribution to be uneven. The prior art is also unable to effectively regulate the electric field of the entire device, and the high peak electric field and uneven electric field distribution of the device will cause the gallium oxide diode devices in the prior art to be prone to additional power loss or even destructive breakdown, resulting in the performance of the produced devices being far below the expected theoretical limit. Summary of the invention

[0003] In order to solve the problem in the prior art that the electric field concentration effect of the gallium oxide diode device causes the gallium oxide diode device to have a high peak electric field and uneven electric field distribution, thereby resulting in poor performance of the produced gallium oxide diode device, the present invention provides a gallium oxide diode.

[0004] To achieve the above purpose, the technical solution adopted by the present invention is: a gallium oxide diode, comprising a gallium oxide wafer, a cathode electrode, an anode electrode and a P-type semiconductor. The gallium oxide wafer comprises a gallium oxide substrate layer and a gallium oxide epitaxial layer. The gallium oxide epitaxial layer is a convex structure, and its lower bottom surface is grown on one side of the gallium oxide substrate layer. The gallium oxide epitaxial layer is provided with a side surface and an end surface, one end of the side surface intersects with the upper bottom surface of the gallium oxide epitaxial layer, and the other end of the side surface intersects with the end surface; the cathode electrode is grown on the side of the gallium oxide substrate layer away from the gallium oxide epitaxial layer; the anode electrode is grown on the upper bottom surface of the gallium oxide epitaxial layer; the P-type semiconductor is n layers, n is the number of layers and n≥2, a first layer of P-type semiconductor is wrapped outside the side surface, and one end of the first layer of P-type semiconductor extends toward the anode electrode until it covers the anode electrode and is connected to the anode electrode, and the first layer of P-type semiconductor The other end of the conductor one extends outward along the end surface; the nth layer of P-type semiconductor one is wrapped around the outside of the n-1th layer of P-type semiconductor one, and one end of the nth layer of P-type semiconductor one extends toward the anode electrode, and extends until it completely wraps the n-1th layer of P-type semiconductor one covering the anode electrode and is connected to the anode electrode; the other end of the nth layer of P-type semiconductor one extends outward along the end surface; wherein the length of the P-type semiconductor one extending outward along the end surface is L, and the length L of the n-layer of the P-type semiconductor one satisfies: the length L1 of the first layer of P-type semiconductor one ≥ the length L2 of the second layer of P-type semiconductor one ≥ ... ≥ the length Ln of the n-th layer of P-type semiconductor one; L represents the length of the P-type semiconductor one extending outward along the end surface, L1 is the length of the first layer of P-type semiconductor one extending outward along the end surface, L1 can approach infinity, L2 is the length of the second layer of P-type semiconductor one extending outward along the end surface, L n The length of the n-th layer of P-type semiconductor extending outward along the end surface forms a stepped structure.

[0005] As a further improvement of the above solution, the length L1 of the first layer of P-type semiconductor 1 is greater than or equal to 3 μm.

[0006] As a further improvement of the above scheme, the concentration N of the n-layer P-type semiconductor 1 satisfies: the concentration N1 of the first layer of P-type semiconductor 1 ≤ the concentration N2 of the second layer of P-type semiconductor 1 ≤ ... ≤ the concentration N of the n-th layer of P-type semiconductor 1 n ; N represents the concentration of P-type semiconductor 1, N1 is the concentration of the first layer of P-type semiconductor 1, N2 is the concentration of the second layer of P-type semiconductor 1, N n is the concentration of the nth layer of P-type semiconductor.

[0007] As a further improvement of the above solution, the gallium oxide diode further includes a second P-type semiconductor, and the second P-type semiconductor is grown between the gallium oxide epitaxial layer and the anode electrode.

[0008] As a further improvement of the above solution, the P-type semiconductor is any one of nickel oxide, copper oxide and tin oxide.

[0009] As a further improvement of the above solution, the P-type semiconductor 1 and the P-type semiconductor 2 are the same P-type semiconductor or different P-type semiconductors.

[0010] As a further improvement of the above solution, the concentration of the gallium oxide substrate layer is 1e18 cm -3 ~1e19cm -3 , with a thickness of 100μm to 1000μm.

[0011] As a further improvement of the above scheme, the concentration of the gallium oxide epitaxial layer is 1e15cm -3 ~5e17cm -3 , thickness is 1μm~100μm.

[0012] As a further improvement of the above solution, the concentration of the P-type semiconductor is 1e15cm -3 ~1e20cm -3 , thickness is 5nm~10μm.

[0013] As a further improvement of the above solution, the growth method of the P-type semiconductor 1 includes any one of magnetron sputtering, electron beam evaporation, and atomic layer deposition.

[0014] A method for preparing a gallium oxide diode comprises the following steps:

[0015] S1, providing gallium oxide wafers;

[0016] S2, growing a cathode metal on the back side of the gallium oxide wafer to form a cathode electrode, so that the cathode electrode forms an ohmic contact with the gallium oxide wafer;

[0017] S3, first patterning the gallium oxide wafer forming the cathode electrode, and then growing an anode metal on the front side of the gallium oxide wafer to form an anode electrode, so that the anode electrode forms a Schottky contact with the gallium oxide wafer; or S3 is: patterning the gallium oxide wafer forming the cathode electrode, and then growing a P-type semiconductor 2 on the front side of the gallium oxide wafer, and then growing an anode metal on the side of the P-type semiconductor 2 away from the gallium oxide wafer to form an anode electrode, so that an ohmic contact is formed between the anode electrode and the P-type semiconductor 2.

[0018] S4, performing self-aligned etching on the corresponding gallium oxide crystal using the anode metal as an etching mask to obtain the gallium oxide wafer with a convex structure;

[0019] S5, patterning the gallium oxide wafer with the convex structure, and then growing a P-type semiconductor 1 on the side surface, wherein one end of the P-type semiconductor 1 extends toward the anode electrode until it covers the anode electrode and is connected to the anode electrode, and the other end extends outward along the end surface, to obtain a gallium oxide wafer with a layer of P-type semiconductor 1 grown thereon;

[0020] S6, patterning the gallium oxide wafer with the first layer of P-type semiconductor one by photolithography, and then growing a second layer of P-type semiconductor one outside the first layer of P-type semiconductor one, with one end of the second layer of P-type semiconductor one extending toward the anode electrode until it covers the anode electrode and is connected to the anode electrode, and the other end extending outward along the end surface, to obtain a gallium oxide wafer with two layers of P-type semiconductor one;

[0021] S7, and so on, the gallium oxide wafer with the n-1th layer of P-type semiconductor 1 grown thereon is patterned, and then an n-th layer of P-type semiconductor 1 is grown on the outside of the n-1th layer of P-type semiconductor, and one end of the n-th layer of P-type semiconductor 1 extends toward the anode electrode until it covers the anode electrode and is connected to the anode electrode, and the other end extends outward along the end surface, so as to obtain a gallium oxide wafer with n-th layer of P-type semiconductor 1 grown thereon, and form the gallium oxide diode.

[0022] As a further improvement of the above solution, in step S1, the gallium oxide wafer is cleaned by organic ultrasonic cleaning, and then the gallium oxide wafer is cleaned by acid.

[0023] As a further improvement of the above scheme, when pickling the gallium oxide wafer, the gallium oxide wafer is pickled with a piranha solution, the pickling time is 15 minutes, and the piranha solution is H2SO4:H2O2:H2O=4:1:1.

[0024] As a further improvement of the above solution, all patterning is performed by photolithography or photolithography followed by etching.

[0025] As a further improvement of the above scheme, in step S4, an inductively coupled plasma etcher is used to perform self-aligned etching with the anode metal as an etching mask, the etching depth is 0.5 μm, the RF power of the inductively coupled plasma etcher is 30 W, the power of the inductively coupled plasma etcher is 900 W, the chamber pressure is 5 mtorr, the flow rate of BCl3 is 35 sccm, the flow rate of Ar is 5 sccm, and the chamber temperature is 20 to 150°C.

[0026] Furthermore, the chamber temperature is 25°C.

[0027] As a further improvement of the above scheme, the concentration of the gallium oxide substrate layer in step S1 is 5e18cm -3 , thickness is 500μm.

[0028] As a further improvement of the above scheme, the concentration of the gallium oxide epitaxial layer is 1e16cm -3 , thickness is 10μm.

[0029] As a further improvement of the above solution, in step S2, 20 nm Ti and 200 nm Au of cathode metal are grown on the back side of the gallium oxide wafer using electron beam evaporation equipment to form a cathode electrode, and the cathode electrode forms an ohmic contact with the gallium oxide wafer.

[0030] As a further improvement of the above solution, in step S3, 20 nm Ni and 200 nm Au of anode metal are grown on the front side of the gallium oxide wafer using electron beam evaporation equipment to form an anode electrode, and the anode electrode forms a Schottky contact with the gallium oxide wafer.

[0031] As a further improvement of the above scheme, in step S3, the gallium oxide wafer is patterned by photolithography, and then a P-type semiconductor 2 is grown on the front side of the gallium oxide wafer by a magnetron sputtering device, and then an anode metal 20nm Ni and 200Au are grown on the side of the P-type semiconductor 2 away from the gallium oxide wafer by an electron beam evaporation device to form an anode electrode, so that an ohmic contact is formed between the anode electrode and the P-type semiconductor 2.

[0032] Furthermore, the P-type semiconductor in step S5, step S6 and step S7 is deposited by magnetron sputtering equipment.

[0033] Furthermore, the power of the magnetron sputtering equipment in step S5 and step S6 is 150 W, the argon flow rate is 36 sccm, the oxygen flow rate is 0 sccm, the reaction chamber pressure is 3.66 mtorr, and the reaction chamber temperature is 25°C.

[0034] Furthermore, the power of the magnetron sputtering equipment in step S7 is 150 W, the argon flow rate is 35.8 sccm, the oxygen flow rate is 1.88 sccm, the reaction chamber pressure is 3.77 mtorr, and the reaction chamber temperature is 25°C.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] (1) The present invention provides a multilayer P-type semiconductor 1, one end of which forms a PN junction with the gallium oxide epitaxial layer. The PN junction can compensate for the charge on the depleted side. Through the depletion effect of the PN junction, the non-ideal factors such as the dangling bonds introduced by etching and the fixed charge introduced by etching damage in the gallium oxide diode can be passivated, thereby reducing the resistance degradation caused by the dangling bonds and improving the stability of the device. At the same time, the other end of the P-type semiconductor 1 is connected to the anode electrode to form an equipotential body, which can promote the depletion of the side PN junction and disperse the high electric field of the device from the original side to the end face, thereby achieving the purpose of reducing the electric field strength of the entire device.

[0037] (2) The length of the multi-layer P-type semiconductor 1 on the end surface decreases from the first layer to the nth layer, so that the multi-layer P-type semiconductor 1 can form a step-like structure on the end surface. The step-like structure enables the high electric field on the side to form an electric field transition along the multi-layer P-type semiconductor 1 on the end surface, so that the electric field distribution on the end surface is relatively uniform, further improving the stability of the manufactured device.

[0038] (3) By setting up multiple layers of P-type semiconductors, the sensitivity of the structure to the thickness and concentration of the P-type semiconductors can be reduced, thereby increasing the device design window and process freedom. At the same time, it can also effectively control the electric field distribution gradient and improve the performance of the manufactured device.

[0039] (4) By setting the concentration of the multilayer P-type semiconductor 1 to different concentration gradients, when the device is reverse biased, the low-concentration P-type semiconductor 1 forms a PN junction with the gallium oxide epitaxial layer to partially or completely deplete the side charge, and at the same time, the high electric field of the device can be dispersed from the side to the end face and bear part of the electric field, thereby reducing the electric field strength of the entire device. At the same time, the high-concentration P-type semiconductor 1 forms an equipotential body with the anode electrode, promoting the depletion of the side PN junction. In addition, when the low-concentration P-type semiconductor 1 is completely depleted, it can bear part of the potential and reduce the electric field in the P-type semiconductor 1.

[0040] (5) The gallium oxide diode of the present invention has a wide design window and process freedom, and can also avoid the damage of the gallium oxide wafer caused by processes such as ion implantation, the device has no loss of conduction performance, and the gallium oxide wafer area utilization rate is high. The device preparation process cost is low, the result is stable and controllable, and the repeatability is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a gallium oxide Schottky diode provided by the present invention.

[0042] Figure 2 A top view of the gallium oxide Schottky diode provided by the present invention.

[0043] Figure 3The present invention is a flow chart of the preparation of the gallium oxide Schottky diode.

[0044] Figure 4 This is a schematic diagram of the gallium oxide PN diode provided by the present invention.

[0045] Figure 5 This is a flow chart for preparing the gallium oxide PN diode of the present invention.

[0046] Figure 6 It is a schematic diagram of a gallium oxide Schottky diode with a mesa terminal structure and the reverse breakdown characteristics of the gallium oxide Schottky diode in the present invention.

[0047] Figure 7 FIG. 4 is a bias stability curve diagram of a gallium oxide Schottky diode with a mesa terminal structure in the prior art.

[0048] Figure 8 This is a bias stability curve diagram of the gallium oxide Schottky diode prepared by the present invention.

[0049] Fig. 9 The electric field distribution diagrams of the non-terminal gallium oxide Schottky diode in the prior art, the mesa-terminated Schottky diode in the prior art, and the Schottky diode prepared by the present invention under a bias voltage of -3100V.

[0050] Fig.10 This is a simulation diagram of the electric field distribution of the gallium oxide Schottky diode prepared by the present invention under a bias voltage of -3100V.

[0051] Fig.11 for Fig.10 An enlarged schematic diagram of part of the structure.

[0052] Fig.12 This is the distribution diagram of the electric field values ​​of P-type semiconductors with different thicknesses at different positions.

[0053] Fig.13 Schematic diagram of a gallium oxide Schottky diode containing a three-layer structure of a P-type semiconductor prepared in the present invention.

[0054] Fig.14 Schematic diagram of a gallium oxide PN diode containing a three-layer P-type semiconductor prepared in the present invention.

[0055] In the figure: 1, gallium oxide substrate layer; 2, gallium oxide epitaxial layer; 21, side surface; 22, end surface; 3, cathode electrode; 4, anode electrode; 5, P-type semiconductor 1; 6, P-type semiconductor 2. DETAILED DESCRIPTION

[0056] The present invention is further described below in conjunction with specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0057] In the description of the present invention, it should be noted that for directional words, such as the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating directions and positional relationships are based on the directions or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and cannot be understood as limiting the specific protection scope of the present invention. The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. The terms "including" and "having" in the specification and claims of the present invention and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device including a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0058] The device in the present invention is a gallium oxide diode, which includes a gallium oxide Schottky diode and a gallium oxide PN diode.

[0059] Example 1

[0060] This embodiment describes a gallium oxide Schottky diode and a method for making the same. In the method for making the same, the P-type semiconductor 1 5 is made of nickel oxide.

[0061] Reference Figure 1-3 As shown, an embodiment of the present invention provides a gallium oxide Schottky diode, including a gallium oxide wafer, a cathode electrode 3, an anode electrode 4 and a P-type semiconductor 5.

[0062] The gallium oxide wafer includes a gallium oxide substrate layer 1 and a gallium oxide epitaxial layer 2. The gallium oxide epitaxial layer 2 is a convex structure, and its lower bottom surface is grown on one side of the gallium oxide substrate layer 1. In this embodiment, the convex structure of the gallium oxide epitaxial layer 2 can be formed into a convex table structure by dry or wet etching. The gallium oxide epitaxial layer 2 is provided with a side surface 21 and an end surface 22, one end of the side surface 21 intersects with the upper bottom surface of the gallium oxide epitaxial layer 2, and the other end of the side surface 21 intersects with the end surface 22.

[0063] The cathode electrode 3 is grown on a side of the gallium oxide substrate layer 1 away from the gallium oxide epitaxial layer 2 .

[0064] The anode electrode 4 is grown on the upper bottom surface of the gallium oxide epitaxial layer 2 .

[0065] The P-type semiconductor 1 5 is n layers, n is the number of layers and n ≥ 2. The first layer of P-type semiconductor 1 is wrapped outside the side surface 21, and one end of the first layer of P-type semiconductor 1 extends toward the anode electrode 4, until it covers the anode electrode 4 and is connected to the anode electrode 4, and the other end of the first layer of P-type semiconductor 1 extends outward along the end surface 22. The n-th layer of P-type semiconductor 1 is wrapped outside the n-1-th layer of P-type semiconductor 1. One end of the n-th layer of P-type semiconductor 1 extends toward the anode electrode 4, until it completely wraps the n-1-th layer of P-type semiconductor 1 covering the anode electrode 4 and is connected to the anode electrode 4, and the other end of the n-th layer of P-type semiconductor 1 extends outward along the end surface 22. Each layer of P-type semiconductor 1 5 can contact the anode electrode 4.

[0066] During the etching process, the side 21 of the gallium oxide epitaxial layer 2 will have dangling bonds and the etching damage will introduce fixed charges. These factors will affect the blocking performance and stability of the gallium oxide diode. In the present invention, the covering structure design of the multi-layer P-type semiconductor 5 can effectively regulate the gradient of the electric field, so that the electric field distribution of the entire device is uniform, and the peak electric field of the device is limited within the device body, so that the peak electric field of the entire device is reduced. Through reasonable structural optimization, the electric field of the entire device can be uniformly distributed, and there will be no local electric field concentration phenomenon. Specifically, one end of the P-type semiconductor 5 forms a PN junction with the gallium oxide epitaxial layer 2, and the PN junction has an initial depletion region, that is, on the contact surface between the two, and the potential on this contact surface is equal. Therefore, after introducing this structure, the potential can be extended along the side 21 to the outside of the end face 22 by utilizing the characteristic that the potential of the PN junction region is equal, thereby achieving the depletion of the charges generated by the side 21 and the end face 22, reducing the peak electric field of the device, and enhancing the device performance. Through the depletion effect of the PN junction, non-ideal factors such as dangling bonds introduced by etching and fixed charges introduced by etching damage in the gallium oxide diode can be passivated, reducing the resistance degradation caused by them and improving the stability of the device.

[0067] At the same time, the other end of the P-type semiconductor 15 is connected to the anode electrode 4 to form an equipotential body. Specifically, the P-type semiconductor 15 is directly connected to the anode metal, and an ohmic contact is formed between the two, that is, there is no potential barrier between the two or the potential barrier is very small, so the P-type semiconductor 15 does not suffer from depletion caused by the anode electrode 4. Therefore, the P-type semiconductor 15 and the anode electrode 4 form an equipotential body, which can promote the lateral extension of the electric field in the horizontal direction. This can promote the depletion of the PN junction on the side 21, and can also disperse the high electric field of the device from the original side 21 to the end face 22, thereby achieving the purpose of reducing the electric field strength of the entire device.

[0068] The length of the P-type semiconductor 1 5 extending outward along the end surface 22 is L, and the length L of the n-layer P-type semiconductor 1 5 satisfies: the length L1 of the first layer of P-type semiconductor 1 ≥ the length L2 of the second layer of P-type semiconductor 1 ≥ ... ≥ the length L of the n-th layer of P-type semiconductor 1 n ; L represents the length of the P-type semiconductor 5 extending outward along the end surface 22, L1 is the length of the first layer of P-type semiconductor 1 extending outward along the end surface 22, L1 can approach infinity, L2 is the length of the second layer of P-type semiconductor 1 extending outward along the end surface 22, L n The length of the n-th layer of P-type semiconductor-1 extending outward along the end face 22 forms a stepped structure. In the present invention, the length of the multi-layer P-type semiconductor-1 5 on the end face 22 is designed to decrease from the first layer to the n-th layer, so that the multi-layer P-type semiconductor-1 5 can form a stepped structure on the end face 22. The stepped structure enables the high electric field of the side 21 to form an electric field transition along the multi-layer P-type semiconductor-1 5 on the end face 22, so that the electric field distribution on the end face 22 is relatively uniform, and the stability of the manufactured device is further improved.

[0069] In this embodiment, the length L1 of the first layer of P-type semiconductor 1 is greater than or equal to 3 μm. When the value of L1 is greater than or equal to 3 μm, the multilayer P-type semiconductor 1 5 in the present invention has a good electric field control effect.

[0070] In this embodiment, the concentration N of the n-layer P-type semiconductor 1 5 satisfies: the concentration N1 of the first layer P-type semiconductor 1 ≤ the concentration N2 of the second layer P-type semiconductor 1 ≤ ... ≤ the concentration N of the n-th layer P-type semiconductor 1 n ; N represents the concentration of P-type semiconductor 15, N1 is the concentration of the first layer of P-type semiconductor 1, N2 is the concentration of the second layer of P-type semiconductor 1, N nis the concentration of the nth layer of P-type semiconductor 1. When the device is reverse biased, the low-concentration P-type semiconductor 15 forms a PN junction with the gallium oxide epitaxial layer 2, and the PN junction can compensate for the charge on the depleted side 21. Through the depletion effect of the PN junction, the high electric field of the device can be dispersed from the side 21 to the end face 22, and the PN junction can also bear part of the electric field, thereby reducing the electric field strength of the entire device. At the same time, the high-concentration P-type semiconductor 15 can form an equipotential body with the anode electrode 4, promote the depletion of the side PN junction, and can also bear part of the potential when the low-concentration P-type semiconductor 15 is completely depleted, reducing the electric field in the low-concentration P-type semiconductor 15, thereby improving the stability of the device.

[0071] The concentration of gallium oxide substrate layer 1 is 1e18 cm -3 ~1e19cm -3 , with a thickness of 100μm to 1000μm.

[0072] The concentration of gallium oxide epitaxial layer 2 is 1e15cm -3 ~5e17cm -3 , thickness is 1μm~100μm.

[0073] The concentration of P-type semiconductor-5 is 1e15cm -3 ~1e20cm -3 , thickness is 5nm~10μm.

[0074] The growth method of the P-type semiconductor 5 includes any one of magnetron sputtering, electron beam evaporation, and atomic layer deposition.

[0075] Among them, magnetron sputtering is a type of physical vapor deposition (PVD). The general sputtering method can be used to prepare multiple materials such as metals, semiconductors, insulators, etc., and has the advantages of simple equipment, easy control, large coating area and strong adhesion.

[0076] Among them, electron beam evaporation is a type of vacuum evaporation coating, which is a method of using an electron beam to directly heat the evaporation material under vacuum conditions, vaporize the evaporation material and transport it to the substrate, and condense it on the substrate to form a thin film.

[0077] Atomic layer deposition is a method that can deposit materials layer by layer on the surface of a substrate in the form of a single atomic film.

[0078] The gallium oxide Schottky diode prepared in this embodiment is a P-type semiconductor 5 having a three-layer structure. The concentration of the gallium oxide substrate layer 1 is 5e18cm -3 , with a thickness of 500 μm. The concentration of the gallium oxide epitaxial layer 2 is 1e16 cm -3 , thickness is 10μm.

[0079] For the P-type semiconductor NiO, the higher the oxygen flow during its growth, the higher the concentration.

[0080] A method for preparing a gallium oxide Schottky diode comprises the following steps:

[0081] (1) The gallium oxide wafer is cleaned by organic ultrasonic cleaning, and then pickled with piranha solution (H2SO4:H2O2:H2O=4:1:1) for 15 minutes.

[0082] (2) Use electron beam evaporation equipment to grow cathode metal 20nmTi and 200nmAu on the back of the chip to form an ohmic contact with the gallium oxide chip.

[0083] (3) Photolithography is used for patterning, and electron beam evaporation is used to grow 20 nm Ni and 200 nm Au anode metals on the front side of the gallium oxide wafer to form a Schottky contact with the gallium oxide wafer.

[0084] (4) Self-aligned etching was performed using an inductively coupled plasma etcher with the anode metal as an etching mask, with an etching depth of 0.5 μm. The RF power of the inductively coupled plasma etcher was 30 W, the ICP power was 900 W, the chamber pressure was 5 mtorr, the BCl3 flow rate was 35 sccm, the Ar flow rate was 5 scm, and the chamber temperature was 25°C.

[0085] (5) Patterning is performed by photolithography, and a first layer of P-type semiconductor NiO is deposited on the side 21 of the gallium oxide epitaxial layer 2 by a magnetron sputtering device. The length of NiO over the anode metal is 8 μm, the length extending on the end surface 22 is 30 μm, and the thickness of NiO is 200 nm. The power of the magnetron sputtering device is 150 W, the argon flow rate is 36 sccm, the oxygen flow rate is 0 sccm, the reaction chamber pressure is 3.66 mtorr, and the reaction chamber temperature is 25°C.

[0086] (6) Patterning is performed by photolithography, and a second layer of P-type semiconductor NiO is deposited on the outside of the first layer of P-type semiconductor using a magnetron sputtering device. The length of NiO over the anode metal is 16 μm, the length extending on the end surface 22 is 20 μm, and the thickness of NiO is 200 nm. The power of the magnetron sputtering device is 150 W, the argon flow rate is 36 sccm, the oxygen flow rate is 0 sccm, the reaction chamber pressure is 3.66 mtorr, and the reaction chamber temperature is 25°C.

[0087] (7) Patterning is performed by photolithography, and a third layer of P-type semiconductor NiO is deposited on the outer side of the second layer of P-type semiconductor one by magnetron sputtering equipment. The length of NiO on the anode metal is 24 μm, the length extending on the end face 22 is 10 μm, and the thickness of NiO is 300 nm. The power of the magnetron sputtering equipment is 150 W, the argon flow rate is 35.8 sccm, the oxygen flow rate is 1.88 sccm, the reaction chamber pressure is 3.77 mtorr, and the reaction chamber temperature is 25° C. Thus, a gallium oxide Schottky diode containing three layers of P-type semiconductor one is obtained.

[0088] like Figure 6 As shown, the breakdown characteristics of the gallium oxide Schottky diode prepared in this embodiment are simulated and compared with the Schottky diode with a mesa terminal in the prior art. Figure 6 It can be seen that the reverse breakdown voltage of the gallium oxide Schottky diode in this embodiment is much greater than that of the Schottky diode with a mesa terminal in the prior art, which indicates that the breakdown characteristics of the gallium oxide Schottky diode prepared in this embodiment are significantly improved.

[0089] Among them, the mesa terminal is to remove the semiconductor material at the edge of the Schottky junction or PN junction to form a mesa structure, which can effectively alleviate the electric field concentration and reduce the peak electric field strength.

[0090] like Figure 7 and Figure 8 As shown, the bias stability of the gallium oxide Schottky diode prepared in this embodiment is simulated and compared with that of the mesa-terminated Schottky diode. Figure 7 and Figure 8 It can be seen that, with the current corresponding to 5V as the criterion, after applying stress for different time periods, the forward conduction current of the mesa terminal Schottky diode gradually decreases, while the current of the gallium oxide Schottky diode prepared in this embodiment is basically stable. It can be seen that the conduction performance of the gallium oxide Schottky diode prepared in this embodiment is more stable than the conduction characteristics of the mesa terminal gallium oxide Schottky diode, and there is basically no degradation.

[0091] like Fig. 9 As shown, the electric field distribution and electric field value of the gallium oxide Schottky diode prepared in this embodiment are simulated and compared with those of a common Schottky diode without terminal and a Schottky diode with table terminal under a bias voltage of -3100V. Fig. 9 (1) is a common Schottky diode without terminal. Fig. 9 (2) is a table-terminated Schottky diode. Fig. 9 (3) is the Schottky diode in this embodiment. Fig. 9 The analysis shows that Fig. 9The peak electric field in (1) is at the interface between the anode electrode 4 and the gallium oxide epitaxial layer 2, and its peak electric field value is about 20.7 MV / cm. Fig. 9 The peak electric field in (2) is concentrated at the mesa terminal, and its peak electric field value is about 10.4 MV / cm. Fig. 9 In (3), due to the presence of a multilayer P-type semiconductor 5, the electric field distribution of the device can be effectively adjusted. As can be seen from the figure, the peak electric field value in this embodiment is about 4.2MV / cm. Compared with ordinary non-terminal Schottky diodes and table-terminated Schottky diodes, the Schottky diode prepared in this embodiment has a more uniform electric field distribution and a greatly reduced electric field peak, thereby improving the performance and stability of the device.

[0092] The present invention obtains the following results by simulating and verifying the above-mentioned structure of the gallium oxide Schottky diode. In this structure, the concentration and thickness of the P-type semiconductor 5 and the gallium oxide epitaxial layer 2 satisfy the following formula: p N p =Eε, where t p N is the total thickness of the first layer to the n-1th layer of the P-type semiconductor 1 in the n-layer P-type semiconductor 1; p is the average value of the concentration of the first layer to the n-1th layer of the P-type semiconductor-5; E is the electric field strength of the gallium oxide epitaxial layer 2; ε is the dielectric constant of the gallium oxide epitaxial layer 2. In the simulation experiment, if the P-type semiconductor-5 is a single-layer structure, the thickness of the P-type semiconductor-5 is too thick or the concentration is too high, the peak electric field point of the device will be located at Fig.11 Too thin or too low a concentration will result in a peak electric field at point A. Fig.11 The peak electric field is at point B. Fig.11 Neither point A nor point B in the device can achieve good electric field regulation. However, in the present invention, through the design of the multi-layer structure P-type semiconductor 5, an electric field transition can be formed at point C and point D, thereby effectively regulating the distribution of the electric field in the device, while also reducing the sensitivity to the concentration of the P-type semiconductor 5.

[0093] pass Fig.10 as well as Fig.11 It can be seen that on the end face 22 of the gallium oxide epitaxial layer 2, from the edge of the anode electrode 4 to the edge of the P-type semiconductor 5 (i.e. Fig.11 The charge of the P-type semiconductor 5 (the thickness of the P-type semiconductor 5 × the concentration) gradually decreases, so that the electric field of the P-type semiconductor 5 presents a gradient change. Correspondingly, the electric field of the gallium oxide epitaxial layer 2 will also be gradient regulated, thereby maximizing the curvature of the edge of the depletion region in the gallium oxide epitaxial layer 2, thereby alleviating the electric field concentration effect to a greater extent.

[0094] In addition, in this embodiment, a related simulation study is also conducted to investigate the electric field of a device with different thickness of a P-type semiconductor 5 along the Fig.11 The distribution of points B, C, D, and A in the middle, the results are as follows Fig.12 As shown. Taking the three-layer P-type semiconductor as an example, Fig.12 It can be seen that the thickness of the first two layers of P-type semiconductor-1 is within a relatively large range of 140nm to 220nm, that is, the total thickness of the first two layers of P-type semiconductor-1 is within a relatively large range of 280nm to 440nm, and the electric field along the BCDA direction has a relatively gentle distribution, and there will not be a large electric field at a certain position. Therefore, the present invention can effectively adjust the electric field distribution of the device through the multi-layer P-type semiconductor-5, and also reduce the sensitivity of the structure to the concentration and thickness of the P-type semiconductor-5.

[0095] It can be seen from this that the gallium oxide Schottky diode in the present invention has a reduced sensitivity to the concentration and thickness of the multilayer P-type semiconductor 5, that is, in the actual preparation process, there is no need to deliberately pursue high-precision control of the concentration and thickness of the P-type semiconductor 5. In other words, the error tolerance of the structure is increased during the preparation process, that is, the design window and degree of freedom of the device during the preparation process are increased.

[0096] Among them, Fig.13 The figure shows a gallium oxide Schottky diode including three layers of P-type semiconductor 1 5. The length of the first layer of P-type semiconductor 1 on the end surface 22 is L1, the length of the second layer of P-type semiconductor 1 on the end surface 22 is L2, and the length of the third layer of P-type semiconductor 1 on the end surface 22 is L3.

[0097] Example 2

[0098] This embodiment describes a gallium oxide PN diode and a method for preparing the same. In the preparation method of this embodiment, both the P-type semiconductor 1 5 and the P-type semiconductor 2 6 are made of nickel oxide.

[0099] Reference Figure 4-5 As shown, an embodiment of the present invention provides a gallium oxide PN diode, including a gallium oxide wafer, a cathode electrode 3, an anode electrode 4, a P-type semiconductor 1 5 and a P-type semiconductor 2 6.

[0100] The gallium oxide wafer includes a gallium oxide substrate layer 1 and a gallium oxide epitaxial layer 2. The gallium oxide epitaxial layer 2 is a convex structure, and its lower bottom surface is grown on one side of the gallium oxide substrate layer 1. In this embodiment, the convex structure of the gallium oxide epitaxial layer 2 can be formed into a convex table structure by dry or wet etching. The gallium oxide epitaxial layer 2 is provided with a side surface 21 and an end surface 22, one end of the side surface 21 intersects with the upper bottom surface of the gallium oxide epitaxial layer 2, and the other end of the side surface 21 intersects with the end surface 22.

[0101] The cathode electrode 3 is grown on a side of the gallium oxide substrate layer 1 away from the gallium oxide epitaxial layer 2 .

[0102] The P-type semiconductor 2 6 is grown on the upper bottom surface of the gallium oxide epitaxial layer 2 .

[0103] The anode electrode 4 is grown on a side of the P-type semiconductor 2 6 away from the gallium oxide epitaxial layer 2 .

[0104] The first P-type semiconductor 5 and the second P-type semiconductor 6 can be the same P-type semiconductor.

[0105] In some other embodiments, the P-type semiconductor 1 5 and the P-type semiconductor 2 6 may be different types of P-type semiconductors.

[0106] The P-type semiconductor 1 5 is n layers, n is the number of layers and n ≥ 2. The first layer of P-type semiconductor 1 is wrapped outside the side surface 21, and one end of the first layer of P-type semiconductor 1 extends toward the anode electrode 4, until it covers the anode electrode 4 and is connected to the anode electrode 4, and the other end of the first layer of P-type semiconductor 1 extends outward along the end surface 22. The n-th layer of P-type semiconductor 1 is wrapped outside the n-1-th layer of P-type semiconductor 1. One end of the n-th layer of P-type semiconductor 1 extends toward the anode electrode 4, until it completely wraps the n-1-th layer of P-type semiconductor 1 covering the anode electrode 4 and is connected to the anode electrode 4, and the other end of the n-th layer of P-type semiconductor 1 extends outward along the end surface 22. Each layer of P-type semiconductor 1 5 can contact the anode electrode 4.

[0107] During the etching process, the side 21 of the gallium oxide epitaxial layer 2 will have dangling bonds and the etching damage will introduce fixed charges. These factors will affect the blocking performance and stability of the gallium oxide diode. In the present invention, the covering structure design of the multi-layer P-type semiconductor 5 can effectively regulate the gradient of the electric field, so that the electric field distribution of the entire device is uniform, and the peak electric field of the device is limited within the device body, so that the peak electric field of the entire device is reduced. Through reasonable structural optimization, the electric field of the entire device can be uniformly distributed, and there will be no local electric field concentration phenomenon. Specifically, one end of the P-type semiconductor 5 forms a PN junction with the gallium oxide epitaxial layer 2, and the PN junction has an initial depletion region, that is, on the contact surface between the two, and the potential on this contact surface is equal. Therefore, after introducing this structure, the potential can be extended along the side 21 to the outside of the end face 22 by utilizing the characteristic that the potential of the PN junction region is equal, thereby achieving the depletion of the charges generated by the side 21 and the end face 22, reducing the peak electric field of the device, and enhancing the device performance. Through the depletion effect of the PN junction, non-ideal factors such as dangling bonds introduced by etching and fixed charges introduced by etching damage in the gallium oxide diode can be passivated, reducing the resistance degradation caused by them and improving the stability of the device.

[0108] At the same time, the other end of the P-type semiconductor 15 is connected to the anode electrode 4 to form an equipotential body. Specifically, the P-type semiconductor 15 is directly connected to the anode metal, and an ohmic contact is formed between the two, that is, there is no potential barrier between the two or the potential barrier is very small, so the P-type semiconductor 15 does not suffer from depletion caused by the anode metal. Therefore, the P-type semiconductor 15 and the anode metal form an equipotential body, which can promote the lateral extension of the electric field in the horizontal direction. This can promote the depletion of the PN junction on the side 21, and can also disperse the high electric field of the device from the original side 21 to the end face 22, thereby achieving the purpose of reducing the electric field strength of the entire device.

[0109] The length of the P-type semiconductor 1 5 extending outward along the end surface 22 is L, and the length L of the n-layer P-type semiconductor 1 5 satisfies: the length L1 of the first layer of P-type semiconductor 1 ≥ the length L2 of the second layer of P-type semiconductor 1 ≥ ... ≥ the length L of the n-th layer of P-type semiconductor 1 n ; L represents the length of the P-type semiconductor 5 extending outward along the end surface 22, L1 is the length of the first layer of P-type semiconductor 1 extending outward along the end surface 22, L2 is the length of the second layer of P-type semiconductor 1 extending outward along the end surface 22, L n The length of the n-th layer of P-type semiconductor 1 extending outward along the end face 22, and the length of the n-th layer of P-type semiconductor 15 extending outward along the end face 22 form a step-like structure. In the present invention, the length of the multi-layer P-type semiconductor 15 on the end face 22 is designed to decrease from the first layer to the n-th layer, so that the multi-layer P-type semiconductor 15 can form a step-like structure on the end face 22. The step-like structure enables the high electric field of the side 21 to form an electric field transition along the multi-layer P-type semiconductor 15 on the end face 22, so that the electric field distribution on the end face 22 is relatively uniform, and the stability of the manufactured device is further improved.

[0110] In this embodiment, the length L1 of the first layer of P-type semiconductor 1 is greater than or equal to 3 μm. When the value of L1 is greater than or equal to 3 μm, the multilayer P-type semiconductor 1 5 in the present invention has a good electric field control effect.

[0111] In this embodiment, the concentration N of the n-layer P-type semiconductor 1 5 satisfies: the concentration N1 of the first layer P-type semiconductor 1 ≤ the concentration N2 of the second layer P-type semiconductor 1 ≤ ... ≤ the concentration N of the n-th layer P-type semiconductor 1 n ; N represents the concentration of P-type semiconductor 15, N1 is the concentration of the first layer of P-type semiconductor 1, N2 is the concentration of the second layer of P-type semiconductor 1, N nis the concentration of the nth layer of P-type semiconductor 1. When the device is reverse biased, the low-concentration P-type semiconductor 15 forms a PN junction with the gallium oxide epitaxial layer 2, and the PN junction can compensate for the charge on the depleted side 21. Through the depletion effect of the PN junction, the high electric field of the device can be dispersed from the side 21 to the end face 22, and the PN junction can also bear part of the electric field, thereby reducing the electric field strength of the entire device. At the same time, the high-concentration P-type semiconductor 15 can form an equipotential body with the anode electrode 4, promote the depletion of the side PN junction, and can also bear part of the potential when the low-concentration P-type semiconductor is completely depleted, reducing the electric field in the low-concentration P-type semiconductor 15, thereby improving the stability of the device.

[0112] The concentration of gallium oxide substrate layer 1 is 1e18 cm -3 ~1e19cm -3 , with a thickness of 100μm to 1000μm.

[0113] The concentration of gallium oxide epitaxial layer 2 is 1e15cm -3 ~5e17cm -3 , thickness is 1μm~100μm.

[0114] The concentration of P-type semiconductor-5 is 1e15cm -3 ~1e20cm -3 , thickness is 5nm~10μm.

[0115] The growth method of the P-type semiconductor 5 includes any one of magnetron sputtering, electron beam evaporation, and atomic layer deposition.

[0116] Among them, magnetron sputtering is a type of physical vapor deposition (PVD). The general sputtering method can be used to prepare multiple materials such as metals, semiconductors, insulators, etc., and has the advantages of simple equipment, easy control, large coating area and strong adhesion.

[0117] Among them, electron beam evaporation is a type of vacuum evaporation coating, which is a method of using an electron beam to directly heat the evaporation material under vacuum conditions, vaporize the evaporation material and transport it to the substrate, and condense it on the substrate to form a thin film.

[0118] Atomic layer deposition is a method that can deposit materials layer by layer on the surface of a substrate in the form of a single atomic film.

[0119] The gallium oxide PN diode prepared in this embodiment is a P-type semiconductor 5 having a three-layer structure. The concentration of the gallium oxide substrate layer 1 is 5e18cm -3 , with a thickness of 500 μm. The concentration of the gallium oxide epitaxial layer 2 is 1e16 cm -3 , thickness is 10μm.

[0120] For the P-type semiconductor NiO, the higher the oxygen flow during its growth, the higher the concentration.

[0121] The preparation method in this embodiment is illustrated by taking a gallium oxide PN diode having three layers of P-type semiconductor 5 as an example.

[0122] A method for preparing a gallium oxide PN diode comprises the following steps:

[0123] (1) The gallium oxide wafer is cleaned by organic ultrasonic cleaning, and then pickled with piranha solution (H2SO4:H2O2:H2O=4:1:1) for 15 minutes.

[0124] (2) Use electron beam evaporation equipment to grow cathode metal 20nmTi and 200nmAu on the back of the chip to form an ohmic contact with the gallium oxide chip.

[0125] (3) Patterning is performed by photolithography, and a magnetron sputtering device is used to grow 100 nm NiO (i.e., P-type semiconductor II 6) on the front side of the gallium oxide wafer. Subsequently, an electron beam evaporation device is used to grow anode metal 20 nm Ni and 200 nm Au on the side of NiO (i.e., P-type semiconductor II 6) away from the gallium oxide epitaxial layer 2 to form an ohmic contact with NiO (i.e., P-type semiconductor II 6). Electron beam evaporation is used to grow anode metal 20 nm Ni and 200 nm Au on the front side of the gallium oxide wafer to form a Schottky contact with the gallium oxide wafer.

[0126] (4) Self-aligned etching was performed using an inductively coupled plasma etcher with the anode metal as an etching mask, with an etching depth of 0.5 μm. The RF power of the inductively coupled plasma etcher was 30 W, the ICP power was 900 W, the chamber pressure was 5 mtorr, the BCl3 flow rate was 35 sccm, the Ar flow rate was 5 scm, and the chamber temperature was 25°C.

[0127] (5) Patterning is performed by photolithography, and a first layer of P-type semiconductor NiO is deposited on the side 21 of the gallium oxide epitaxial layer 2 by a magnetron sputtering device. The length of NiO over the anode metal is 8 μm, the length extending on the end surface 22 is 30 μm, and the thickness of NiO is 200 nm. The power of the magnetron sputtering device is 150 W, the argon flow rate is 36 sccm, the oxygen flow rate is 0 sccm, the reaction chamber pressure is 3.66 mtorr, and the reaction chamber temperature is 25°C.

[0128] (6) Patterning is performed by photolithography, and a second layer of P-type semiconductor NiO is deposited on the outside of the first layer of P-type semiconductor using a magnetron sputtering device. The length of NiO over the anode metal is 16 μm, the length extending on the end surface 22 is 20 μm, and the thickness of NiO is 200 nm. The power of the magnetron sputtering device is 150 W, the argon flow rate is 36 sccm, the oxygen flow rate is 0 sccm, the reaction chamber pressure is 3.66 mtorr, and the reaction chamber temperature is 25°C.

[0129] (7) Patterning is performed by photolithography, and a third layer of P-type semiconductor NiO is deposited on the outer side of the second layer of P-type semiconductor 1 by magnetron sputtering equipment. The length of NiO on the anode metal is 24 μm, the length extending on the end surface 22 is 10 μm, and the thickness of NiO is 300 nm. The power of the magnetron sputtering equipment is 150 W, the argon flow rate is 35.8 sccm, the oxygen flow rate is 1.88 sccm, the reaction chamber pressure is 3.77 mtorr, and the reaction chamber temperature is 25° C. Thus, a gallium oxide Schottky diode containing three layers of P-type semiconductor 15 is obtained.

[0130] Among them, Fig.14 The figure shows a gallium oxide PN diode including three layers of P-type semiconductor 1 5. The length of the first layer of P-type semiconductor 1 on the end surface 22 is L1, the length of the second layer of P-type semiconductor 1 on the end surface 22 is L2, and the length of the third layer of P-type semiconductor 1 on the end surface 22 is L3. It can be seen from the figure that L1>L2>L3.

[0131] The above describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention. These changes and improvements fall within the scope of the present invention to be protected. The scope of protection claimed by the present invention is defined by the attached claims and their equivalents.

Claims

1. A gallium oxide diode, characterized in that: It includes: A gallium oxide wafer, comprising a gallium oxide substrate layer (1) and a gallium oxide epitaxial layer (2); the gallium oxide epitaxial layer (2) is a convex structure, and its lower bottom surface is grown on one side of the gallium oxide substrate layer (1); the gallium oxide epitaxial layer (2) is provided with a side surface (21) and an end surface (22); one end of the side surface (21) intersects with the upper bottom surface of the gallium oxide epitaxial layer (2), and the other end of the side surface (21) intersects with the end surface (22); A cathode electrode (3) grown on a side of the gallium oxide substrate layer (1) away from the gallium oxide epitaxial layer (2); an anode electrode (4) grown on the upper bottom surface of the gallium oxide epitaxial layer (2); A P-type semiconductor (5), wherein the P-type semiconductor (5) is n layers, n being the number of layers and n≥2, a first layer of the P-type semiconductor (1) is wrapped outside the side surface (21), and one end of the first layer of the P-type semiconductor (1) extends toward the anode electrode (4), until it covers the anode electrode (4) and is connected to the anode electrode (4), and the other end of the first layer of the P-type semiconductor (1) extends outward along the end surface (22); an n-th layer of the P-type semiconductor (1) is wrapped outside the n-1-th layer of the P-type semiconductor (1), and one end of the n-th layer of the P-type semiconductor (1) extends toward the anode electrode (4), until it completely covers the n-1-th layer of the P-type semiconductor (1) covering the anode electrode (4) and is connected to the anode electrode (4); the other end of the n-th layer of the P-type semiconductor (1) extends outward along the end surface (22); The length of the P-type semiconductor (5) extending outward along the end surface (22) is L, and the length L of the n-layer P-type semiconductor (1) satisfies: the length L1 of the first layer of P-type semiconductor (1) ≥ the length L2 of the second layer of P-type semiconductor (1) ≥ ... ≥ the length L of the n-th layer of P-type semiconductor (1) n ; L represents the length of the P-type semiconductor (5) extending outward along the end surface (22), L1 is the length of the first layer of P-type semiconductor (5) extending outward along the end surface (22), L2 is the length of the second layer of P-type semiconductor (5) extending outward along the end surface (22), L n The length of the n-th layer of P-type semiconductor (5) extending outward along the end surface (22) forms a stepped structure.

2. The gallium oxide diode according to claim 1, characterized in that: The length L1 of the first P-type semiconductor layer 1 is greater than or equal to 3 μm.

3. The gallium oxide diode according to claim 1, characterized in that: The concentration N of the n-layer P-type semiconductor 1 satisfies: the concentration N1 of the first layer of P-type semiconductor 1 ≤ the concentration N2 of the second layer of P-type semiconductor 1 ≤ ... ≤ the concentration N of the n-th layer of P-type semiconductor 1 n ; N represents the concentration of P-type semiconductor 1, N1 is the concentration of the first layer of P-type semiconductor 1, N2 is the concentration of the second layer of P-type semiconductor 1, N n is the concentration of the nth layer of P-type semiconductor.

4. The gallium oxide diode according to claim 1, characterized in that: The gallium oxide diode further comprises a second P-type semiconductor (6), and the second P-type semiconductor (6) is grown between the gallium oxide epitaxial layer (2) and the anode electrode (4).

5. The gallium oxide diode according to claim 4, characterized in that: The P-type semiconductor one (5) is any one of nickel oxide, copper oxide, and tin oxide; and / or the P-type semiconductor one (5) and the P-type semiconductor two (6) are the same P-type semiconductor or different P-type semiconductors.

6. The gallium oxide diode according to claim 1, characterized in that: The concentration of the gallium oxide substrate layer (1) is 1e18 cm -3 ~1e19cm -3 , with a thickness of 100 μm to 1000 μm; and / or, the concentration of the gallium oxide epitaxial layer (2) is 1e15 cm -3 ~5e17cm -3 , thickness is 1μm~100μm.

7. The gallium oxide diode according to claim 1, characterized in that: The concentration of the P-type semiconductor (5) is 1e15 cm -3 ~1e20cm -3 , a thickness of 5 nm to 10 μm, and / or the growth method of the P-type semiconductor (5) includes any one of magnetron sputtering, electron beam evaporation, and atomic layer deposition.

8. A method for preparing a gallium oxide diode, characterized in that: The following steps are involved: S1, providing gallium oxide wafers; S2, growing cathode metal on the back side of the gallium oxide wafer to form a cathode electrode (3), so that the cathode electrode (3) forms an ohmic contact with the gallium oxide wafer; S3, first patterning the gallium oxide wafer forming the cathode electrode (3), then growing an anode metal on the front side of the gallium oxide wafer to form an anode electrode (4), so that the anode electrode (4) forms a Schottky contact with the gallium oxide wafer; or S3 is: patterning the gallium oxide wafer forming the cathode electrode (3), then growing a P-type semiconductor 2 (6) on the front side of the gallium oxide wafer, and then growing an anode metal on the side of the P-type semiconductor 2 (6) away from the gallium oxide wafer to form an anode electrode (4), so that an ohmic contact is formed between the anode electrode (4) and the P-type semiconductor 2 (6); S4, performing self-aligned etching on the corresponding gallium oxide crystal using the anode metal as an etching mask to obtain the gallium oxide wafer with a convex structure; S5, patterning the gallium oxide wafer with the convex structure, and then growing a P-type semiconductor (5) on the side surface (21), wherein one end of the P-type semiconductor (5) extends toward the anode electrode (4) until it covers the anode electrode (4) and is connected to the anode electrode (4), and the other end extends outward along the end surface (22), thereby obtaining a gallium oxide wafer with a layer of P-type semiconductor (1) grown thereon; S6, patterning the gallium oxide wafer on which the first layer of P-type semiconductor one is grown, and then growing a second layer of P-type semiconductor one on the outer side of the first layer of P-type semiconductor one, wherein one end of the second layer of P-type semiconductor one extends toward the anode electrode (4) until it covers the anode electrode (4) and is connected to the anode electrode (4), and the other end extends outward along the end surface (22), thereby obtaining a gallium oxide wafer on which two layers of P-type semiconductor one are grown; S7, and so on, the gallium oxide wafer with the n-1th layer of P-type semiconductor one grown thereon is patterned, and then the nth layer of P-type semiconductor one is grown on the outside of the n-1th layer of P-type semiconductor, with one end of the nth layer of P-type semiconductor one extending toward the anode electrode (4) until it covers the anode electrode (4) and is connected to the anode electrode (4), and the other end extending outward along the end surface (22), thereby obtaining a gallium oxide wafer with n layers of P-type semiconductor one grown thereon, and forming a gallium oxide diode as described in any one of claims 1 to 7.

9. The method for preparing a gallium oxide diode according to claim 8, characterized in that: In the step S1, the gallium oxide wafer is subjected to organic ultrasonic cleaning, and then the gallium oxide wafer is subjected to acid cleaning; And / or, in step S4, an inductively coupled plasma etcher is used to perform self-aligned etching using the anode metal as an etching mask, the etching depth is 0.5 μm, the RF power of the inductively coupled plasma etcher is 30 W, the power of the inductively coupled plasma etcher is 900 W, the chamber pressure is 5 mtorr, the flow rate of BCl3 is 35 sccm, the flow rate of Ar is 5 sccm, and the chamber temperature is 20 to 150° C.; and / or, the concentration of the gallium oxide substrate layer (1) is 5e18 cm -3 , thickness is 500 μm; And / or, the concentration of the gallium oxide epitaxial layer (2) is 1e16cm -3 , thickness is 10μm.

10. The method for preparing a gallium oxide diode according to claim 8, characterized in that: When pickling the gallium oxide wafer, the gallium oxide wafer is pickled with a piranha solution for 15 minutes. The piranha solution is H2SO4:H2O2:H2O=4:1:1.

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