Chip integrated packaging technology

Abstract

The present invention provides a chip integrated packaging process, which uses a chip mounter to place multiple chips on a packaging substrate at intervals and fix them with a fixing material; and electrically connects all pins of the multiple chips to the pins of the packaging substrate. The present invention integrates and packages multiple chips into one chip, thereby reducing the packaging cost while meeting the chip application requirements and improving the applicability and stability of the packaged chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a chip integrated packaging process. Background Art

[0002] With the rapid development of science and technology, semiconductor power devices use multiple chips more and more frequently. The existing technology generally uses multiple chips to be connected separately, which uses a large number of chips, occupies a large space, has complex wiring, and requires high drawing skills of engineers. In order to meet the requirements of chip concentration, electronic engineers began to use chip sealing technology to seal multiple chips together as sealed chips, and lead the pins to the outside of the sealed chip as sealed pins. The pins that multiple chips should have are not led out, and the parameters cannot be adjusted according to the needs of actual application scenarios, resulting in a narrow range of use for sealed chips and easy waste of resources. At the same time, the stability of sealed chips is not high, and internal components are easy to burn when the external circuit changes. Therefore, it is a technical problem that needs to be solved at present to reduce the packaging cost while meeting application requirements and make the packaged chips more widely used and more stable in performance. Summary of the invention

[0003] The present invention provides a chip integrated packaging process for solving the problem in the prior art that, while meeting application requirements, resources are easily wasted and the packaged chip cannot be more widely used or have more stable performance.

[0004] The present invention provides a chip integrated packaging process, which uses a chip mounter to place multiple chips on a packaging substrate at intervals and fix them with fixing materials; and electrically connects all pins of the multiple chips with pins of the packaging substrate.

[0005] Optionally, a protective material is filled on the packaging substrate; and the packaged chip is inspected and tested.

[0006] Optionally, chip parameters are adjusted according to board layout requirements, where the chip parameters include the number of chips, chip models, chip positions and / or chip specifications after packaging.

[0007] Optionally, the number of pins of the package substrate is not less than the sum of the pins of the multiple chips.

[0008] Optionally, external circuit connection is performed through pins of the package substrate; the external circuit is adjusted according to preset requirements.

[0009] Optionally, the multiple chips include a half-bridge driver chip and two MOS tubes.

[0010] Optionally, the packaged chip has a side length of 6.95-7.05 mm and a thickness of 0.7-0.8 mm.

[0011] Optionally, the input voltage range of the packaged chip includes: 0-400V.

[0012] Optionally, the inspection and testing include appearance inspection, pin arrangement inspection, electrical performance test, functional test, reliability test and safety test.

[0013] Optionally, the fixing material includes conductive silver paste.

[0014] It can be seen from the above technical solution that the present invention includes: using a chip mounter to place multiple chips on a packaging substrate at intervals and fix them with a fixing material; and electrically connecting all pins of the multiple chips to the pins of the packaging substrate. The present invention integrates and packages multiple chips into one chip, thereby reducing the packaging cost while meeting the chip application requirements and improving the applicability and stability of the packaged chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of a chip integrated packaging process according to an embodiment of the present invention;

[0016] Figure 2 A circuit diagram of a non-integrated packaged chip provided by an embodiment of the present invention;

[0017] Figure 3 A circuit diagram of an integrated package chip provided by an embodiment of the present invention;

[0018] Figure 4 A schematic diagram of the molding dimensions of a chip integrated package provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] Figure 1 FIG. 1 is a schematic diagram showing a process flow of a chip integrated packaging process provided by an embodiment of the present invention, such as Figure 1 As shown, the packaging process of this embodiment includes:

[0021] 110. Use a chip mounter to place multiple chips on the packaging substrate at intervals and fix them with fixing materials;

[0022] 120. Electrically connect all pins of the multiple chips and pins of the packaging substrate.

[0023] In a specific embodiment, after the circuit engineer has drawn the diagram, he uses a chip mounter to mount multiple chips on the package substrate according to the intervals in the circuit diagram, and uses a fixing material to fix the chips, wherein the fixing material includes conductive silver glue, which is an adhesive with certain conductive properties after curing or drying. The conductive particles are combined together through the bonding effect of the matrix resin to form a conductive path to achieve conductive connection of the bonded materials. When laying out the circuit, the chip spacing must meet the assembly requirements. When processing the chip using the general surface mount technology (SMT), it is necessary to consider the certain errors in the machine mounting. For the convenience of maintenance and visual appearance inspection, the adjacent chips should not be too close, and a certain safety distance should be left. At the same time, the chip should also be kept away from the edge of the substrate.

[0024] Figure 2 FIG. 1 shows a circuit diagram of a non-integrated packaged chip provided by an embodiment of the present invention. Figure 3 FIG. 1 shows a circuit diagram of an integrated package chip provided by an embodiment of the present invention, such as Figure 2 As shown, the multiple chips may include a half-bridge driver chip and two MOS tubes. The half-bridge driver circuit drives two MOS tubes connected in series and is composed of two drivers, one driver is used to control the upper MOS tube, and the other driver is used to control the lower MOS tube. By alternately controlling the two drivers, the half-bridge driver circuit can achieve forward and reverse driving of the two MOS tubes, thereby achieving signal amplification and output. Among them, the driver chip includes 8 pins, the two MOS tubes have a total of 6 pins, and the sum of the pins of the multiple chips is 14 pins.

[0025] like Figure 3 As shown, Figure 2 The half-bridge driver chip and two MOS tubes are integrated into a package. The packaged chip has a total of 20 pins. Figure 2 The 14 pins in the package increase the number of pins of the chip, and there is no need to change the external circuits of the driver chip and the MOS tube when using the packaged chip, making the integrated packaged chip more application scenarios and more applicable.

[0026] Figure 4 The schematic diagram of the chip integrated package molding size provided by an embodiment of the present invention is shown, and from left to right are the top view, bottom view and side view. The integrated package chip specifications are related to the number of chips and the chip type. Under the premise of meeting the safe distance and packaging requirements of the packaged chips, the package chip specifications and the placement of the internal chips are adjusted according to user needs. Figure 3 The half-bridge driver chip and two MOS tubes are integrated into a package, and the package size is as follows Figure 4As shown, the packaged chip includes three substrates, the side length D1 of substrate 1 is 2.9-3.0mm, and E1 is 2.9-3.0mm; the length E2 of substrate 2 is 3.45-3.55mm, and the width D2 is 2.9-3.0mm; the length D3 of substrate 3 is 2.95-3.05mm, and the width E3 is 1.55-1.65mm; the interval L1 between substrate 1 and substrate 3 is 1.42-1.52mm; the side length of the packaged chip is 6.95-7.05mm, the height A is 0.7-0.8mm; the pin width b is 0.35-0.45mm. Packaging multiple chips into one chip not only meets the application requirements but also reduces the packaging cost. All pins of multiple chips are electrically connected to the pins of the package substrate, and the chip pins are soldered to the pins on the substrate with gold wire or aluminum wire. Among them, the number of pins of the packaging substrate is greater than or equal to the sum of the pins of multiple chips. More pins can be packaged in a smaller volume, which effectively solves the problem of pin limitation in applications with high pin requirements and small board space.

[0027] In a specific embodiment, after the chip pins and the package substrate pins are electrically connected, a package filling material, such as epoxy resin, is filled on the package substrate to protect the substrate and protect the chip from the external environment. After the package is completed, the packaged chip needs to be strictly inspected and tested to ensure that the quality and performance of the packaged product meet the requirements. The inspection and testing may include appearance inspection, pin arrangement inspection, electrical performance test, function test, reliability test and safety test.

[0028] First, perform an overall appearance inspection of the chip to check whether the chip has obvious damage, loose solder joints, or surface oxidation to prevent the chip from being damaged or of poor quality; check whether the pin arrangement of the integrated chip is correct; use professional testing instruments to test the chip's electrical parameters such as current, voltage, and frequency. If the test results are consistent with the specified range, it means that the chip's electrical performance is good; design a series of test cases that cover all functions of the chip and verify the chip's performance in different working modes; test the chip under different environmental conditions to evaluate the chip's life and stability. Reliability tests include temperature cycling tests, humidity tests, vibration tests, etc.; simulate hacker attacks, vulnerability scans, encryption and decryption tests, and other tests to evaluate the chip's security features.

[0029] In a specific embodiment, the chip package uses a high-voltage resistant material, and the input voltage range of the packaged chip includes: 0-400V. It is compatible with MOS tube parameters from different manufacturers and is adapted to the products of most current power tube manufacturers. It is widely used in multi-chip integration in the fields of high-speed hair dryers, ceiling fans, fans, vacuum cleaners, water pumps, etc.

[0030] Different integrated chips will be used for different manufacturers' needs. For example, the control circuit chip in the fan can be integrated into one chip, and the speed regulation circuit chip in the high-speed air duct can be integrated into one chip, which brings great convenience and reliable stability to design and development. According to different application scenarios of integrated chips, such as fans and sensors, and different circuits, such as control circuits and signal processing circuits, the number and model of integrated chips are adjusted according to the layout requirements. For example, a driver chip and two MOS tubes can be adjusted to a DFN7X7-20L integrated chip according to the layout requirements. Because the sizes and models of various chips are different, the chip position and chip specifications after packaging need to be adjusted accordingly during the packaging process. The chip position includes the relative position and mounting direction of the internal chips, and the chip specifications include the size and thickness of the chip after packaging.

[0031] In a specific embodiment, the pins of the chip inside the package are all connected to the pins of the package substrate, and there is no electrical connection between the internal chips. The external circuit is connected through the pins of the package substrate, and the external circuit is adjusted according to the preset requirements of the application scenario, including the resistance, capacitance, inductance and circuit connection of the external circuit. The internal routing of the package will produce routing inductance, plus the resistance and other effects caused by other routing factors. For example, different MOS tubes in the package will have different gate capacitance and driving voltage. It is necessary to adjust the resistance, capacitance and / or inductance of the driving circuit accordingly, and externalize the connection circuit. The stability and applicability of the packaged chip can be improved by adjusting the external circuit.

[0032] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0033] Those skilled in the art will appreciate that the foregoing embodiments are merely intended to illustrate the technical solutions of the present invention rather than to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that the technical solutions described in the foregoing embodiments may be modified or some or all of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope defined by the claims of the present invention.

Claims

1. A chip integrated packaging process, characterized in that: include: Use a chip mounter to place multiple chips on the packaging substrate at intervals and fix them with fixing materials; Adjust chip parameters according to board layout requirements. The chip parameters include the number of chips, chip model, chip position and / or chip specifications after packaging; Electrically connecting all pins of a plurality of chips to pins of a packaging substrate, wherein the plurality of chips include a half-bridge driver chip and two MOS tubes; The external circuit is connected through the pins of the packaging substrate, and the external circuit is adjusted according to the preset requirements. The pins of the packaging substrate are not less than the sum of the pins of multiple chips.

2. The chip integrated packaging process according to claim 1, characterized in that: Also includes: Filling a protective material on the packaging substrate; Inspect and test the packaged chips.

3. The chip integrated packaging process according to claim 1, characterized in that: Also includes: The packaged chip has a side length of 6.95-7.05mm and a thickness of 0.7-0.8mm.

4. The chip integrated packaging process according to claim 1, characterized in that: Also includes: The input voltage range of the packaged chip includes: 0-400V.

5. The chip integrated packaging process according to claim 2, characterized in that: Inspection and testing include appearance inspection, pin arrangement inspection, electrical performance test, functional test, reliability test and safety test.

6. The chip integrated packaging process according to claim 1, characterized in that: The fixing material includes conductive silver glue.

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