A Start and Stop Identification Circuit and Method for I2C Bus

Abstract

The present invention discloses a Start and Stop identification circuit and method of an I2C bus, comprising a first register F1, a second register F2, a latch SR, a NAND gate A1, a NAND gate A2, a NAND gate I1, a NAND gate I2, a NAND gate I3 and a delay device Delay. When a signal SCL is at a low level, the circuit does not identify Start and Stop, and uses the signal SCL as an output signal for resetting the two registers Start and Stop. The present invention can realize the identification of Start and Stop by using only two signals SDC and SCL, without using a high-speed clock, and the dynamic power consumption of the circuit is extremely low when working. Compared with the prior art, the present invention adopts a different solution to realize a similar solution of realizing the identification of Start and Stop without using a high-speed clock, and the present invention has fewer registers and logic gates, and a simpler circuit structure.

Description

Technical Field

[0001] The present invention relates to a signal recognition circuit and method, in particular to a Start and Stop recognition circuit and method of an I2C bus, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] The use of I2C circuits has become very popular, and there are various ways to implement them. Figure 2 As shown in the figure, the Start and Stop waveforms defined by the I2C protocol are shown. Usually, the chip needs a high-speed clock to sample the SDA and SCL signal lines of the I2C to identify the Start and Stop of the protocol. However, the high-speed clock will cause high dynamic power consumption when the circuit is working.

[0003] Therefore, the prior art US8878569B1 discloses a start and stop identification circuit and method, in which only two signals, SDC and SCL, are used to realize the start and stop identification, without the need for a high-speed clock, thereby greatly reducing the dynamic power consumption of the circuit during operation. However, the circuit structure in this solution is still relatively complex. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a Start and Stop identification circuit and method for an I2C bus, which does not require a high-speed clock and has a simpler circuit structure.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A Start and Stop recognition circuit of an I2C bus comprises a first register F1, a second register F2, a latch SR, a NAND gate A1, a NAND gate A2, a NAND gate I1, a NAND gate I2, a NAND gate I3 and a delay device Delay, wherein an input end of the NAND gate I1 is connected to a clk end of the second register F2 with a signal SDA, a first input end of the NAND gate A1 and a first input end of the NAND gate A2 are connected to a signal SCL, an output end of the NAND gate I1 is connected to the clk end of the first register F1, and a D end of the first register F1 and a D end of the second register F2 are connected Power supply VDD, the Q end of the first register F1 is connected to the S end of the latch SR, the R end of the latch SR is connected to the input end of the NOT gate I2, the Q end of the second register F2 and one end of the delay device Delay, the output end of the NOT gate I2 is connected to the second input end of the NOT gate A1, the output end of the NOT gate A1 is connected to the CLR end of the first register F1, the output end of the NOT gate A2 is connected to the CLR end of the second register F2, the other end of the delay device Delay is connected to the input end of the NOT gate I3, and the output end of the NOT gate I3 is connected to the second input end of the NOT gate A2.

[0007] Furthermore, the first register F1 and the second register F2 are D flip-flops.

[0008] Furthermore, the latch SR is a RS trigger.

[0009] Furthermore, the delay time of the delay device Delay is 20ns.

[0010] Furthermore, the Q terminal of the latch SR outputs a signal FLAG. When the signal FLAG is at a high level, it indicates that the transmission is in progress. When the signal FLAG is at a low level, it indicates that the transmission has ended.

[0011] A method for identifying a Start and Stop identification circuit of an I2C bus comprises the following steps:

[0012] When the signal SCL is at a low level, the low level of the signal SCL resets the first register F1 and the second register F2 respectively through the NAND gate A1 and the NAND gate A2;

[0013] When the signal SCL is at a high level, the Start and Stop recognition circuits of the I2C bus can recognize the Start and Stop signals;

[0014] When the signal SDA changes from high level to low level, the signal SDA passing through the NOT gate I1 will send out a rising edge from low level to high level, and the rising edge triggers the first register F1 to output a high level, that is, the signal Start changes to high; the high level of the signal Start will trigger the latch SR to output a high level, that is, the signal FLAG changes to high, and the signal Start recognition is completed; at the same time, the clk terminal of the second register F2 will only have a falling edge from high level to low level, and will not trigger any changes;

[0015] When the signal SDA changes from low level to high level, the rising edge from low level to high level triggers the second register F2 to output high level, that is, the signal Stop changes to high level; the high level of the signal Stop resets the first register F1 after passing through the NOT gate I2 and the NAND gate A1, and changes the signal Start to low level; at the same time, the high level of the signal Stop will trigger the latch SR to output low level, that is, the signal FLAG changes to low level, and the signal Stop recognition is completed; at the same time, the clk end of the first register F1 will only have a falling edge from high level to low level, and will not trigger any changes;

[0016] The delay device delay will make the high level of the signal Stop last for 20ns, and then reset the second register F2 through the NOT gate I3 and the NAND gate A2, and change the signal Stop to a low level, so as to ensure that the recognition of the next signal Start will start again after 20ns;

[0017] When the signal FLAG is at a high level, it indicates that the transmission is in progress; when FLAG is at a low level, it indicates that the transmission has ended.

[0018] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a Start and Stop identification circuit and method for an I2C bus, which can realize the identification of Start and Stop by using only two signals, SDC and SCL, without using a high-speed clock, and the dynamic power consumption of the circuit is extremely low when working; when the signal SCL is at a low level, the circuit does not recognize Start and Stop, and uses the signal SCL as an output signal for resetting the two registers, Start and Stop; compared with the prior art, the present invention adopts a different scheme to realize a similar scheme of realizing the identification of Start and Stop without using a high-speed clock, and the present invention has fewer registers and logic gates, and a simpler circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The present invention is a schematic diagram of a Start and Stop identification circuit of an I2C bus.

[0020] Figure 2 It is a schematic diagram of the Start and Stop waveforms defined by the I2C protocol in the prior art. DETAILED DESCRIPTION

[0021] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0022] like Figure 1As shown, a Start and Stop identification circuit of an I2C bus of the present invention comprises a first register F1, a second register F2, a latch SR, a NAND gate A1, a NAND gate A2, a NAND gate I1, a NAND gate I2, a NAND gate I3 and a delay device Delay, an input end of the NAND gate I1 and a clk end of the second register F2 are connected to a signal SDA, a first input end of the NAND gate A1 and a first input end of the NAND gate A2 are connected to a signal SCL, an output end of the NAND gate I1 is connected to the clk end of the first register F1, and the first register F1 and the second register F2 are connected to the clk end of the first register F1 and the second register F2. The D end is connected to the power supply VDD, the Q end of the first register F1 is connected to the S end of the latch SR, the R end of the latch SR is connected to the input end of the NOT gate I2, the Q end of the second register F2 and one end of the delay device Delay, the output end of the NOT gate I2 is connected to the second input end of the NOT gate A1, the output end of the NOT gate A1 is connected to the CLR end of the first register F1, the output end of the NOT gate A2 is connected to the CLR end of the second register F2, the other end of the delay device Delay is connected to the input end of the NOT gate I3, and the output end of the NOT gate I3 is connected to the second input end of the NOT gate A2.

[0023] The first register F1 and the second register F2 are D flip-flops, and the latch SR is an RS flip-flop.

[0024] The delay time of the delay device Delay is 20ns.

[0025] The Q terminal of the latch SR outputs a signal FLAG. When the signal FLAG is at a high level, it indicates that the transmission is in progress. When the signal FLAG is at a low level, it indicates that the transmission has ended.

[0026] A method for identifying a Start and Stop identification circuit of an I2C bus comprises the following steps:

[0027] When the signal SCL is at a low level, the low level of the signal SCL resets the first register F1 and the second register F2 respectively through the NAND gate A1 and the NAND gate A2, thereby ensuring that the data is not mistakenly identified as Start and Stop when the I2C is sampling data.

[0028] When the signal SCL is at a high level, the Start and Stop recognition circuits of the I2C bus can recognize the Start and Stop signals.

[0029] When the signal SDA changes from a high level to a low level, the signal SDA passing through the NOT gate I1 will send out a rising edge from a low level to a high level, and the rising edge triggers the first register F1 to output a high level, that is, the signal Start becomes high; the high level of the signal Start will trigger the latch SR to output a high level, that is, the signal FLAG becomes high, and the signal Start recognition is completed; at the same time, the clk end of the second register F2 will only have a falling edge from a high level to a low level, and will not trigger any changes.

[0030] When the signal SDA changes from low level to high level, the rising edge from low level to high level triggers the second register F2 to output high level, that is, the signal Stop changes to high level; the high level of the signal Stop resets the first register F1 after passing through the NOT gate I2 and the NAND gate A1, and changes the signal Start to low level; at the same time, the high level of the signal Stop will trigger the latch SR to output a low level, that is, the signal FLAG changes to a low level, and the signal Stop recognition is completed; at the same time, the clk end of the first register F1 will only have a falling edge from high level to low level, and will not trigger any changes.

[0031] The delay device delay will make the high level of the signal Stop last for 20ns, and then reset the second register F2 through the NOT gate I3 and the NAND gate A2, and change the signal Stop to a low level, thereby ensuring that the recognition of the next signal Start will be restarted after 20ns. At the same time, it also ensures that the high level of the R end of the latch SR will last longer than the high level of the S end, thereby ensuring that the latch SR will be reset to 0 after a brief conflict when the R and S ends are both high, that is, the signal FLAG becomes 0. The delay time of 20ns cannot be too small, otherwise the duration of the high level of the signal Stop will be too short, and ultimately the reset will fail. The delay time of 20ns cannot be too long, otherwise the next signal Start will not be recognized.

[0032] When the signal FLAG is at a high level, it indicates that the transmission is in progress; when the signal FLAG is at a low level, it indicates that the transmission has ended. The circuit and method finally realize the function of identifying Start and Stop without relying on an external clock, using only the two original signals SCL and SDA.

[0033] The present invention provides a Start and Stop recognition circuit and method for an I2C bus. The recognition of Start and Stop can be realized by using only two signals, SDC and SCL, without using a high-speed clock, and the dynamic power consumption of the circuit is extremely low when the circuit is working. When the signal SCL is at a low level, the circuit does not recognize Start and Stop, and uses the signal SCL as an output signal for resetting the two registers Start and Stop. Compared with the prior art, the present invention adopts a different scheme to realize a similar scheme of realizing the recognition of Start and Stop without using a high-speed clock, and the present invention has fewer registers and logic gates, and a simpler circuit structure.

[0034] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A Start and Stop recognition circuit for an I2C bus, characterized in that: The invention comprises a first register F1, a second register F2, a latch SR, a NAND gate A1, a NAND gate A2, a NAND gate I1, a NAND gate I2, a NAND gate I3 and a delay device Delay, wherein the input end of the NAND gate I1 and the clk end of the second register F2 are connected to a signal SDA, the first input end of the NAND gate A1 and the first input end of the NAND gate A2 are connected to a signal SCL, the output end of the NAND gate I1 is connected to the clk end of the first register F1, the D end of the first register F1 and the D end of the second register F2 are connected to a power supply VDD, and the first register The Q end of F1 is connected to the S end of the latch SR, the R end of the latch SR is connected to the input end of the NOT gate I2, the Q end of the second register F2 and one end of the delay device Delay, the output end of the NOT gate I2 is connected to the second input end of the NOT gate A1, the output end of the NOT gate A1 is connected to the CLR end of the first register F1, the output end of the NOT gate A2 is connected to the CLR end of the second register F2, the other end of the delay device Delay is connected to the input end of the NOT gate I3, and the output end of the NOT gate I3 is connected to the second input end of the NOT gate A2; The first register F1 and the second register F2 are D flip-flops; the latch SR is an RS flip-flop.

2. The Start and Stop identification circuit of an I2C bus according to claim 1, characterized in that: The delay time of the delay device Delay is 20ns.

3. The Start and Stop identification circuit of an I2C bus according to claim 1, characterized in that: The Q terminal of the latch SR outputs a signal FLAG. When the signal FLAG is at a high level, it indicates that the transmission is in progress. When the signal FLAG is at a low level, it indicates that the transmission has ended.

4. A method for identifying the Start and Stop identification circuit of an I2C bus according to any one of claims 1 to 3, characterized in that The following steps are involved: When the signal SCL is at a low level, the low level of the signal SCL resets the first register F1 and the second register F2 respectively through the NAND gate A1 and the NAND gate A2; When the signal SCL is at a high level, the Start and Stop recognition circuits of the I2C bus can recognize the Start and Stop signals; When the signal SDA changes from high level to low level, the signal SDA passing through the NOT gate I1 will send out a rising edge from low level to high level, and the rising edge triggers the first register F1 to output a high level, that is, the signal Start changes to high; the high level of the signal Start will trigger the latch SR to output a high level, that is, the signal FLAG changes to high, and the signal Start recognition is completed; at the same time, the clk terminal of the second register F2 will only have a falling edge from high level to low level, and will not trigger any changes; When the signal SDA changes from low level to high level, the rising edge from low level to high level triggers the second register F2 to output high level, that is, the signal Stop changes to high level; the high level of the signal Stop resets the first register F1 after passing through the NOT gate I2 and the NAND gate A1, and changes the signal Start to low level; at the same time, the high level of the signal Stop will trigger the latch SR to output low level, that is, the signal FLAG changes to low level, and the signal Stop recognition is completed; at the same time, the clk end of the first register F1 will only have a falling edge from high level to low level, and will not trigger any changes; The delay device delay will make the high level of the signal Stop last for 20ns, and then reset the second register F2 through the NOT gate I3 and the NAND gate A2, and change the signal Stop to a low level, so as to ensure that the recognition of the next signal Start will start again after 20ns; When the signal FLAG is at a high level, it indicates that the transmission is in progress; when FLAG is at a low level, it indicates that the transmission has ended.

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