Two-phase interleaved AC link converter topology and constant frequency quasi-peak current control method

Abstract

The present invention discloses a two-phase interleaved AC link converter topology and a constant-frequency quasi-peak current control method thereof, wherein the converter topology comprises a two-phase interleaved Buck-Boost structure, a series resonant tank and a support capacitor C v , wherein: the two-phase staggered Buck-Boost structure is composed of switch devices Q1~Q8, inductors L1~L2, and the series resonant tank is composed of resonant inductor L r , resonant capacitor C r and a transformer; the series resonant tank has multiple secondary windings and a rectifier circuit to form a multi-phase parallel output; the support capacitor C v The two-phase interleaved Buck-Boost structure is connected in parallel at both ends of the two rear bridge arms to provide a supporting voltage for the series resonant tank. The two-phase interleaved AC link converter of the present invention realizes the combination of the chopper circuit and the resonant circuit, and the circuit topology has the advantages of easy voltage regulation of the chopper circuit and easy soft switching and magnetic integration of the resonant circuit.

Description

Technical Field

[0001] The invention relates to a converter topology, in particular to a two-phase interleaved AC link converter topology and a constant-frequency quasi-peak current control method thereof. Background Art

[0002] At present, the most widely used power supply topology for high-performance computing boards is the two-stage power supply topology. The front stage usually uses a fixed ratio converter to achieve pre-voltage reduction to obtain a 5-12V intermediate bus, such as LLC or hybrid switched capacitor topology. The back stage uses a multi-phase interleaved Buck converter to achieve multi-phase parallel connection and output a large current. However, as the power consumption of the processor continues to increase and the power supply voltage continues to decrease, the required power supply current continues to rise, which leads to a significant increase in the transmission loss on the 5-12V intermediate bus in the existing two-stage topology. At the same time, the multi-phase Buck converter cannot achieve soft switching of the switching device under high current load, and its switching loss will increase with the increase of the intermediate bus voltage and the increase of load current. Therefore, the multi-phase Buck converter cannot adapt to higher intermediate bus voltages. In addition, the magnetic integration design of the multi-phase coupled inductor of the Buck converter is difficult, which limits the further improvement of the power density of the load point power supply.

[0003] Compared with the Buck converter, the LLC converter has obvious advantages in efficiency and power density when used as a point-of-load power supply. This is due to the fact that the LLC converter transmits sinusoidal alternating current to the transformer in a resonant manner, which can not only realize soft switching of the primary and secondary switching devices, but also reduce the difficulty of magnetic integration of magnetic components because its transformer core works in an alternating magnetization state rather than a biased magnetization state. In addition, the Buck-Boost converter can be used as the front stage of the LLC converter to provide it with a higher intermediate bus voltage to achieve smaller PDN losses. However, the Buck-Boost converter has many control degrees of freedom, and the existing control strategy has obvious defects, which can be summarized into the following three aspects: (1) It is necessary to calculate the modulation time of each switching device through complex calculation formulas, which has high requirements on the computing power of the microcontroller. At the same time, the large calculation delay is not conducive to powering high dynamic loads such as processors. (2) It is necessary to change the control object and control parameters under different working conditions and switch the algorithm to achieve converter efficiency optimization. However, this control mode has the problem of algorithm boundary oscillation under frequent load jumps. (3) In order to reduce the computing burden of the microcontroller, many algorithms are implemented by table lookup. However, this method requires very detailed tables to ensure control accuracy, which takes up a lot of storage resources. At the same time, it inevitably brings high latency to the control system in the process of querying huge table data. In summary, the existing Buck-Boost control strategy is not suitable for the use scenario of high-performance computing power supply. Summary of the invention

[0004] In view of the above problems, the present invention provides a two-phase interleaved AC link converter topology and a constant-frequency quasi-peak current control method thereof. The converter proposed in the present invention is a single-stage converter that combines a Buck-Boost structure with a series resonant structure, forms a high-voltage AC transmission chain through the rear bridge arm of the Buck-Boost structure, and proposes a constant-frequency quasi-peak control strategy, which aims to combine the flexible voltage regulation capability of the Buck-Boost structure with the high efficiency and high density characteristics of the series resonant structure, so that it can power low-voltage and high-current loads such as CPUs and GPUs under the VBA power supply architecture, and achieve rapid regulation of the output voltage V by real-time control of the inductor current working waveform. o purpose.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] A two-phase interleaved AC link converter topology includes a two-phase interleaved Buck-Boost structure, a series resonant tank and a support capacitor C v ,in:

[0007] The two-phase interleaved Buck-Boost structure is composed of switch devices Q1-Q8 and inductors L1-L2.

[0008] The series resonant tank consists of a resonant inductor L r , resonant capacitor C r And transformer composition;

[0009] The primary side of the converter is composed of four bridge arms formed by switching devices Q1 and Q2, Q3 and Q4, Q5 and Q6, Q7 and Q8, respectively. The two ends of the inductor L1 are respectively connected to the midpoint of the bridge arm formed by Q1 and Q2 and the midpoint of the bridge arm formed by Q3 and Q4, and the two ends of the inductor L2 are respectively connected to the midpoint of the bridge arm formed by Q5 and Q6 and the midpoint of the bridge arm formed by Q7 and Q8. The above devices together form a two-phase staggered Buck-Boost structure; the two rear bridge arms composed of switching devices Q3 and Q4, Q7 and Q8 together form a full-bridge inverter structure, and the series resonant tanks are connected at the midpoints a and b of the two rear bridge arms;

[0010] The series resonant tank has a plurality of secondary windings and rectification circuits thereof to form a multi-phase parallel output;

[0011] The supporting capacitor C v Connected in parallel at both ends of the two rear bridge arms of the two-phase interleaved Buck-Boost structure to provide support voltage for the series resonant tank;

[0012] The two-phase interleaved Buck-Boost structure can be used as a voltage regulation and inverter link in the VBA power supply architecture, and the series resonant tank serves as a resonant step-down link in the VBA power supply architecture. In the two-phase interleaved Buck-Boost structure, the midpoints a and b of the two rear bridge arms composed of switching devices Q3 and Q4, Q7 and Q8 form a high-voltage AC transmission chain.

[0013] A constant frequency quasi-peak current control method for the above two-phase interleaved AC link converter topology is provided by real-time controlling the working current i of the inductors L1 and L2. L1 、i L2 waveform, to quickly adjust the output voltage V o The purpose of which:

[0014] The working current i of the inductors L1 and L2 L1 、i L2 The waveform is modulated into a quadrilateral wave, and the phase difference between the two is 180°. The waveform contains four inflection points and four stages.

[0015] The four inflection points are A, B, C, and D. When the input voltage is lower than the support capacitor voltage, the current waveform characteristics of the inductors L1 and L2 have point A higher than point B; when the input voltage is higher than the support capacitor voltage, the current waveform characteristics of the inductors L1 and L2 have point A lower than point B; when the input voltage is equal to the support capacitor voltage, the current waveform characteristics of the inductors L1 and L2 have point A equal to point B;

[0016] The four stages are respectively the input stage T1, the input-output stage T2, the falling stage T3 and the clamping stage T4, the DA segment of the current waveform is the input stage T1, the AB segment is the input-output stage T2, the BC segment is the falling stage T3, and the CD segment is the clamping stage T4;

[0017] The working current i of the inductor L1 L1 The waveform is as follows: During the input stage T1, the switch devices Q1 and Q4 are turned on, and the inductor L1 is connected in parallel to the input side voltage source V in , energy storage begins, and when the working current rises to point A, the switch device Q4 is turned off, and the current at point A in the inductor L1 is I A and the resonant tank excitation current I m The parasitic capacitances in the switch devices Q3 and Q4 are charged and discharged together, preparing for the zero voltage turn-on of the switch device Q3; then the circuit enters the input-output stage T2, during which the switch devices Q1 and Q3 are turned on, and the inductor L1 is connected to the input side power supply V in The series transfers energy to the output side, V in >V c In this state, the working current slope is positive, V in <V cIn this state, the working current slope is negative, V c To support the capacitor voltage, Q1 is turned off when the working current reaches point B, and the current I B The parasitic capacitances of the switch devices Q1 and Q2 are charged and discharged respectively, preparing for the zero voltage turn-on of the switch device Q2; then the circuit enters the falling stage T3, during which the switch devices Q2 and Q3 are turned on, and the inductor L1 is connected to the output terminal V o In parallel, magnetic reset begins. In order to achieve zero voltage turn-on of the switch device Q1, the working current needs to drop to a negative value C during this stage. Then the switch device Q3 is turned off, and the current I C and the resonant tank excitation current I m The parasitic capacitance of the switching devices Q3 and Q4 is charged and discharged together, preparing for the zero voltage turn-on of the switching device Q4; during the clamping stage T4, the switching devices Q2 and Q4 are turned on, and the inductor does not exchange energy with the outside world. The reverse circulation in it discharges the parasitic capacitance before the switching device Q1 is turned on in the next cycle T1, thereby realizing the zero voltage turn-on of the switching device Q1;

[0018] The working current i of the inductor L2 L The waveform is as follows: the inductor L2 starts to lag behind the inductor L1 by 180° in each phase T1 to T4. During the input phase T1, the switching devices Q5 and Q8 are turned on, and the inductor L2 is connected in parallel to the input side voltage source V in , energy storage begins, and when the working current rises to point A, the switch device Q8 is turned off, and the current at point A in the inductor L2 is I A and the resonant tank excitation current I m The parasitic capacitances in the switch devices Q7 and Q8 are charged and discharged together, preparing for the zero voltage turn-on of the switch device Q7; then the circuit enters the input-output stage T2, during which the switch devices Q5 and Q7 are turned on, and the inductor L2 is connected to the input side power supply V in The series transfers energy to the output side, V in >V c In this state, the working current slope is positive, V in <V c In this state, the working current slope is negative, V c To support the capacitor voltage, when the working current reaches point B, Q5 is turned off, and the current I B The parasitic capacitances of the switch devices Q5 and Q6 are charged and discharged respectively, preparing for the zero voltage turn-on of the switch device Q6; then the circuit enters the falling stage T3, during which the switch devices Q6 and Q7 are turned on, and the inductor L2 is connected to the output terminal V oIn parallel, magnetic reset begins. In order to achieve zero voltage turn-on of the switch device Q5, the working current needs to drop to a negative value C during this stage. Then the switch device Q5 is turned off, and the current I C and the resonant tank excitation current I m The parasitic capacitance of the switching devices Q7 and Q8 is charged and discharged together, preparing for the zero voltage turn-on of the switching device Q8; during the clamping stage T4, the switching devices Q6 and Q8 are turned on, and the inductor does not exchange energy with the outside world. The reverse circulation in it discharges the parasitic capacitance before the switching device Q5 is turned on in the next cycle T1, thereby realizing the zero voltage turn-on of the switching device Q5;

[0019] The working current i of the inductors L1 and L2 L1 、i L2 The specific regulation process under different input voltages is as follows:

[0020] Assume that the resonant tank and its secondary rectifier circuit are ideal devices with no additional losses, and the supporting capacitor C v In steady state, the voltage is constant at V c , since the resonant tank operates at the resonant frequency, it has a gain K r , and there is V o =K r ·V c ;

[0021] When the input voltage V in =V c When the current AB segment slope is 0, and the absolute value of the current slope of the DA segment is equal to that of the BC segment, the working current waveform is an isosceles trapezoid, and the average value of the input current in one cycle of the power supply is equal to the current flowing to the support capacitor C v The average value of the transport current, that is, the area S1+S2 is equal to the area S2+S3, S1 is the area of ​​the geometric shape formed by the DA segment current and the abscissa, S2 is the area of ​​the geometric shape formed by the AB segment current and the abscissa, and S3 is the area of ​​the geometric shape formed by the BC segment current and the abscissa;

[0022] When the input voltage V in <V c When the current AB segment has a negative slope, the absolute value of the current slope of the DA segment is smaller than that of the BC segment. As the input voltage decreases, the output voltage will drop transiently. At this time, the voltage loop output accumulates positively, and the voltage loop output V err Increase, the current I at point A A Increase, T2 stage duration in kV err The area S1+S2 is larger than the area S2+S3, and the average input current of the power supply in one cycle is larger than the support capacitor C. v The average value of the delivery current is used to stabilize the output voltage V o;

[0023] When the input voltage V in >V c When the current AB segment has a positive slope, the absolute value of the current slope of the DA segment is greater than that of the BC segment. As the input voltage increases, the output voltage will produce a transient overshoot. At this time, the voltage loop output accumulates negatively, V err Decrease, the current I at point A A Decreased, T2 phase duration in kV err The area S1+S2 is also reduced under the action of, making the area S1+S2 smaller than the area S2+S3, that is, the average value of the input current in one cycle of the power supply is less than the support capacitor C v The average value of the transmission current is used to achieve a stable output voltage V o ;

[0024] The working current i of the inductors L1 and L2 L1 、i L2 At different load currents I o There are three working states:

[0025] When the load current is large, i L1 and i L2 Working in the critical continuous state, point C coincides with point D, and the clamping stage T4 time is 0;

[0026] When the load current I o decreases, which will cause the output voltage V o During transient overshoot, the compensator accumulates the error negatively, V err Decrease, the current I at point A A Decreased, T2 phase duration in kV err The converter input average current and output average current are reduced, thereby stabilizing the output voltage. As the converter input average current and output average current decrease, i L1 and i L2 Start working in the current discontinuous state; if the current I A and the current I at point B B Both are greater than the minimum soft switching current I ZVS , the working state at this time is called the non-clamped intermittent state;

[0027] When the load current I o When further reduced, for V in <V c In the case of B Will first reduce to the minimum soft switching current I ZVS To ensure that the switching devices Q2 / Q6 can achieve ZVS, I B Clamp to I ZVSAt this time, the working current enters the clamped discontinuous state, and the voltage regulation of the converter is only determined by V err Control I A Implementation; for V in >V c In the case of A Will first reduce to the minimum soft switching current I ZVS To ensure that the switching devices Q1 / Q5 can achieve ZVS, I A Clamp to I ZVS At this time, the working current enters the clamped intermittent state, and the voltage regulation of the converter is only determined by kV err Control T2 to achieve; for V in =V c In the case of A Equal to the current I at point B B , when I A Reduce to the minimum soft switching current I ZVS When it is clamped, the working current enters the clamped intermittent state, and the voltage regulation of the converter is only controlled by kV err Control T2 implementation.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] 1. The two-phase interleaved AC link converter of the present invention realizes the combination of a chopper circuit and a resonant circuit. The circuit topology has the advantages that the chopper circuit is easy to adjust the voltage and the resonant circuit is easy to realize soft switching and magnetic integration.

[0030] 2. The two-phase interleaved Buck-Boost structure in the two-phase interleaved AC chain converter of the present invention can be used as a voltage regulation and inverter link in the VBA power supply architecture, and can be packaged as a front module in the virtual bus power supply architecture (Virtual Bus Architecture, referred to as VBA architecture), and placed at the edge of the board to access the input bus. The series resonant tank structure and its secondary side rectifier circuit can be used as a resonant step-down link in the VBA power supply architecture, and can be packaged as a load point module in the VBA architecture, and placed at the load point to provide better dynamic performance. A high-voltage AC transmission chain is formed at points a and b in the converter, which has lower PDN losses than the 12V bus in the IBC architecture. Therefore, compared with the existing power supply architecture or topology, the virtual bus power supply architecture proposed in the present invention is easier to achieve high efficiency and high power density.

[0031] 3. The constant-frequency quasi-peak current control strategy of the two-phase interleaved AC link converter proposed in the present invention is a continuous control method. Its real-time control of the working current waveform does not change the control object and control parameters under different working conditions, and does not require algorithm switching, which can avoid the problem of algorithm boundary oscillation under frequent load jumps.

[0032] 4. The constant-frequency quasi-peak current control strategy of the two-phase interleaved AC link converter proposed in the present invention can be implemented by a digital controller combined with an analog circuit. Compared with the existing control strategy, it can occupy less storage resources and computing resources of the digital controller.

[0033] 5. Under the constant-frequency quasi-peak current control strategy of the two-phase interleaved AC link converter proposed in the present invention, the two-phase interleaved AC link converter can realize soft switching of all switching devices and has good dynamic response capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a topology diagram of a two-phase interleaved AC link converter;

[0035] Figure 2 Provides virtual 48V bus power supply architecture;

[0036] Figure 3 Schematic diagram of module layout under VBA power supply architecture, (a) horizontal power supply, (b) vertical power supply;

[0037] Figure 4 Schematic diagram of the working waveform of the working current under different modulation strategies and working conditions, (a) triangle wave modulation strategy, (b) quadrilateral wave modulation strategy;

[0038] Figure 5 is the AC transmission link voltage v ab and current i ab Waveform diagram;

[0039] Figure 6 Schematic diagram of the main current waveform of the two-phase interleaved AC link converter, (a) buck state, (b) boost state;

[0040] Figure 7 It is the process of adjusting the waveform of the working current under different input voltages for quasi-peak current control;

[0041] Figure 8 Three working states of working current under quasi-peak current control strategy;

[0042] Fig. 9 V in =The value range of k at 40V;

[0043] Fig.10 V in =The value range of k at 48V;

[0044] Fig.11 V in =The value range of k at 60V;

[0045] Fig.12It is a schematic diagram of closed-loop control of a two-phase interleaved AC link converter based on VBA architecture;

[0046] Fig.13 It is a schematic diagram of the logic control module;

[0047] Fig.14 It is the main power topology simulation model;

[0048] Fig.15 It is a simulation model for logic control circuit;

[0049] Fig.16 Key waveforms for converters @60V&400A;

[0050] Fig.17 Key waveforms for converter @60V&100A;

[0051] Fig.18 Key waveforms for converter @48V&400A;

[0052] Fig.19 Key waveforms for converter @48V&100A;

[0053] Fig. 20 Key waveforms for converters @40V&400A;

[0054] Fig.21 Key waveforms for converters @40V&100A;

[0055] Fig. 22 It is the zero voltage turn-on (ZVS) waveform of the switching device;

[0056] Fig.23 Load dump response characteristics of the converter under rated input and output, (a) overall waveform, (b) local amplified waveform;

[0057] Fig.24 The load sudden increase response characteristics of the converter at rated input and output are (a) overall waveform and (b) local amplified waveform. DETAILED DESCRIPTION

[0058] The technical solution of the present invention is further described below in conjunction with the accompanying drawings, but is not limited thereto. Any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention should be included in the protection scope of the present invention.

[0059] The present invention provides a two-phase interleaved AC link converter topology, such as Figure 1As shown, the primary side of the converter is composed of four bridge arms formed by switching devices Q1 and Q2, Q3 and Q4, Q5 and Q6, Q7 and Q8, respectively. The two ends of the inductor L1 are connected to the midpoint of the bridge arm composed of Q1 and Q2, and the midpoint of the bridge arm composed of Q3 and Q4, respectively. The two ends of the inductor L2 are connected to the midpoint of the bridge arm composed of Q5 and Q6, and the midpoint of the bridge arm composed of Q7 and Q8, respectively. The above devices together form a two-phase staggered Buck-Boost structure. The two rear bridge arms composed of switching devices Q3 and Q4, Q7 and Q8 together form a full-bridge inverter structure, which can provide alternating voltage. A resonant inductor L is connected at the midpoints a and b of the two rear bridge arms composed of switching devices Q3 and Q4, Q7 and Q8. r , resonant capacitor C r and a series resonant tank formed by a transformer, the series resonant tank having a characteristic resonant frequency f r , L r The series resonant tank operates at its characteristic resonant frequency f r When the gain K is fixed r , characteristic resonant frequency f r It is n times the operating frequency f of the two-phase interleaved Buck-Boost structure, where n is a positive integer. The resonant tank transformer can have multiple secondary windings and their rectifier circuits to form a multi-phase parallel output, where the rectifier circuit includes a rectifier switch and a filter capacitor. Support capacitor C v It is connected in parallel at both ends of the two rear bridge arms of the two-phase interleaved Buck-Boost structure to provide a supporting voltage for the series resonant tank.

[0060] The two-phase interleaved AC link converter combines the two-phase interleaved Buck-Boost structure with the series resonant tank structure to achieve the fusion of the chopper circuit and the resonant circuit. The two-phase interleaved Buck-Boost structure in the topology has a wide voltage regulation range, and its rear bridge arm also takes into account the inverter function, so it serves as the voltage regulation and inverter link in the VBA architecture. The series resonant tank structure in the topology uses the transformer to transfer a sinusoidal alternating current with the same phase as the voltage from the primary side to the secondary side through resonance, and obtains a stable DC output voltage through the full-wave rectifier circuit on the secondary side. This structure serves as the resonant step-down link in the VBA architecture. The two-phase interleaved Buck-Boost structure and the series resonant tank structure are connected at the midpoints a and b of the two rear bridge arms composed of the switching devices Q3 and Q4, Q7 and Q8 in the topology to form a high-voltage AC transmission chain, and the alternating voltage transmitted on it is v ab, the alternating voltage and the alternating current are in phase. The voltage waveform between the midpoints a and b of the two rear bridge arms formed by the switching devices Q3 and Q4, Q7 and Q8 can be an AC square wave voltage, an AC three-level voltage or an AC multi-level voltage, or switch between two or three of the AC square wave voltage, the AC three-level voltage and the AC multi-level voltage. The current waveforms of the inductors L1 and L2 in the two-phase interleaved Buck-Boost structure are 180° out of phase. The two-phase interleaved Buck-Boost structure in the two-phase interleaved AC link converter can be packaged as a front module in a virtual bus power supply architecture (Virtual Bus Architecture, referred to as VBA architecture), and the series resonant tank structure and its secondary side rectifier circuit can be packaged as a load point module in the VBA architecture. The output of the front module is an AC square wave voltage, an AC three-level voltage or an AC multi-level voltage, or switches between two or three of the AC square wave voltage, the AC three-level voltage and the AC multi-level voltage, and serves as the input of the load point module. The load point module transmits alternating current to the load side through a transformer in a resonant manner, and the alternating current is rectified by a rectifier circuit to form a stable DC output voltage.

[0061] like Figure 2 As shown, the VBA architecture has the characteristics of wide voltage regulation range, high step-down ratio, high dynamic response, etc. It can convert a certain range of input voltage into 0.6~1.8V to realize power supply for low-voltage, high-current loads such as GPU and CPU. The converter topology used in this architecture can be divided into voltage regulation and inverter link and resonant step-down link according to function, and the two are connected by a high-voltage AC transmission chain. Among them, the voltage regulation and inverter link mainly realizes the closed-loop voltage stabilization function of the entire power supply system, and provides alternating voltage for the connected resonant step-down link to form a high-voltage AC transmission chain. The voltage regulation and inverter link can provide the required AC square wave voltage, AC three-level voltage or multi-level voltage for the resonant step-down link by constructing a half-bridge, full-bridge or push-pull structure. In addition, as Figure 3 As shown in the figure, the voltage regulation and inverter link can be packaged as a front module and placed at the edge of the computing board away from the load to access the input bus. At the same time, the resonant buck link can be packaged as a load point module and placed at the load point. It can be placed horizontally around the load chip to form a horizontal power supply, such as Figure 3 As shown in (a), it can also be placed vertically on the back of the load chip to form a vertical power supply, such as Figure 3 As shown in (b), in order to save the layout space around the high-performance computing chip and obtain better dynamic performance, finally, the high-voltage AC transmission chain can be arranged on the main board of the load chip.

[0062] The resonant buck link can transmit sinusoidal alternating current on the transformer by constructing a series resonant slot. Therefore, compared with the magnetic components in the Buck and CDR converters working in the biased magnetization state, it is easier to integrate and optimize the size of the magnetic components and achieve higher power density. At the same time, the resonant buck link can use multiple identical structures in parallel to improve the current output capacity; the resonant buck link has a characteristic resonant frequency f r , operating at its characteristic resonant frequency f r When the gain K is fixed r In addition, the characteristic resonant frequency f r It can be n times the operating frequency f of the voltage regulation and inverter link, where n is a positive integer. In the VBA architecture, the alternating voltage and alternating current transmitted on the AC transmission chain are in phase.

[0063] Compared with the existing IBC and FPA two-stage power supply architectures, the VBA power supply architecture is a single-stage power supply architecture. This architecture does not connect two independent converters in series, but splits the single-stage two-phase interleaved AC chain converter into two parts according to the functional structure to obtain packaging and layout advantages. For example, the voltage regulation and inverter link can be packaged as a front module, and the computing board is placed away from the edge of the load to access the input bus. At the same time, the resonant buck link is packaged as a load point module and placed at the load point to save layout space around the high-performance computing chip and obtain better dynamic performance.

[0064] In the VBA architecture, the alternating voltage amplitude on the high-voltage AC transmission chain provided by the voltage regulation and inverter link can always be higher than the maximum input voltage, or within the input voltage range, or always lower than the minimum input voltage. For example, for an input voltage of 40 to 60V, the voltage amplitude on the high-voltage AC transmission chain can be 80V, 48V or 36V, etc. As the voltage amplitude on the high-voltage AC transmission chain increases, the board can have smaller PDN losses.

[0065] In the present invention, the two-phase interleaved AC link converter can sample the output voltage V in real time. o And with the given value V ref After comparison, the compensator controls the on and off time (duty cycle) of the switch devices Q1 to Q8 to stabilize the output voltage. Among them, the switch devices Q1 and Q2 are complementary turned on, Q3 and Q4 are complementary turned on, Q5 and Q6 are complementary turned on, and Q7 and Q8 are complementary turned on. The current waveforms of the inductors L1 and L2 in the topology can work in a triangular wave or a quadrilateral wave state according to different modulation strategies, or switch between a triangular wave and a quadrilateral wave, and according to the size of the load current, the working current of the inductors L1 and L2 can work in a current continuous state, a discontinuous state or a critical continuous state, or can switch between two or three states of current continuous, discontinuous, and critical continuous, such as Figure 4 As shown in (a) and (b). Support capacitor C in the two-phase interleaved AC link converter v There is a stable DC voltage V c , whose amplitude determines the alternating voltage v on the high voltage AC transmission chain ab Under the dual-phase interleaved Buck-Boost structure, the converter input voltage V in Can be lower, equal or higher than the support capacitor voltage V c For example, when the input voltage is 40-60V, the support capacitor voltage V c It can be stabilized at around 48V, thus obtaining a 48V AC transmission chain to reduce the current conduction loss between the front module and the rear module. In addition, the alternating voltage v on the high-voltage AC transmission chain ab The waveform can be a symmetrical square wave alternating voltage or a symmetrical three-level alternating voltage according to different modulation strategies, or it can switch between the two according to the changes of input voltage and output load, such as Figure 5 Finally, the two-phase interleaved AC link converter can be realized by utilizing the working current i of inductor L1 and inductor L2. L1 、i L2 and the series resonant tank transformer excitation current i m During the dead time of the switch drive signal, the parasitic capacitance of the switch devices Q1~Q8 is charged and discharged to achieve zero voltage turn-on (ZVS turn-on), and the secondary side rectifier switch of the transformer can achieve zero current turn-off (ZCS turn-off). Therefore, the converter can have a higher operating frequency, usually greater than 100kHz.

[0066] The present invention also provides a fixed-frequency quasi-peak current control strategy for the above-mentioned two-phase interleaved AC link converter topology, which aims to control the working current i of the inductor L1 and the inductor L2 in real time. L1 and i L2 waveform, to quickly adjust the output voltage V oThe purpose of this invention is to achieve the purpose of controlling the switching device of the control strategy by using a mixed digital-analog circuit and a digital timer combined with analog comparators and other devices, thereby avoiding the calculation of the modulation time of each switching device in the controller through complex calculation formulas and reducing the control strategy's requirements on the computing power of the microcontroller. Although the table lookup method can also reduce the computing burden of the controller, it also has the following obvious disadvantages: First, the table lookup is a discrete point control, which requires the value of each control variable to be queried according to the working state of the converter, and cannot achieve real-time continuous control; second, to ensure the control accuracy, the table lookup method requires a very fine table, so it takes up a lot of storage resources; third, the table lookup method inevitably brings a high delay to the control system in the process of querying huge table data, so it is not suitable for powering high dynamic loads such as CPUs and GPUs. Finally, the quasi-peak current control strategy of the two-phase interleaved AC link converter does not change the control object and control parameters under different working conditions, and does not switch the algorithm, thereby avoiding the problem of algorithm boundary oscillation under frequent load jumps.

[0067] Under the constant frequency quasi-peak current control strategy of the two-phase interleaved AC link converter, the working current i L1 and i L2 It is modulated into a quadrilateral wave, and the phase difference between the two is 180°. The waveform contains four inflection points A, B, C, and D. When the input voltage is lower than the supporting capacitor voltage, the current waveform characteristics of the inductors L1 and L2 have point A higher than point B; when the input voltage is higher than the supporting capacitor voltage, the current waveform characteristics of the inductors L1 and L2 have point A lower than point B; when the input voltage is equal to the supporting capacitor voltage, the current waveform characteristics of the inductors L1 and L2 have point A equal to point B. Figure 6 In (a) and (b), V in >V c and V in <V c The current waveform of the lower inductor L1 and L2 is L1 and i L2 and the resonant tank current i r The waveform has a positive direction in Figure 2 Given. Current i L1 and i L2 The waveform contains four stages, namely input stage T1, input-output stage T2, drop stage T3 and clamping stage T4. The DA segment of the current waveform is the input stage T1, the AB segment is the input-output stage T2, the BC segment is the drop stage T3, and the CD segment is the clamping stage T4. L1 For example, during the input phase T1, the switch devices Q1 and Q4 are turned on, and the inductor L1 is connected in parallel to the input side voltage source V in , energy storage begins, and when the working current rises to point A, the switch device Q4 is turned off, and the current I in the inductor L1 Aand the resonant tank excitation current I m The parasitic capacitance in the switch devices Q3 and Q4 is charged and discharged together, preparing for the zero voltage turn-on of the switch device Q3. Then the circuit enters the input-output stage T2, during which the switch devices Q1 and Q3 are turned on, and the inductor L1 is connected to the input side power supply V in The series transfers energy to the output side, V in >V c In this state, the working current slope is positive, V in <V c In this state, the slope of the working current is negative. When the working current reaches point B, Q1 is turned off and the current I in the inductor L1 B The parasitic capacitance of the switch devices Q1 and Q2 is charged and discharged respectively, preparing for the zero voltage turn-on of the switch device Q2. Then the circuit enters the falling stage T3, during which the switch devices Q2 and Q3 are turned on, and the inductor L1 is connected to the output terminal V o In parallel, magnetic reset begins. In order to achieve zero voltage turn-on of the switch device Q1, the working current needs to drop to a negative value C during this stage. Then the switch device Q3 is turned off and the working current flows to I C and the resonant tank excitation current I m The parasitic capacitance of the switching devices Q3 and Q4 is charged and discharged together, preparing for the zero voltage turn-on of the switching device Q4. During the clamping stage T4, the switching devices Q2 and Q4 are turned on, and the inductor does not exchange energy with the outside world. The reverse circulation in it discharges the parasitic capacitance before the switching device Q1 is turned on in the next cycle T1, thereby achieving the zero voltage turn-on of the switching device Q1.

[0068] In order to ensure that the switch devices Q1~Q4 can be completely turned on with zero voltage, the working current i L1 and i L2 The absolute values ​​at points A, B, C, and D must be greater than or equal to the minimum zero voltage turn-on current I ZVS If the resonant tank excitation inductance L m is large enough that the excitation current i m Small enough to be ignored, I ZVS It can be determined by formula (1):

[0069]

[0070] In the formula, C oss is the drain-source parasitic capacitance of the switching device, t dead is the dead time.

[0071] When the resonant tank excitation current i m The time cannot be ignored, according to Figure 6 It can be seen that it reaches the peak value I when the switch device Q3 or Q7 is turned on. m, combined with Figure 2 The positive direction of each current given in the figure shows that the soft switching current that can be obtained when the switch device Q3 is turned on is I A +I m , the soft switching current available to the switch device Q4 when it is turned on is I C +I m The same is true for the switch devices Q7 and Q8, which will not be described here. Therefore, the minimum soft switching current of the upper and lower tubes of the two rear bridge arms is rewritten as formula (2):

[0072]

[0073] Wherein, T is the working period of the two-phase interleaved AC link converter.

[0074] In the constant frequency quasi-peak current control strategy of the AC link converter proposed in the present invention, the output voltage V is sampled in real time. o and with a given value V ref After the difference is made, the voltage loop output V is obtained through the compensator. err , V err It is used to adjust the amplitude I of point A in the current waveform of inductors L1 and L2. A , while the input-output stage T2 time is determined by V err and the proportional coefficient k, which is given by formula (3):

[0075] I A =V err , T2=k·V err (3)

[0076] Figure 7 The constant frequency quasi-peak current control strategy is used to control the working current under different input voltages. For the convenience of analysis, it is assumed that the resonant tank and its secondary rectifier circuit are ideal devices with no additional losses. v In steady state, the voltage is constant at V c , since the resonant tank operates at the resonant frequency, it has a gain K r , and there is V o =K r ·V c When the input voltage V in =V c When the current AB segment slope is 0, and the absolute value of the current slope of the DA segment is equal to that of the BC segment, the working current waveform is an isosceles trapezoid. At this time, the average input current of the power supply in one cycle is equal to the current flowing to the support capacitor C v The average value of the transmitted current, that is, the area S1+S2 is equal to the area S2+S3. in <V cWhen the current AB segment has a negative slope, the absolute value of the current slope of the DA segment is smaller than that of the BC segment. As the input voltage decreases, the output voltage will drop transiently. At this time, the voltage loop output accumulates positively, V err Increase, the current I at point A A Increase, T2 stage duration in kV err The area S1+S2 is larger than the area S2+S3, and the average input current of the power supply in one cycle is larger than the support capacitor C. v The average value of the delivery current is used to stabilize the output voltage V o When the input voltage V in >V c When the current AB segment has a positive slope, the absolute value of the current slope of the DA segment is greater than that of the BC segment. As the input voltage increases, the output voltage will produce a transient overshoot. At this time, the voltage loop output accumulates negatively, V err Decrease, the current I at point A A Decreased, T2 phase duration in kV err The area S1+S2 is also reduced under the action of, making the area S1+S2 smaller than the area S2+S3, that is, the average value of the input current in one cycle of the power supply is less than the support capacitor C v The average value of the transmission current is used to achieve a stable output voltage V o .

[0077] When the output load current is greater than a certain value, the duration of the clamping stage T4 can be 0, and at this time, points C and D in the working current waveform coincide. When points C and D coincide, the two-phase interleaved AC link converter operates in the critical continuous state of the working current; when points C and D do not coincide, the two-phase interleaved AC link converter operates in the discontinuous state of the working current. When the current amplitude at point A or point B is clamped to the minimum soft switching current for realizing the ZVS opening of Q1~Q8, the two-phase interleaved AC link converter operates in the clamped discontinuous state of the working current. When the current amplitude at point A or point B is greater than the minimum soft switching current for realizing the ZVS opening of Q1~Q8, the two-phase interleaved AC link converter operates in the non-clamped discontinuous state of the working current.

[0078] Figure 8 The two-phase interleaved AC link converter is given at different load currents I o There are three working states of the working current. When the load current is large, the working current i L1 and i L2 Working in the critical continuous state, point C and point D in the current waveform coincide, and the clamping stage T4 time is 0. o decreases, which will cause the output voltage V o During transient overshoot, the compensator accumulates the error negatively, V err Decrease, the current I at point A ADecreased, T2 phase duration in kV err , which reduces the average input current and output current of the converter, thereby stabilizing the output voltage. As the average input current and output current of the converter decrease, the working current i L1 and i L2 It starts to work in the current discontinuous state. If the current I A and the current I at point B B Both are greater than the minimum soft switching current I ZVS , the working state at this time is called the non-clamped intermittent state. o When further reduced, for V in <V c In the case of B Will first reduce to the minimum soft switching current I ZVS To ensure that the switching devices Q2 / Q6 can achieve ZVS, I B Clamp to I ZVS At this time, the working current enters the clamped discontinuous state, and the voltage regulation of the converter is only determined by V err Control I A For V in >V c In the case of A Will first reduce to the minimum soft switching current I ZVS To ensure that the switching devices Q1 / Q5 can achieve ZVS, I A Clamp to I ZVS At this time, the working current enters the clamped intermittent state, and the voltage regulation of the converter is only determined by kV err Control T2 to achieve. For V in =V c , which is similar to V in >V c They are quite similar and will not be described here.

[0079] Finally, under the fixed-frequency quasi-peak current control strategy, the duty cycle of the switch devices Q3 / Q7 on the two rear bridge arms of the Buck-Boost structure can be kept within 0.2 to 0.8 by designing the proportional coefficient k. ab When the duty cycle is not equal to 0.5, it is an AC three-level wave, such as Figure 6 As shown in (a), when the duty cycle is equal to 0.5, it is a square wave. Figure 6 (b) as shown.

[0080] In the switch devices Q1 to Q8, the driving signal of the complementary conduction device has a dead time T D , during the dead time, the resonant tank transformer excitation current i m With the working current i L1and i L2 Together they charge and discharge the parasitic capacitance of the switching device to achieve ZVS turn-on; the working current i L1 and i L2 In the waveform, the minimum current amplitude at point C and point D is the minimum soft switching current I required to turn on the switching devices Q1 or Q5 and Q2 or Q6 ZVS. ZVS1 The minimum current amplitude at point B is the minimum soft switching current I required to turn on the switching device Q2 or Q6ZVS. ZVS2 The minimum current amplitude at point A is the minimum soft switching current I required to turn on the ZVS of the switching device Q3 or Q7. ZVS3 . Among them I ZVS2 It can be determined according to formula (1), I ZVS1 and I ZVS3 It can be determined by formula (1) or (2) according to the magnitude of the excitation current.

[0081] Under the constant frequency quasi-peak current control strategy, the output voltage sampling value is subtracted from the given value, and the error voltage signal V is obtained through the compensator. err ; The voltage v between the midpoints a and b of the two rear bridge arms ab The waveform is an AC square wave or an AC three-level wave; the duty cycle of the upper tubes of the two rear bridge arms increases with the increase of the load current, and when approaching full load, the duty cycle is maintained at 0.4-0.5; the operating frequency of the two-phase interleaved AC link converter is fixed, and the operating frequency is greater than or equal to 100kHz.

[0082] In addition, the fixed-frequency quasi-peak current control strategy also has but is not limited to the following variations:

[0083] (1) Using V err Adjust the current I at point A in the working current waveform A , by V err And the proportional coefficient k together determine the sum of the input stage T1 and the input and output stage T2, that is, T1+T2=kV err ;

[0084] (2) Using V err Adjust the current I at point A in the working current waveform A , the input-output stage T2 time is determined by the proportionality coefficient k and the current working cycle T of the inductors L1 and L2, that is, T2 = kT;

[0085] (3) Using V err Adjust the current I at point A in the working current waveform A The sum of the input phase T1 and the input-output phase T2 is determined by the proportionality coefficient k and the current working cycle T of the inductors L1 and L2, that is, T1+T2=kT;

[0086] (4) The above proportionality coefficient k can be a constant or can be proportional to V in 、V o , L, T, or I o It is a functional relationship, that is, k=f(V in ,V o ,L,T,I o ), where L is the inductance of inductors L1 and L2.

[0087] Under the constant frequency quasi-peak current control strategy, the input phase T1 and point B current I B According to formula (3), I A and T2 vs. k and V err It can be expressed by the relationship between, as shown in equations (4) and (5):

[0088]

[0089] Then, the expression (6) of the falling phase time T3 can be obtained, and the expression (7) of the clamping phase time T4 can be obtained according to the current working cycle T:

[0090]

[0091] T4=T-T1-T2-T3 (7)

[0092] If the end point D of the current waveform of the previous current cycle is taken as the origin, the relationship between the four stages of the working current waveform and time t is given by the following formula:

[0093]

[0094] i4(t3~t4)=-I ZVS (11)

[0095] Combining equations (3) to (11), it can be deduced that the Buck-Boost structure of one phase in the two-phase interleaved AC link converter supports the capacitor C v The average current delivered is I c Expression (12):

[0096]

[0097] Therefore, according to (12), the proportional coefficients k and I under different input voltages and loads can be solved. A In addition, considering that the quasi-peak current control strategy is in the current critical continuous and non-clamped discontinuous state, the output voltage regulation is determined by V err and kV errAt the same time, in order to avoid that the high level duration of the three-level AC voltage provided by the two rear bridge arms to the resonant tank is too short, the duty cycle of the rear bridge arm switch also needs to be limited. Therefore, when solving k and I A The following restrictions need to be added (13):

[0098]

[0099] Among them, V err_max is the voltage loop error V err upper limit.

[0100] Figures 9 to 11 Given an input voltage V in They are 40V, 48V, and 60V respectively, and the output voltage V o The value of k and the current I at point A are 1V and the loads are 400W, 200W, 100W and 50W respectively. A The relationship curve of the shadow area in the figure is the intersection of k values ​​under different input voltages, and the selection range of k is 2.5╳10 -8 ~7.5╳10 -8 At the same time, the larger the value of k is, the more current I A The smaller the k value is, the smaller the peak value and effective value of the working current are, which helps to improve the efficiency of the converter. Therefore, the k value can be selected as 7╳10 -8 .

[0101] Fig.12 A closed-loop control schematic diagram of a two-phase interleaved AC link converter based on a VBA architecture is given. The control part mainly includes an output voltage and working current sampling circuit, a compensator, a logic control circuit and a drive circuit, wherein: the output voltage and working current sampling circuit is used to monitor the output voltage and working current in real time; the compensator is used to realize the loop compensation of the converter, which can be realized based on a digital controller or an analog circuit; the logic control circuit is used to realize the above-mentioned fixed-frequency quasi-peak current control strategy; the drive circuit controls the opening and closing of each switch device according to the switch control signal generated by the logic control circuit.

[0102] Fig.13 Taking the inductor L1 phase as an example, a schematic diagram of the logic control circuit is given. The circuit uses a comparator to obtain the working current and voltage loop error V in real time. err and soft switching current I ZVS Comparison information, so as to ensure that the working current at point A can reach V err , and the above minimum soft switching current conditions are met at the four points A, B, C, and D. Timer 1 is used to control the switch device Q1 to turn on at the beginning of each current cycle. Timer 2 starts timing when the switch devices Q1 and Q3 are turned on at the same time. When its counting time reaches kV errWhen the comparator generates a turn-off signal for the switch device Q1, the timer 3 is used to prevent the switch devices Q3 and Q4 from being long-on or normally closed during the startup process.

[0103] Based on the above logic control implementation method, a corresponding simulation model was built in the circuit simulation software Simplis, and the operation of the circuit under various working conditions was simulated and verified. Fig.14 The main power topology simulation model is given. Fig.15 A simulation model of logic control circuit is given.

[0104] Table 1 gives the design parameters of the two-phase interleaved AC link converter in the simulation. Figure 16 to Figure 21 The converter operating current i is given when the input voltage is 60V, 48V, and 40V and the load current is 400A and 100A respectively. L1 、i L2 , resonant current i r , excitation current i m And the resonant tank input voltage v ab Waveform. Fig. 22 The soft switching conditions of the switching devices Q1 to Q4 under the fixed-frequency quasi-peak current control strategy are demonstrated. It can be seen that they all achieve complete zero-voltage turn-on. The working conditions of the switching devices Q5 to Q8 are exactly the same as those of the switching devices Q1 to Q4, so they will not be repeated here.

[0105] Fig.23 (a) shows the changes in the key waveforms of the converter when the load current suddenly decreases from 200A to 100A at a slew rate of 100A / us under the rated input voltage of 48V. Fig.23 (b) shows the local magnified i o 、v c and v o The waveform details show the supporting capacitor voltage v c Slightly rise, the output voltage v o Maximum overshoot 20mV. Fig.24 (a) shows the changes in the key waveforms of the converter when the load current suddenly increases from 100A to 200A at a slew rate of 100A / us under the rated input voltage of 48V. Fig.24 (b) shows the local magnified i o 、v c and v o The waveform details show the supporting capacitor voltage v c Slightly decreases, the output voltage v o Maximum drop 25mV.

[0106] Table 1 Parameter design of two-phase interleaved AC link converter

[0107]

Claims

1. A constant frequency quasi-peak current control method for a two-phase interleaved AC link converter topology, characterized in that The converter topology includes a two-phase interleaved Buck-Boost structure, a series resonant tank and a support capacitor C v ,in: The two-phase interleaved Buck-Boost structure is composed of switch devices Q1-Q8 and inductors L1-L2. The series resonant tank consists of a resonant inductor L r , resonant capacitor C r And transformer composition; The primary side of the converter is composed of four bridge arms formed by switching devices Q1 and Q2, Q3 and Q4, Q5 and Q6, Q7 and Q8, respectively. The two ends of the inductor L1 are respectively connected to the midpoint of the bridge arm formed by Q1 and Q2 and the midpoint of the bridge arm formed by Q3 and Q4, and the two ends of the inductor L2 are respectively connected to the midpoint of the bridge arm formed by Q5 and Q6 and the midpoint of the bridge arm formed by Q7 and Q8. The above devices together form a two-phase staggered Buck-Boost structure; the two rear bridge arms composed of switching devices Q3 and Q4, Q7 and Q8 together form a full-bridge inverter structure, and the series resonant tanks are connected at the midpoints a and b of the two rear bridge arms; The series resonant tank has a plurality of secondary windings and rectification circuits thereof to form a multi-phase parallel output; The supporting capacitor C v Connected in parallel at both ends of the two rear bridge arms of the two-phase interleaved Buck-Boost structure to provide support voltage for the series resonant tank; The fixed-frequency quasi-peak current control method controls the working current i of the inductors L1 and L2 in real time. L1 、i L2 waveform, to quickly adjust the output voltage V o The purpose of which: The working current i of the inductors L1 and L2 L1 、i L2 The waveform is modulated into a quadrilateral wave, and the phase difference between the two is 180°. The waveform contains four inflection points and four stages. The four inflection points are A, B, C, and D. When the input voltage is lower than the support capacitor voltage, the current waveform characteristics of the inductors L1 and L2 have point A higher than point B; when the input voltage is higher than the support capacitor voltage, the current waveform characteristics of the inductors L1 and L2 have point A lower than point B; when the input voltage is equal to the support capacitor voltage, the current waveform characteristics of the inductors L1 and L2 have point A equal to point B; The four stages are respectively the input stage T1, the input-output stage T2, the falling stage T3 and the clamping stage T4, the DA segment of the current waveform is the input stage T1, the AB segment is the input-output stage T2, the BC segment is the falling stage T3, and the CD segment is the clamping stage T4; The working current i of the inductor L1 L1 The waveform is as follows: During the input stage T1, the switch devices Q1 and Q4 are turned on, and the inductor L1 is connected in parallel to the input side voltage source V in , energy storage begins, and when the working current rises to point A, the switch device Q4 is turned off, and the current at point A in the inductor L1 is I A and the resonant tank excitation current I m The parasitic capacitances in the switch devices Q3 and Q4 are charged and discharged together, preparing for the zero voltage turn-on of the switch device Q3; then the circuit enters the input-output stage T2, during which the switch devices Q1 and Q3 are turned on, and the inductor L1 is connected to the input side power supply V in The series transfers energy to the output side, V in >V c In this state, the working current slope is positive, V in <V c In this state, the working current slope is negative, V c To support the capacitor voltage, Q1 is turned off when the working current reaches point B, and the current I B The parasitic capacitances of the switch devices Q1 and Q2 are charged and discharged respectively, preparing for the zero voltage turn-on of the switch device Q2; then the circuit enters the descending stage T3, during which the switch devices Q2 and Q3 are turned on, and the inductor L1 and the support capacitor C v In parallel, magnetic reset begins. In order to achieve zero voltage turn-on of the switch device Q1, the working current needs to drop to a negative value C during this stage. Then the switch device Q3 is turned off, and the current I C and the resonant tank excitation current I m The parasitic capacitance of the switching devices Q3 and Q4 is charged and discharged together, preparing for the zero voltage turn-on of the switching device Q4; during the clamping stage T4, the switching devices Q2 and Q4 are turned on, and the inductor does not exchange energy with the outside world. The reverse circulation in it discharges the parasitic capacitance before the switching device Q1 is turned on in the next cycle T1, thereby realizing the zero voltage turn-on of the switching device Q1; The working current i of the inductor L2 L The waveform is as follows: the inductor L2 starts to lag behind the inductor L1 by 180° in each phase T1 to T4. During the input phase T1, the switching devices Q5 and Q8 are turned on, and the inductor L2 is connected in parallel to the input side voltage source V in , energy storage begins, and when the working current rises to point A, the switch device Q8 is turned off, and the current at point A in the inductor L2 is I A and the resonant tank excitation current I m The parasitic capacitances in the switch devices Q7 and Q8 are charged and discharged together, preparing for the zero voltage turn-on of the switch device Q7; then the circuit enters the input-output stage T2, during which the switch devices Q5 and Q7 are turned on, and the inductor L2 is connected to the input side power supply V in The series transfers energy to the output side, V in >V c In this state, the working current slope is positive, V in <V c In this state, the working current slope is negative, V c To support the capacitor voltage, when the working current reaches point B, Q5 is turned off, and the current I B The parasitic capacitances of the switch devices Q5 and Q6 are charged and discharged respectively, in preparation for the zero voltage turn-on of the switch device Q6; then the circuit enters the descending stage T3, during which the switch devices Q6 and Q7 are turned on, and the inductor L2 and the support capacitor C v In parallel, magnetic reset begins. In order to achieve zero voltage turn-on of the switch device Q5, the working current needs to drop to a negative value C during this stage. Then the switch device Q5 is turned off, and the current I C and the resonant tank excitation current I m The parasitic capacitance of the switching devices Q7 and Q8 is charged and discharged together, preparing for the zero voltage turn-on of the switching device Q8; during the clamping stage T4, the switching devices Q6 and Q8 are turned on, and the inductor does not exchange energy with the outside world. The reverse circulation in it discharges the parasitic capacitance before the switching device Q5 is turned on in the next cycle T1, thereby realizing the zero voltage turn-on of the switching device Q5; The working current i of the inductors L1 and L2 L1 、i L2 The specific regulation process under different input voltages is as follows: Assume that the resonant tank and its secondary rectifier circuit are ideal devices with no additional losses, and the supporting capacitor C v In steady state, the voltage is constant at V c , since the resonant tank operates at the resonant frequency, it has a gain K r , and there is V o =K r ·V c ; When the input voltage V in =V c When the current AB segment slope is 0, and the absolute value of the current slope of the DA segment is equal to that of the BC segment, the working current waveform is an isosceles trapezoid, and the average value of the input current in one cycle of the power supply is equal to the current flowing to the support capacitor C v The average value of the transport current, that is, the area S1+S2 is equal to the area S2+S3, S1 is the area of ​​the geometric shape formed by the DA segment current and the abscissa, S2 is the area of ​​the geometric shape formed by the AB segment current and the abscissa, and S3 is the area of ​​the geometric shape formed by the BC segment current and the abscissa; When the input voltage V in <V c When the current AB segment has a negative slope, the absolute value of the current slope of the DA segment is smaller than that of the BC segment. As the input voltage decreases, the output voltage will drop transiently. At this time, the voltage loop output accumulates positively, and the voltage loop output V err Increase, the current I at point A A Increase, T2 stage duration in kV err The area S1+S2 is larger than the area S2+S3. k is the proportionality coefficient. The average value of the input current in one cycle of the power supply is greater than the support capacitor C. v The average value of the delivery current is used to stabilize the output voltage V o ; When the input voltage V in >V c When the current AB segment has a positive slope, the absolute value of the current slope of the DA segment is greater than that of the BC segment. As the input voltage increases, the output voltage will produce a transient overshoot. At this time, the voltage loop output accumulates negatively, V err Decrease, the current I at point A A Decreased, T2 phase duration in kV err The area S1+S2 is also reduced under the action of, making the area S1+S2 smaller than the area S2+S3, that is, the average value of the input current in one cycle of the power supply is less than the support capacitor C v The average value of the transmission current is used to achieve a stable output voltage V o ; The working current i of the inductors L1 and L2 L1 、i L2 At different load currents I o There are three working states: When the load current is large, i L1 and i L2 Working in the critical continuous state, point C coincides with point D, and the clamping stage T4 time is 0; When the load current I o decreases, which will cause the output voltage V o During transient overshoot, the compensator accumulates the error negatively, V err Decrease, the current I at point A A Decreased, T2 phase duration in kV err The converter input average current and output average current are reduced, thereby stabilizing the output voltage. As the converter input average current and output average current decrease, i L1 and i L2 Start working in the current discontinuous state; if the current I A and the current I at point B B Both are greater than the minimum soft switching current I ZVS , the working state at this time is called the non-clamped intermittent state; When the load current I o When further reduced, for V in <V c In the case of B Will first reduce to the minimum soft switching current I ZVS To ensure that the switching devices Q2 / Q6 can achieve ZVS, I B Clamp to I ZVS At this time, the working current enters the clamped discontinuous state, and the voltage regulation of the converter is only determined by V err Control I A Implementation; for V in >V c In the case of A Will first reduce to the minimum soft switching current I ZVS To ensure that the switching devices Q1 / Q5 can achieve ZVS, I A Clamp to I ZVS At this time, the working current enters the clamped intermittent state, and the voltage regulation of the converter is only determined by kV err Control T2 to achieve; for V in =V c In the case of A Equal to the current I at point B B , when I A Reduce to the minimum soft switching current I ZVS When it is clamped, the working current enters the clamped intermittent state, and the voltage regulation of the converter is only controlled by kV err Control T2 implementation.

2. The constant frequency quasi-peak current control method of the two-phase interleaved AC link converter topology according to claim 1 is characterized in that In the switching devices Q1 to Q8, the driving signal of the complementary conduction device has a dead time. During the dead time, the excitation current i m With the working current i L1 and i L2 Together, they charge and discharge the parasitic capacitance of the switching device to achieve ZVS switching. The working current i L1 and i L2 In the waveform, the minimum current amplitude at point C and point D is the minimum soft switching current I required to turn on the switching devices Q1 or Q5 and Q2 or Q6 ZVS. ZVS1 The minimum current amplitude at point B is the minimum soft switching current I required to turn on the switching device Q2 or Q6ZVS. ZVS2 The minimum current amplitude at point A is the minimum soft switching current I required to turn on the ZVS of the switching device Q3 or Q7. ZVS3 , where I ZVS2 According to formula (1), I ZVS1 and I ZVS3 According to the magnitude of the excitation current, the value is determined by formula (1) or (2): In the formula, C oss is the drain-source parasitic capacitance of the switching device, t dead is the dead time, and T is the working period of the two-phase interleaved AC link converter.

3. The constant frequency quasi-peak current control method of the two-phase interleaved AC link converter topology according to claim 1 is characterized in that The output voltage sampling value is subtracted from the given value, and the error voltage signal V is obtained through the compensator. err , current at point A I A , input-output stage T2 time is determined by V err and the proportional coefficient k, which is given by formula (3): I A =V err ,T2=k·V err (3) Input stage T1 and point B current I B According to formula (3), I A and T2 vs. k and V err It can be expressed by the relationship between, as shown in equations (4) and (5): Wherein, L is the inductance value of inductors L1 and L2; Then the expression (6) of the falling phase time T3 is obtained, and the expression (7) of the clamping phase time T4 is obtained according to the current working cycle T: T4=T-T1-T2-T3 (7) If the end point D of the current waveform of the previous current cycle is taken as the origin, the relationship between the four stages of the working current waveform and time t is given by the following formula: i4(t3~t4)=-I ZVS (11) Combining equations (3) to (11), the Buck-Boost structure of one phase in the two-phase interleaved AC link converter is derived to support capacitor C v The average current delivered is I c Expression (12): According to (12), the proportional coefficients k and I under different input voltages and loads can be obtained. A The value of In solving for k and I A The following restrictions need to be added (13): Among them, V err_max is the voltage loop error V err upper limit.

4. The constant frequency quasi-peak current control method of the two-phase interleaved AC link converter topology according to claim 1, characterized in that The output voltage sampling value is subtracted from the given value, and the error voltage signal V is obtained through the compensator. err , (1) Using V err Adjust the current I at point A in the working current waveform A , by V err And the proportional coefficient k together determine the sum of the input stage T1 and the input and output stage T2, that is, T1+T2=kV err ; (2) Using V err Adjust the current I at point A in the working current waveform A The input-output phase T2 time is determined by the proportionality coefficient k and the current working cycle T of the inductors L1 and L2, that is, T2 = kT; (3) Using V err Adjust the current I at point A in the working current waveform A The sum of the input phase T1 and the input-output phase T2 is determined by the proportionality coefficient k and the current duty cycle T of the inductors L1 and L2, that is, T1+T2=kT; (4) The above proportionality coefficient k is a constant or is proportional to V in 、V o , L, T, or I o It is a functional relationship, that is, k=f(V in ,V o ,L,T,I o ), where L is the inductance of inductors L1 and L2.

5. The constant frequency quasi-peak current control method of the two-phase interleaved AC link converter topology according to claim 1, characterized in that The converter input voltage V in Lower, equal to or higher than the support capacitor voltage V c The voltage amplitude between the midpoints a and b of the two rear bridge arms formed by the switching devices Q3 and Q4, Q7 and Q8 is always higher than the maximum input voltage, or is within the input voltage range, or is always lower than the minimum input voltage; the operating frequency of the converter is greater than 100kHz; the series resonant tank has a characteristic resonant frequency f r , operating at its characteristic resonant frequency f r When the gain K is fixed r , characteristic resonant frequency f r It is n times the operating frequency f of the two-phase interleaved Buck-Boost structure, where n is a positive integer; the alternating voltage and alternating current transmitted between the midpoints a and b of the two rear bridge arms composed of switching devices Q3 and Q4, Q7 and Q8 are in phase; the duty cycle of the upper tubes of the two rear bridge arms increases with the increase of load current, and when close to full load, the duty cycle is maintained at 0.4~0.5.

Images