Chip test data processing method, device and storage medium

Abstract

The present invention relates to the field of chip test data processing technology, and specifically discloses a chip test data processing method, device and storage medium, the method comprising: performing a basic test on a memory to be tested under a preset working environment, marking the memory to be tested that fails the basic test as a defective product, and marking the memory to be tested that passes the basic test as a non-defective product; performing a step-by-step standard test on the non-defective product, comparing the test results with the corresponding level test standards, and obtaining the quality grade of the non-defective product. The present invention performs quality testing on the memory by specifying multiple levels of test standards, ensuring that the memory can run stably and efficiently under different workloads and conditions. The test method of step-by-step standard testing effectively improves the reliability of the memory, reduces the failure rate, and at the same time improves the memory testing effect, thereby providing more specific and targeted product quality information.

Description

Technical Field

[0001] The present invention relates to the technical field of chip test data processing, and in particular to a chip test data processing method, device and storage medium. Background Art

[0002] With the rise of intelligent computing industries such as artificial intelligence, online finance, driverless cars, and intelligent medical care, the requirements for reliability of computing power infrastructure are getting higher and higher. In computing power systems, memory is a key component for data storage and transmission, and its performance and quality directly affect the operating efficiency and stability of the entire computer system.

[0003] For example, the invention patent with announcement number CN116718218B is a method for processing test data of an optoelectronic integrated sensor chip. The method includes: obtaining amplitude data during the operation of an optoelectronic integrated sensor chip acquisition device, dividing the operation process of the device into no less than two time periods, and obtaining the corresponding noise probability based on the amplitude data at each moment in each time period and the duration of each time period; obtaining a target matrix based on the amplitude data at each moment in time periods with the same duration; classifying the data in the target matrix to obtain various types of data corresponding to each row; obtaining the degree of noise influence in each time period based on the numerical distribution of each type of data in each row of data in the target matrix, the number of data in each type of data, and the noise probability, and then determining the window length corresponding to each time period; denoising the amplitude data using the sliding average method based on the window length to obtain denoised data.

[0004] For example, the invention application with publication number CN114064372A is a memory testing method and device, which includes using a preset test template to test the memory to be tested, and when it is judged that the memory to be tested is not a defective product according to the test results, performing a comprehensive test on the memory to be tested; the comprehensive test includes: performing parameter analysis on the memory parameters of each particle in the memory to be tested under a preset multi-type working environment, and obtaining a first static analysis measurement value of the memory to be tested; and when the first static analysis measurement value does not meet a preset first standard threshold, determining that the memory to be tested is a defective product, thereby using a comprehensive test to perform further in-depth quality analysis on the memory to be tested that is not a defective product in the initial screening, and then making a more accurate judgment on the memory quality, thereby effectively identifying and intercepting low-quality memory.

[0005] However, in the process of implementing the technical solution of the invention in the embodiments of the present application, the present application found that the above technology has at least the following technical problems: At present, traditional memory testing methods mostly use step-by-step testing, such as static testing, dynamic testing, aging testing, etc. These methods have achieved remarkable results in the preliminary detection of memory defects and failures. However, in the face of growing computing needs and diversified application scenarios, the step-by-step testing is not ideal in some complex or specific usage scenarios, and cannot provide users with more specific and targeted product quality information. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention provides a chip test data processing method, device and storage medium, which can effectively solve the problems involved in the above-mentioned background technology.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions: The first aspect of the present invention provides a chip test data processing method, including: performing a basic test on the memory to be tested under a preset working environment, obtaining the memory to be tested that has not passed the basic test, determining whether the memory to be tested that has not passed the basic test has a repair condition, and marking the memory to be tested that has a repair condition as a repair-permitted memory.

[0008] Perform a repair test on the repair-permitted memory, obtain repair test data of the repair-permitted memory, and obtain an appearance damage degree assessment index and a performance impairment degree assessment index of the repair-permitted memory after processing.

[0009] Based on the appearance damage degree assessment index and the performance impairment degree assessment index of the repair allowed memory, a comprehensive analysis is performed to obtain a repair reliability assessment value of the repair allowed memory, and based on the repair reliability assessment value of the repair allowed memory, it is determined whether the repair allowed memory has passed the repair test.

[0010] As a further method, a basic test is performed on the memory to be tested under a preset working environment, wherein the basic test includes: performing a system indicator test on the memory to be tested under a first preset working environment to obtain a first operating parameter, comparing the first operating parameter with a first preset standard, and extracting the memory to be tested that passes the system indicator test.

[0011] Under a second preset working environment, a reliability test is performed on the memory to be tested that has passed the system indicator test to obtain a second operating parameter, the second operating parameter is compared with the second preset standard, the memory that has passed the reliability test is marked as a non-defective product, and a repair test is performed on the memory that has failed the test, the memory that has passed the repair test is marked as a non-defective product, and the memory that has failed the repair test is marked as a defective product.

[0012] As a further method, the determination of whether the memory to be tested that has not passed the basic test meets the repair conditions comprises the following specific processes: obtaining the memory capacity of the memory to be tested, comparing the memory capacity of the memory to be tested with the set repair test permitted capacity; if the memory capacity of the memory to be tested is greater than or equal to the repair test permitted capacity, marking the memory to be tested as repair permitted memory, repairing the repair permitted memory, and subjecting the repaired repair permitted memory to the basic test.

[0013] As a further method, the processing obtains an appearance damage degree assessment index of the repair-allowed memory. The specific process is: obtaining the length, width and height of the repair-allowed memory, and establishing an actual size matrix of the repair-allowed memory, while extracting the standard length, standard width and standard height of the repair-allowed memory from a memory test database, and establishing a standard size matrix of the repair-allowed memory.

[0014] Obtain an appearance image of the repair-permitted memory, compare the appearance image of the repair-permitted memory with a memory standard appearance image stored in a memory test database, deploy a number of pixel points, and extract the pixel value of each pixel point on the appearance image of the repair-permitted memory and the pixel value of the corresponding pixel point on the memory standard appearance image.

[0015] Comprehensive analysis is used to obtain an evaluation index of the degree of damage to the memory that can be repaired.

[0016] As a further method, the performance impairment degree assessment index has a specific analysis process of: deploying several monitoring time points, collecting the working voltage and working current of the repaired permitted memory at each monitoring time point in the basic test, and obtaining the reference standard voltage, reference standard current and critical power consumption from the memory test database, and obtaining the power parameter abnormality assessment value of the repaired permitted memory after processing.

[0017] The signal rise time and signal fall time of the repair-permitted memory are obtained, and the critical signal rise time and critical signal fall time are obtained from the memory test database. A comprehensive analysis is performed to obtain a performance impairment degree evaluation index of the repair-permitted memory.

[0018] As a further method, the repair-permitted memory is judged whether it has passed the repair test based on the repair reliability evaluation value of the repair-permitted memory. The specific process is: obtaining a set repair reliability evaluation threshold from a memory test database, comparing the repair reliability evaluation value of the repair-permitted memory with the repair reliability evaluation threshold; if the repair reliability evaluation value of the repair-permitted memory is greater than or equal to the repair reliability evaluation threshold, the repair-permitted memory is deemed to have passed the repair test; if the repair reliability evaluation value of the repair-permitted memory is less than the repair reliability evaluation threshold, the repair-permitted memory is deemed to have failed the repair test.

[0019] As a further method, the appearance damage degree evaluation index of the repair permission memory is specifically expressed as:

[0020]

[0021] In the formula, Indicates the damage assessment index of the memory that can be repaired. Indicates the pixel value of the i-th pixel on the appearance image of the repaired allowed memory, Represents the pixel value of the i-th pixel on the memory standard appearance image, Indicates the allowable deviation pixel value, Represents the size of the jth column of the actual size matrix A that repairs the allowed memory, Indicates the size value of the jth column of the standard size matrix E for repairing the allowed memory, i represents the number of each pixel, i=1,2,3,...,n, n represents the total number of pixels, j represents the number of columns in the actual size matrix and the standard size matrix, j=1,2,3, It represents the impact factor of the appearance damage assessment corresponding to the set appearance image deviation. It indicates the impact factor of the appearance damage degree assessment corresponding to the set unit size deviation.

[0022] As a further method, it also includes: performing grade-by-grade standard tests on non-defective products to obtain test data results, and comparing them with grade test standards to obtain quality grades of non-defective products.

[0023] The step-by-step standard testing includes standard testing for standard products, standard testing for superior products and standard testing for superior refined products.

[0024] The second aspect of the present invention provides a chip test data processing device, comprising: a processor and a memory and a network interface connected to the processor; the network interface is connected to a non-volatile memory in a server; when the processor is running, it calls a computer program from the non-volatile memory through the network interface, and runs the computer program through the memory to execute any one of the methods described in the above inventions.

[0025] A third aspect of the present invention provides a chip test data processing storage medium, comprising: a computer program stored therein, wherein when the computer program is run on a computer, the computer executes any chip test data processing method of the present invention.

[0026] Compared with the prior art, the embodiments of the present invention have at least the following advantages or beneficial effects:

[0027] (1) The present invention provides a chip test data processing method, device and storage medium, and performs quality testing on memory by specifying multiple levels of test standards to ensure that the memory can operate stably and efficiently under different workloads and conditions. The test method of step-by-step standard testing effectively improves the reliability of the memory, reduces the failure rate, and improves the memory test effect, thereby providing more specific and targeted product quality information.

[0028] (2) By analyzing the signal rise time and signal fall time of the memory, the present invention can determine whether the memory signal has distortion, jitter and other problems, and then evaluate the overall signal quality of the memory bar, which helps to optimize data transmission efficiency and reduce data loss and errors. At the same time, the analysis of memory signal transmission quality can help optimize memory management strategies, thereby improving system response speed.

[0029] (3) The present invention analyzes the appearance and performance of the repaired memory, quantitatively evaluates the effect of memory repair, and conducts comprehensive tests on the repaired memory stick to ensure that the repaired memory stick has good stability and performance, significantly reduces system problems caused by memory stick failure, reduces the risk of system crashes and data loss, and thus enhances the overall reliability and durability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention is further described using the accompanying drawings, but the embodiments in the accompanying drawings do not constitute any limitation to the present invention. A person skilled in the art can obtain other drawings based on the following drawings without creative work.

[0031] Figure 1 It is a schematic diagram of the method flow of the present invention.

[0032] Figure 2 A schematic diagram of a memory quality grading standard involved in an embodiment of the present invention.

[0033] Figure 3 The figure is a schematic diagram of the memory quality grading process involved in an embodiment of the present invention.

[0034] Figure 4 It is a schematic diagram of the relationship function between the appearance damage degree assessment index and the repair reliability assessment value involved in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0036] Reference Figure 1 As shown, the first aspect of the present invention provides a chip test data processing method, including: performing a basic test on the memory to be tested under a preset working environment, obtaining the memory to be tested that has not passed the basic test, determining whether the memory to be tested that has not passed the basic test has a repair condition, and marking the memory to be tested that has a repair condition as a repair-permitted memory.

[0037] Perform a repair test on the repair-permitted memory, obtain repair test data of the repair-permitted memory, and obtain an appearance damage degree assessment index and a performance impairment degree assessment index of the repair-permitted memory after processing.

[0038] Specifically, a basic test is performed on the memory to be tested under a preset working environment, wherein the basic test includes: performing a system indicator test on the memory to be tested under a first preset working environment to obtain a first operating parameter, comparing the first operating parameter with a first preset standard, and extracting the memory to be tested that passes the system indicator test.

[0039] In this embodiment, the system index test includes the core parameter JEDEC (Joint Electron Device Engineering Council) standard test and the standard signal integrity test. The obtained test index is compared with the preset qualified index standard. If the test index meets the qualified index standard, it indicates that the memory to be tested has passed the test.

[0040] Under a second preset working environment, a reliability test is performed on the memory to be tested that has passed the system indicator test to obtain a second operating parameter, the second operating parameter is compared with the second preset standard, the memory that has passed the reliability test is marked as a non-defective product, and a repair test is performed on the memory that has failed the test, the memory that has passed the repair test is marked as a non-defective product, and the memory that has failed the repair test is marked as a defective product.

[0041] In this embodiment, the reliability test refers to the basic system test, including appearance inspection, DC parameter (direct current) test (open and short circuit test, current power consumption test, voltage parameter test, etc., where the voltage range at least covers the maximum voltage value and the minimum voltage value defined by the JEDEC standard), AC parameter (alternating current) test (mainly measuring electrical parameters related to time, including: frequency, access delay time, refresh time, data retention time and other memory core parameter tests).

[0042] Specifically, determine whether the memory to be tested that has not passed the basic test meets the repair conditions. The specific process is: obtain the memory capacity of the memory to be tested, compare the memory capacity of the memory to be tested with the set repair test permitted capacity, if the memory capacity of the memory to be tested is greater than or equal to the repair test permitted capacity, mark the memory to be tested as repair permitted memory, repair the repair permitted memory, and perform basic testing on the repaired repair permitted memory.

[0043] It should be understood that in this embodiment, whether the memory has the repair test capability is determined based on the memory capacity. The set repair test permission capacity can be extracted from the memory test database. According to the DDR4 (Double Data Rate 4th Generation Synchronous Dynamic Random-Access Memory, i.e., the fourth generation double data rate synchronous dynamic random access memory) standard, memories with a capacity of 8Gb and above must be equipped with a PPR (Post Package Repair) function. Therefore, if the memory capacity reaches or exceeds 8Gb, it can be determined that the memory has the ability to perform PPR repair. At the same time, you can also consult the technical manual or data sheet of the memory to find out whether it explicitly mentions support for the PPR repair function.

[0044] It should be understood that PPR repair means that when a row in a memory is damaged, an algorithm is used to map the damaged row to a redundant row, so that the redundant row is used for data transmission to repair the memory error. Equipping redundant rows is a necessary condition for PPR repair.

[0045] Specifically, the appearance damage degree assessment index of the repair-allowed memory is obtained by processing, and the specific process is: obtaining the length, width and height of the repair-allowed memory, and establishing an actual size matrix of the repair-allowed memory, and at the same time extracting the standard length, standard width and standard height of the repair-allowed memory from the memory test database, and establishing a standard size matrix of the repair-allowed memory.

[0046] It should be understood that in this embodiment, the memory length refers to the size of the memory bar along its longest side, the memory width refers to the lateral size of the memory bar at its widest part, perpendicular to the length direction, and the memory height refers to the size of the memory bar from bottom to top, perpendicular to the length and width directions.

[0047] In this embodiment, the size of the repair-approved memory can be measured by a scanner. The accuracy and consistency of the size can indirectly indicate the control level of the production process, which is one of the foundations for ensuring the performance, reliability and compatibility of the memory stick.

[0048] Obtain an appearance image of the repair-permitted memory, compare the appearance image of the repair-permitted memory with a memory standard appearance image stored in a memory test database, deploy a number of pixel points, and extract the pixel value of each pixel point on the appearance image of the repair-permitted memory and the pixel value of the corresponding pixel point on the memory standard appearance image.

[0049] It should be understood that in this embodiment, an industrial camera is used to collect a high-precision image of the repair permission memory and provide accurate pixel values ​​of each pixel. The image pixel value is the basic unit that constitutes a digital image and is a quantitative representation of a pixel. In a digital image, each pixel stores one or more numerical values ​​that describe the color or brightness of the pixel. In this embodiment, the pixel value can be expressed as a grayscale value of each pixel. By analyzing the image of the repair permission memory, it can be used to check whether there are scratches, stains or other physical defects on the surface of the memory bar, ensuring that the mass-produced memory bars have a consistent appearance and structure, which helps to improve the stability of the production process and the effectiveness of quality control.

[0050] Comprehensive analysis is used to obtain an evaluation index of the degree of damage to the memory that can be repaired.

[0051] In a specific embodiment, the allowable deviation pixel value is obtained from the memory test database, and the shape damage degree assessment influencing factors corresponding to the set appearance image deviation and size deviation are extracted from the memory test database, and the shape damage degree assessment index of the repair-allowed memory is obtained through comprehensive analysis. The specific numerical expression is:

[0052]

[0053] In the formula, Indicates the damage assessment index of the memory that can be repaired. Indicates the pixel value of the i-th pixel on the appearance image of the repaired allowed memory, Represents the pixel value of the i-th pixel on the memory standard appearance image, Indicates the allowable deviation pixel value, Represents the size of the jth column of the actual size matrix A that repairs the allowed memory, Indicates the size value of the jth column of the standard size matrix E for repairing the allowed memory, i represents the number of each pixel, i=1,2,3,...,n, n represents the total number of pixels, j represents the number of columns in the actual size matrix and the standard size matrix, j=1,2,3, It represents the impact factor of the appearance damage assessment corresponding to the set appearance image deviation. It indicates the impact factor of the appearance damage degree assessment corresponding to the set unit size deviation.

[0054] In this embodiment, the actual size matrix of the allowed memory is repaired , a standard size matrix , the first column elements in the two matrices represent the length dimension, the second column elements represent the width dimension, and the third column elements represent the height dimension.

[0055] In a specific embodiment, the appearance damage degree assessment index of the repair-permitted memory is used to quantitatively assess the appearance damage degree of the repair-permitted memory from two perspectives: appearance image deviation and size deviation. The larger the appearance image pixel value deviation and each dimension size deviation, the larger the corresponding appearance damage degree assessment index of the repair-permitted memory, indicating that the appearance damage degree of the repair-permitted memory is more serious. The formula comprehensively considers the appearance image deviation and actual size deviation of the repair-permitted memory, and the appearance damage degree assessment influencing factors corresponding to the appearance image deviation and size deviation can be adjusted according to actual test requirements to adapt to different assessment scenarios and requirements. The appearance damage degree assessment results of the repair-permitted memory can provide guidance for memory repair, help determine the focus and priority of repair, and thus improve repair efficiency and effectiveness.

[0056] It should be understood that in this embodiment, the value range of the appearance damage degree assessment influencing factors corresponding to the appearance image deviation and size deviation is between 0 and 1. A mapping set of images and sizes and corresponding appearance damage degree assessment influencing factors can be established through memory test history data, and the appearance damage degree assessment influencing factors corresponding to the appearance image deviation and size deviation can be obtained from the mapping set based on the pixel value and size of the repair-allowed memory in the actual test.

[0057] In a specific embodiment, there is a close connection between appearance image deviation and size deviation. On the one hand, some physical damage that causes image deviation may lead to size deviation; on the other hand, slight changes in size may also affect the appearance image difference of the memory. By analyzing the appearance image and actual size of the repair-approved memory, the full picture of the damage can be captured from multiple dimensions, which helps to improve the accuracy of judging the degree and type of damage and provide data basis for subsequent repair decisions.

[0058] Specifically, the performance impairment degree assessment index has a specific analysis process as follows: deploy several monitoring time points, collect the working voltage and working current of the repaired and permitted memory at each monitoring time point in the basic test, and obtain the reference standard voltage, reference standard current and critical power consumption from the memory test database, and obtain the power parameter abnormality assessment value of the repaired and permitted memory after processing.

[0059] It should be understood that in this embodiment, the operating voltage and operating current of the repair permission memory are monitored by a voltage sensor and a current sensor. Reasonable memory voltage selection is crucial to computer performance. Too high or too low voltage may cause computer crashes, data loss and other problems. When the memory is overclocked, the current demand for the CPU and memory will increase. Properly increasing the current supply can ensure that the memory and CPU run stably in the overclocked state and improve performance. However, excessive current may cause hardware damage or overheating. Therefore, it is necessary to carefully set the current parameters to ensure overclocking within a safe range.

[0060] The power consumption of the repair-permitted memory can be obtained by multiplying the operating voltage and the operating current. Reducing the operating voltage of the memory can significantly reduce the power consumption. Low power consumption not only helps to save energy and reduce emissions, but also reduces the computer's heat dissipation requirements and improves the stability and reliability of the system.

[0061] In a specific embodiment, the power parameter abnormality assessment influencing factors corresponding to the set voltage, current and power consumption are extracted from the memory test database, and the set allowable deviation voltage and allowable deviation current are obtained from the memory test database, and the power parameter abnormality assessment value of the repair-permitted memory is obtained through comprehensive analysis. The specific numerical expression is:

[0062]

[0063] In the formula, Indicates that the abnormal evaluation value of the power parameter of the allowed memory is repaired. represents the operating voltage at the tth monitoring time point, represents the operating current at the tth monitoring time point, Indicates the reference standard voltage, Indicates the allowable deviation voltage, Indicates the reference standard current, Indicates the allowable deviation current, represents the critical power consumption, Indicates the impact factor of power parameter abnormality assessment corresponding to the set voltage, Indicates the impact factor of power parameter abnormality assessment corresponding to the set current, It represents the power parameter abnormality assessment impact factor corresponding to the set power consumption, t represents the number of each monitoring time point, t=1,2,3,...,s, s represents the total number of monitoring time points.

[0064] It should be understood that in this embodiment, the value range of the power parameter abnormality assessment impact factor corresponding to the voltage, current and power consumption is between 0 and 1. A mapping set of voltage, current and power consumption and the corresponding power parameter abnormality assessment impact factor can be established through memory test history data, and the power parameter abnormality assessment impact factor corresponding to the voltage, current and power consumption can be obtained from the mapping set based on the voltage, current and power consumption collected in the actual test.

[0065] Table 1 Example of power parameter abnormality evaluation value data

[0066]

[0067] As shown in Table 1, in a specific embodiment, =1.2V, =1A, =0.05V, =0.1A, =2W, =0.5, =0.5, =0.7. In this embodiment, in order to simplify the calculation, it is assumed that five groups of monitoring time data are collected, and the values ​​of each group of data are the same. The power parameter abnormality evaluation value is used to quantitatively evaluate the degree of abnormality of the power parameters of the repair-permitted memory in normal operation. The power parameter abnormality evaluation value is related to the working voltage and working current of the repair-permitted memory. The more the working voltage and working current deviate from the standard value, the larger the corresponding power parameter abnormality evaluation value, indicating that the power parameters of the repair-permitted memory are more abnormal. At the same time, the power parameter abnormality evaluation value is also affected by the product of the working voltage and the working current. The larger the product of the working voltage and the working current, the greater the power consumption of the repair-permitted memory, and the larger the corresponding power parameter abnormality evaluation value.

[0068] The formula comprehensively considers three important power parameters: voltage, current, and power consumption, and by comparing with reference values ​​and allowable deviations, it can comprehensively evaluate and repair abnormal states that allow memory to work. By setting different power parameter abnormality evaluation influencing factors, the importance of each parameter in the evaluation can be adjusted according to actual needs, so that the evaluation results are more in line with actual needs. The formula uses the hyperbolic tangent function to normalize the average power parameter abnormality evaluation value, so that the value range of the power parameter abnormality evaluation value is limited to between 0 and 1, which is convenient for subsequent processing and analysis.

[0069] The signal rise time and signal fall time of the repair-permitted memory are obtained, and the critical signal rise time and critical signal fall time are obtained from the memory test database. A comprehensive analysis is performed to obtain a performance impairment degree evaluation index of the repair-permitted memory.

[0070] It should be understood that in this embodiment, the signal waveform can be collected by an oscilloscope to obtain the signal rise time and signal fall time of the repair permission memory. The rise time and fall time of the memory signal directly reflect the quality of the signal. Shorter rise and fall times mean that the signal changes rapidly and stably, which is conducive to accurate data transmission. By measuring these time parameters, it can be determined whether the memory signal has distortion, jitter and other problems, and then the overall signal quality of the memory stick can be evaluated.

[0071] In a specific embodiment, the performance impairment degree evaluation influencing factors corresponding to the set power parameters and signal transmission parameters are obtained from the memory test database, and the performance impairment degree evaluation index of the repair-permitted memory is obtained through comprehensive analysis. The specific numerical expression is:

[0072]

[0073] In the formula, Indicates the performance barrier evaluation index for repairing permitted memory. Indicates that the abnormal evaluation value of the power parameter of the allowed memory is repaired. Indicates the signal rise time of the repair grant memory, Indicates the fall time of the signal that repairs the memory grant, represents the critical signal rise time, represents the critical signal fall time, Indicates the performance impairment assessment impact factor corresponding to the set power parameters, Indicates the performance impairment degree assessment impact factor corresponding to the set signal transmission parameters.

[0074] It should be understood that in this embodiment, the value range of the performance obstacle degree assessment impact factor corresponding to the power parameters and signal transmission parameters is between 0 and 1. A mapping set of power parameters and signal transmission parameters and corresponding performance obstacle degree assessment impact factors can be established through memory test history data, and the performance obstacle degree assessment impact factors corresponding to the power parameters and signal transmission parameters can be obtained from the mapping set based on the power parameters and signal transmission parameters collected in the actual test.

[0075] In this embodiment, the performance impairment degree evaluation index of the repair-permitted memory is used to quantitatively evaluate the performance abnormality of the repair-permitted memory in the basic test. The performance impairment degree evaluation index is jointly determined by the power parameter abnormality evaluation value, the signal rise time and the signal fall time. The larger the power parameter abnormality evaluation value, the signal rise time and the signal fall time, the larger the corresponding performance impairment degree evaluation index is, indicating that the performance of the repair-permitted memory is more abnormal.

[0076] The formula combines the power parameter abnormality assessment value and the signal transmission parameter to provide a comprehensive repair-permitted memory performance impairment assessment index, which helps to fully understand the performance status of the memory. The formula contains two influencing factors, and the values ​​of the influencing factors can be adjusted according to specific application scenarios or needs, so as to more accurately reflect the impact of different parameters on the degree of performance impairment. By using this formula, different types of repair-permitted memory can be standardized for performance evaluation, which is convenient for comparison and selection, and has important guiding significance for the research and development, production, testing and sales of memory products.

[0077] Based on the appearance damage degree assessment index and the performance impairment degree assessment index of the repair allowed memory, a comprehensive analysis is performed to obtain a repair reliability assessment value of the repair allowed memory, and based on the repair reliability assessment value of the repair allowed memory, it is determined whether the repair allowed memory has passed the repair test.

[0078] In a specific embodiment, the repair reliability assessment influencing factors corresponding to the set appearance damage degree assessment index and performance obstacle degree assessment index are extracted from the memory test database, and the repair reliability assessment value of the repair-permitted memory is obtained through comprehensive analysis. The specific numerical expression is:

[0079]

[0080] In the formula, Indicates the repair reliability evaluation value of the repair permission memory, represents a natural constant, Indicates the damage assessment index of the memory that can be repaired. Indicates the performance barrier evaluation index for repairing permitted memory. It represents the repair reliability assessment impact factor corresponding to the set appearance damage assessment index. It represents the repair reliability assessment impact factor corresponding to the set performance impairment degree assessment index.

[0081] It should be understood that the value range of the repair reliability assessment influence factor corresponding to the appearance damage degree assessment index and the performance impairment degree assessment index in the present embodiment is between 0 and 1. A mapping set of the appearance damage degree assessment index and the performance impairment degree assessment index and the corresponding appearance damage degree assessment influence factor can be established through the memory test history data, and the repair reliability assessment influence factor corresponding to the appearance damage degree assessment index and the performance impairment degree assessment index can be obtained from the mapping set according to the appearance damage degree assessment index and the performance impairment degree assessment index obtained in the actual test.

[0082] like Figure 4 As shown, in a specific embodiment, let =0.6, =0.4, when =3, the relationship function between the appearance damage evaluation index and the repair reliability evaluation value is shown in curve a; when =5, the relationship function between the appearance damage evaluation index and the repair reliability evaluation value is shown in curve b; when =7, the relationship function between the appearance damage degree assessment index and the repair reliability assessment value is shown in curve c. The repair reliability assessment value of the repair-permitted memory is used to quantitatively evaluate the repair effect of the repair-permitted memory. The repair reliability assessment value is jointly determined by the appearance damage degree assessment index and the performance impairment degree assessment index. The larger the appearance damage degree assessment index and the performance impairment degree assessment index, the smaller the corresponding repair reliability assessment value, indicating that the repair effect of the repair-permitted memory is worse.

[0083] This formula converts the degree of physical damage and performance impairment of the repair-permitted memory into a specific repair reliability evaluation value, taking into account both the degree of physical damage and the degree of performance impairment, and multiplying them with their respective corresponding impact factors and then adding them together, thus achieving a comprehensive consideration of the two factors, making the evaluation result more objective and accurate. By adjusting the value of the impact factor, the degree of influence of different factors on the repair reliability evaluation can be flexibly set according to actual conditions, so that the evaluation result is more in line with actual needs.

[0084] In a specific embodiment, by analyzing the appearance and performance of the repaired memory, quantitatively evaluating the effect of the memory repair, and comprehensively testing the repaired memory stick, it is ensured that the repaired memory stick has good stability and performance, significantly reducing system problems caused by memory stick failure, reducing the risk of system crashes and data loss, and thus enhancing the overall reliability and durability of the system.

[0085] Specifically, whether the repair-permitted memory has passed the repair test is judged according to the repair reliability evaluation value of the repair-permitted memory. The specific process is: obtain the set repair reliability evaluation threshold from the memory test database, compare the repair reliability evaluation value of the repair-permitted memory with the repair reliability evaluation threshold, if the repair reliability evaluation value of the repair-permitted memory is greater than or equal to the repair reliability evaluation threshold, then the repair-permitted memory is regarded as having passed the repair test, if the repair reliability evaluation value of the repair-permitted memory is less than the repair reliability evaluation threshold, then the repair-permitted memory is regarded as having failed the repair test.

[0086] In a specific embodiment, non-defective products are subjected to grade-by-grade standard tests to obtain test data results, which are then compared with grade test standards to obtain the quality grade of the non-defective products.

[0087] The step-by-step standard testing includes standard testing for standard products, standard testing for superior products and standard testing for superior refined products.

[0088] In a specific embodiment, after the memory is quality tested, if it first passes the JEDEC standard, signal integrity test and basic system test, defective products are excluded. Then, if the product only meets the basic test requirements, it is judged as the original product level; if it passes the power-on and power-off restart successfully for 10 consecutive times and the basic system test, it is the standard product level; if the performance is better than the standard and passes more stringent tests, it is the superior product level; if it meets the highest quality standards, including special design and extreme testing, it is the premium product level. These classifications ensure comprehensive quality assurance of memory from basic to excellent.

[0089] The memory test database is used to store memory test related data, including the repair test allowed capacity, the repair reliability assessment influencing factors corresponding to the appearance damage degree assessment index and the performance obstacle degree assessment index, the standard length, standard width and standard height of the repair allowed memory, the standard appearance image of the memory, the allowable deviation pixel value, the appearance damage degree assessment influencing factors corresponding to the appearance image deviation and the size deviation, the reference standard voltage, the reference standard current, the critical power consumption, the power parameter abnormality assessment influencing factors corresponding to the voltage, current and power consumption, the allowable deviation voltage, the allowable deviation current, the critical signal rise time, the critical signal fall time, the performance obstacle degree assessment influencing factors corresponding to the power parameters and signal transmission parameters, and the repair reliability assessment threshold. The data in the memory test database can be obtained by integrating external data sources. Integrating external data sources requires cleaning and verifying the data, removing abnormal values, duplicate values ​​or erroneous data, and converting and standardizing the external data format to make it consistent with the memory test data format.

[0090] The second aspect of the present invention provides a chip test data processing device, comprising: a processor and a memory and a network interface connected to the processor; the network interface is connected to a non-volatile memory in a server; when the processor is running, it calls a computer program from the non-volatile memory through the network interface, and runs the computer program through the memory to execute any one of the methods described in the above inventions.

[0091] A third aspect of the present invention provides a chip test data processing storage medium, comprising: a computer program stored therein, wherein when the computer program is run on a computer, the computer executes any chip test data processing method of the present invention.

[0092] In a specific embodiment, the present invention provides a chip test data processing method, device and storage medium, and performs quality testing on memory by specifying multiple levels of test standards to ensure that the memory can operate stably and efficiently under different workloads and conditions. The test method of step-by-step standard testing effectively improves the reliability of the memory, reduces the failure rate, and improves the memory test effect, thereby providing more specific and targeted product quality information.

[0093] The above contents are merely examples and explanations of the structure of the present invention. The technicians in this technical field may make various modifications or additions to the specific embodiments described or replace them in a similar manner. As long as they do not deviate from the structure of the invention or exceed the scope defined by the present invention, they should all fall within the protection scope of the present invention.

Claims

1. A chip test data processing method, characterized in that: include: Performing a basic test on the memory to be tested under a preset working environment, obtaining the memory to be tested that fails the basic test, determining whether the memory to be tested that fails the basic test has a repair condition, and marking the memory to be tested that has the repair condition as a repair-permitted memory; Performing a repair test on the repair-permitted memory, obtaining repair test data of the repair-permitted memory, and obtaining an appearance damage degree assessment index and a performance impairment degree assessment index of the repair-permitted memory after processing; Comprehensively analyzing the appearance damage degree evaluation index and the performance impairment degree evaluation index of the repair-permitted memory to obtain a repair reliability evaluation value of the repair-permitted memory, and judging whether the repair-permitted memory passes the repair test according to the repair reliability evaluation value of the repair-permitted memory; The processing obtains the appearance damage degree evaluation index of the repair-permitted memory, and the specific process is: obtaining the length, width and height of the repair-permitted memory, and establishing an actual size matrix of the repair-permitted memory, and at the same time extracting the standard length, standard width and standard height of the repair-permitted memory from the memory test database, and establishing a standard size matrix of the repair-permitted memory; Acquire an appearance image of the repair-permitted memory, compare the appearance image of the repair-permitted memory with a memory standard appearance image stored in a memory test database, deploy a number of pixel points, and extract the pixel value of each pixel point on the appearance image of the repair-permitted memory and the pixel value of the corresponding pixel point on the memory standard appearance image; Comprehensive analysis to obtain the damage degree assessment index of the memory allowed to be repaired; The performance impairment degree evaluation index has a specific analysis process of: deploying several monitoring time points, collecting the working voltage and working current of the repair-permitted memory at each monitoring time point in the basic test, and obtaining the reference standard voltage, reference standard current and critical power consumption from the memory test database, and obtaining the power parameter abnormality evaluation value of the repair-permitted memory after processing; Acquire the signal rise time and signal fall time of the repair-permitted memory, and simultaneously acquire the critical signal rise time and critical signal fall time from the memory test database, and comprehensively analyze to obtain the performance obstacle degree evaluation index of the repair-permitted memory; The specific numerical expression of the appearance damage degree evaluation index of the repair permission memory is: In the formula, Indicates the damage assessment index of the memory that can be repaired. Indicates the pixel value of the i-th pixel on the appearance image of the repaired allowed memory, Represents the pixel value of the i-th pixel on the memory standard appearance image, Indicates the allowable deviation pixel value, Represents the size of the jth column of the actual size matrix A that repairs the allowed memory, Indicates the size value of the jth column of the standard size matrix E for repairing the allowed memory, i represents the number of each pixel, i=1,2,3,...,n, n represents the total number of pixels, j represents the number of columns in the actual size matrix and the standard size matrix, j=1,2,3, It represents the impact factor of the appearance damage assessment corresponding to the set appearance image deviation. Indicates the impact factor of the appearance damage assessment corresponding to the set unit size deviation; The specific numerical expression of the abnormal power parameter evaluation value of the repair permission memory is: In the formula, Indicates that the abnormal evaluation value of the power parameter of the allowed memory is repaired. represents the operating voltage at the tth monitoring time point, represents the operating current at the tth monitoring time point, Indicates the reference standard voltage, Indicates the allowable deviation voltage, Indicates the reference standard current, Indicates the allowable deviation current, represents the critical power consumption, Indicates the impact factor of power parameter abnormality assessment corresponding to the set voltage, Indicates the impact factor of power parameter abnormality assessment corresponding to the set current, Indicates the power parameter abnormality assessment impact factor corresponding to the set power consumption, t indicates the number of each monitoring time point, t=1,2,3,...,s, s indicates the total number of monitoring time points; The performance obstacle evaluation index of the repair allowed memory is specifically expressed as: In the formula, Indicates the performance barrier evaluation index for repairing permitted memory. Indicates that the abnormal evaluation value of the power parameter of the allowed memory is repaired. Indicates the signal rise time of the repair grant memory, Indicates the fall time of the signal that repairs the memory grant, represents the critical signal rise time, represents the critical signal fall time, Indicates the performance impairment assessment impact factor corresponding to the set power parameters, Indicates the performance impairment degree assessment impact factor corresponding to the set signal transmission parameters; The repair reliability evaluation value of the repair permission memory is specifically expressed as: In the formula, Indicates the repair reliability evaluation value of the repair permission memory, represents a natural constant, Indicates the damage assessment index of the memory that can be repaired. Indicates the performance barrier evaluation index for repairing permitted memory. It represents the repair reliability assessment impact factor corresponding to the set appearance damage assessment index. It represents the repair reliability assessment impact factor corresponding to the set performance impairment degree assessment index.

2. The chip test data processing method according to claim 1, characterized in that: The basic test is performed on the memory to be tested under a preset working environment, wherein the basic test includes: Performing a system index test on the memory to be tested under a first preset working environment to obtain a first operating parameter, comparing the first operating parameter with a first preset standard, and extracting the memory to be tested that passes the system index test, wherein the system index test includes a core parameter JEDEC standard test and a standard signal integrity test; Under a second preset working environment, a reliability test is performed on the memory to be tested that has passed the system indicator test to obtain a second operating parameter, the second operating parameter is compared with the second preset standard, the memory that has passed the reliability test is marked as a non-defective product, and a repair test is performed on the memory that has failed the test, the memory that has passed the repair test is marked as a non-defective product, and the memory that has failed the repair test is marked as a defective product.

3. The chip test data processing method according to claim 1, characterized in that: The specific process of judging whether the memory to be tested that fails the basic test is repairable is as follows: Obtain the memory capacity of the memory to be tested, and compare the memory capacity of the memory to be tested with the set repair test allowed capacity. If the memory capacity of the memory to be tested is greater than or equal to the repair test allowed capacity, mark the memory to be tested as repair allowed memory, repair the repair allowed memory, and perform basic testing on the repaired repair allowed memory.

4. The chip test data processing method according to claim 1, characterized in that: The specific process of judging whether the repair-permitted memory passes the repair test according to the repair reliability evaluation value of the repair-permitted memory is as follows: A set repair reliability assessment threshold is obtained from a memory test database, and the repair reliability assessment value of the repair-permitted memory is compared with the repair reliability assessment threshold. If the repair reliability assessment value of the repair-permitted memory is greater than or equal to the repair reliability assessment threshold, the repair-permitted memory is deemed to have passed the repair test; if the repair reliability assessment value of the repair-permitted memory is less than the repair reliability assessment threshold, the repair-permitted memory is deemed to have failed the repair test.

5. The chip test data processing method according to claim 1, characterized in that: Also includes: Conduct grade-by-grade standard tests on non-defective products, obtain test data results, and compare them with grade test standards to obtain the quality grade of non-defective products; The step-by-step standard testing includes standard testing for standard products, standard testing for superior products and standard testing for superior refined products.

6. A chip test data processing device, characterized in that: include: Processor and memory and network interfaces connected to the processor; The network interface is connected to a non-volatile memory in the server; When running, the processor retrieves a computer program from the non-volatile memory through the network interface, and runs the computer program through the memory to execute the method described in any one of claims 1 to 5.

7. A chip test data processing storage medium, characterized in that: include: A computer program is stored, and when the computer program is run on a computer, the computer executes the chip test data processing method according to any one of claims 1 to 5.

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