Cross type constant ratio timing system and method based on LVDS (Low Voltage Differential Signaling)

Abstract

The invention provides an LVDS (Low Voltage Differential Signaling)-based cross-type constant ratio timing system and method, and the system comprises a signal source module which is used for transmitting two paths of same initial signals; the input end of the signal amplification module is electrically connected with the output end of the signal source module, and the signal amplification module is used for amplifying one path of initial signal to obtain an amplified signal; the input end of the signal delay module is electrically connected with the output end of the signal amplification module, and the signal delay module is used for delaying the amplified signal to obtain a delay signal; the input P end of the LVDS comparator is electrically connected with the output end of the signal delay module, the input N end of the LVDS comparator is electrically connected with the output end of the signal source module, and the LVDS comparator is used for comparing the voltage amplitude of the other path of initial signal and the voltage amplitude of the delay signal and outputting a digital signal; and the input end of the time-to-digital conversion module is electrically connected with the output end of the LVDS comparator, and the time-to-digital conversion module is used for recording time information of constant ratio timing triggering of the digital signal. According to the invention, the phenomenon of multiple times of triggering timing can be effectively avoided, so that the reliability and accuracy of constant ratio triggering timing are improved.

Description

Technical Field

[0001] The invention relates to the field of nuclear electronics and detection technology, and in particular to a cross-type constant ratio timing system and method based on LVDS. Background Art

[0002] Nuclear energy detection is one of the important means of obtaining information in many fields such as nuclear physics experiments, nuclear medicine applications, and nuclear radiation measurements. High-quality nuclear energy spectrum data can better preserve the true information of the original radioactive particles, such as energy information, time information, etc.

[0003] The nuclear energy detection process is that the high-energy rays generated by the decay of radioactive nuclides are converted into scintillation photons through the front-end scintillation crystals, and the scintillation photons are converted into electrical pulse signals, also called scintillation pulses, by photoelectric detectors such as SiPM. The back-end collects and analyzes the scintillation pulses to obtain important information related to the properties of nuclear energy, such as energy information, time information, and position information. Among them, recording the arrival time of the scintillation pulses is the key to the nuclear energy detection electronics system.

[0004] Constant ratio timing is a timing method with a constant trigger ratio. Constant ratio timing can ensure that the timing signal is generated at a constant ratio point of the signal amplitude. Traditional constant ratio timing includes leading edge constant ratio timing and trailing edge constant ratio timing. The leading edge constant ratio timing method divides the signal into two, one for delay and the other for attenuation. The two signals are then compared by a high-speed comparator. When the leading edges of the two signals intersect, the timing is triggered. Leading edge timing delays and attenuates the signal separately, and both the signal and the external DC signal will be attenuated. In order to avoid the DC signal being completely attenuated during the attenuation process, which makes it impossible to be recognized by the subsequent circuit and affects the timing accuracy, people have proposed the delayed constant ratio timing method. The delayed constant ratio timing method simultaneously attenuates and delays one signal, and keeps the other signal unchanged, so that the two signals intersect on the trailing edge of the signal. When the two signals intersect on the trailing edge, the high-speed comparator generates a timing signal to realize the function of constant ratio timing. The delayed constant ratio timing method not only simplifies the circuit structure, but also reduces the timing error.

[0005] In the process of nuclear energy detection, since the scintillation pulse generated by the photodetector is a signal with the characteristics of fast linear rise and slow decay, and the signal actually has certain noise fluctuations, when using the traditional trailing edge constant ratio timing method, multiple intersections and multiple trigger timing phenomena will occur at the trailing edges of the two signals, and the false triggering phenomenon affects the accuracy of the constant ratio trigger timing. Therefore, according to the signal characteristics of the scintillation pulse, it is necessary to solve the false triggering phenomenon of the constant ratio timing, improve the reliability of the constant ratio timing, and increase the system integration. Summary of the invention

[0006] The object of the present invention is to provide a cross-type constant ratio timing system and method based on LVDS, aiming to solve the problem that the traditional constant ratio timing method has low timing accuracy due to multiple intersections and multiple trigger timings.

[0007] In a first aspect, the present invention provides a cross-type constant ratio timing system based on LVDS, the system comprising:

[0008] A signal source module, used for sending out two identical initial signals;

[0009] A signal amplification module, whose input end is electrically connected to the output end of the signal source module, and is used to amplify one of the initial signals to obtain an amplified signal;

[0010] A signal delay module, whose input end is electrically connected to the output end of the signal amplification module, and is used to delay the amplified signal to obtain a delayed signal;

[0011] An LVDS comparator, whose input P terminal is electrically connected to the output terminal of the signal delay module, and whose input N terminal is electrically connected to the output terminal of the signal source module, is used to compare the voltage amplitudes of the other path of the initial signal and the delayed signal, and output a digital signal;

[0012] The time digital conversion module has an input end electrically connected to the output end of the LVDS comparator and is used to record the time information of the constant ratio timing trigger of the digital signal.

[0013] In summary, according to the above-mentioned LVDS-based cross-type constant ratio timing system, the initial signal is divided into two paths, and one path of the initial signal is amplified and delayed in turn, and the other path of the initial signal is not processed, and then the voltage amplitude of the delayed signal obtained after the amplification and delay is compared with the other path of the initial signal by the LVDS comparator to ensure that the constant ratio timing intersection is located at the trailing edge of the original signal and the leading edge of the amplified delay signal, effectively avoiding the phenomenon of multiple triggering timing, thereby improving the reliability and accuracy of the constant ratio triggering timing.

[0014] Furthermore, the signal source module is used to send an initial signal according to the following formula:

[0015]

[0016] Among them, f 原 (x) represents the initial signal, A represents the peak value of the initial signal, t0 represents the time when the initial signal reaches the peak value, and t1 represents the time when the initial signal ends attenuation.

[0017] Furthermore, the LVDS comparator is used to detect the voltage amplitude of the delayed signal and the voltage amplitude of the initial signal;

[0018] When it is detected that the voltage amplitude of the delayed signal is less than or equal to the voltage amplitude of the initial signal, a low-level digital signal is output;

[0019] When it is detected that the voltage amplitude of the delayed signal is greater than the voltage amplitude of the initial signal, a high-level digital signal is output.

[0020] Furthermore, it is defined that the logic state of a low-level digital signal is 0, and the logic state of a high-level digital signal is 1.

[0021] Furthermore, the intersection time of the initial signal and the delayed signal is calculated according to the following formula:

[0022]

[0023] Among them, t x represents the intersection time of the initial signal and the delayed signal, ɑ represents the signal amplification coefficient of the signal amplification module, and Δt represents the delay time of the signal delay module;

[0024] The signal amplification factor of the signal amplification module and the delay time of the signal delay module are set so that the intersection time is located at the trailing edge of the initial signal and the leading edge of the delayed signal.

[0025] Furthermore, the step of setting the signal amplification factor of the signal amplification module and the delay time of the signal delay module so that the intersection time is located at the trailing edge of the initial signal and the leading edge of the delayed signal includes:

[0026] Set the signal amplification factor and delay time according to the following formulas:

[0027] t o ≤Δt <t1

[0028]

[0029] Furthermore, the time-to-digital conversion module comprises:

[0030] A trigger signal source electrically connected to the output end of the LVDS comparator, the trigger signal source being used to forward the digital signal;

[0031] A delay chain and a coarse counter are respectively electrically connected to the output end of the trigger signal source, and it is defined that whenever the rising edge of the clk of the system clock arrives, the coarse count value of the coarse counter is increased by 1, and the coarse counter is used to output the coarse count value corresponding to the rising edge of the digital signal, and the delay chain is used to output an order of magnitude signal, and the order of magnitude signal includes at least one character, and the number of the characters is proportional to the distance from the rising edge of the digital signal to the next rising edge of the clk of the system clock;

[0032] an encoder electrically connected to the output end of the delay chain, the encoder being used to count the number of characters to output a detailed count value;

[0033] A control unit is electrically connected to the output end of the encoder and the output end of the coarse timer, and the control unit is used to output the time information of the rising edge of the digital signal according to the coarse count value and the fine count value.

[0034] Furthermore, the magnitude signal is triggered by detecting a rising edge of a digital signal and terminated when the next rising edge of the system clock clk arrives.

[0035] Furthermore, the time information of the rising edge of the digital signal is calculated according to the following formula:

[0036] Time information = coarse measurement time - fine measurement time

[0037] Coarse measurement time = coarse count value × coarse counter clock cycle

[0038] Detailed measurement time = detailed count value × average delay of each character in the delay chain.

[0039] In a second aspect, the present invention provides a cross-type constant ratio timing method based on LVDS, the method comprising:

[0040] Used to send out two identical initial signals;

[0041] amplifying one of the initial signals to obtain an amplified signal;

[0042] Delaying the amplified signal to obtain a delayed signal;

[0043] Comparing the voltage amplitudes of the initial signal and the delayed signal of the other path, and outputting a digital signal;

[0044] Record the time information of the constant ratio timing trigger of the digital signal.

[0045] Compared with the prior art, the present invention also has the following advantages:

[0046] The present invention uses the underlying carry delay chain and uses a combination of time interpolation, coarse time and fine time to construct a time digital conversion module, and its measurement accuracy can reach picoseconds. In addition, the interpolation technology combines the advantages of the coarse counter and the delay chain, effectively ensuring a wider time measurement dynamic range while improving the measurement accuracy, further improving the measurement accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1It is a structural schematic diagram of a cross-type constant ratio timing system based on LVDS proposed in one embodiment of the present invention;

[0048] Figure 2 A schematic diagram of the linearization processing of the cross-type constant ratio timing principle and the output of the LVDS comparator in one embodiment of the present invention;

[0049] Figure 3 A schematic diagram of the structure of a time-to-digital conversion module in one embodiment of the present invention;

[0050] Figure 4 Schematic diagram of a coarse counter and a fine counter in one embodiment of the present invention.

[0051] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0053] See also Figure 1 , which is a schematic diagram of the structure of a cross-type constant ratio timing system based on LVDS in one embodiment of the present invention, the system includes a signal source module, a signal amplification module, a signal delay module, an LVDS comparator, and a time digital conversion module, wherein:

[0054] The signal source module is made of a scintillation crystal and a silicon photodetector coupled by optical glue. The scintillation crystal generates fluorescence under the impact of high-energy particles such as gamma rays and x-rays. The silicon photodetector converts the fluorescence photons into electrons, and after amplification, it outputs an electrical pulse signal with the characteristics of rapid linear rise and slow decay, also known as a scintillation pulse. The signal source module is used to split the electrical pulse signal with the characteristics of rapid linear rise and slow decay into two, that is, to send out two identical initial signals, such as signal 1 and signal 2.

[0055] The input end of the signal amplification module is electrically connected to the output end of the signal source module. The signal amplification module is used to perform gain amplification on one of the signals 1 to obtain an amplified signal. The input end of the signal delay module is electrically connected to the output end of the signal amplification module to delay the signal 1 after passing through the signal amplification module. The signal 1 processed by the signal amplification module and the signal delay module is then processed to obtain a delayed signal.

[0056] The input P terminal of the LVDS comparator is electrically connected to the output terminal of the signal delay module, and the input N terminal thereof is electrically connected to the output terminal of the signal source module, that is, the signal 1 after amplification and delay processing is used as the input signal of the "P" terminal of the LVDS comparator. The signal 2 output by the signal source module is not amplified and delayed, and is connected to the "N" terminal of the LVDS comparator as the input signal of the "N" terminal of the LVDS comparator. The LVDS comparator is used to compare the voltage amplitude of the delayed signal (signal 1) after amplification and delay processing and the voltage amplitude of another initial signal (signal 2) after amplification and delay processing, and output a digital signal.

[0057] The input end of the time digital conversion module is electrically connected to the output end of the LVDS comparator, and is used to record the time information of the constant ratio timing trigger of the digital signal. That is to say, the digital pulse signal output by the LVDS comparator is used as the input of the time digital conversion module (TDC), and the rising edge of the digital pulse signal triggers the time digital conversion module (TDC) timing to record the time information of the intersection of analog pulse signal 1 and signal 2.

[0058] In summary, according to the above-mentioned LVDS-based cross-type constant ratio timing system, the initial signal is divided into two paths, and one path of the initial signal is amplified and delayed in turn, and the other path of the initial signal is not processed, and then the voltage amplitude of the delayed signal obtained after the amplification and delay is compared with the other path of the initial signal by the LVDS comparator to ensure that the constant ratio timing intersection is located at the trailing edge of the original signal and the leading edge of the amplified delay signal, effectively avoiding the phenomenon of multiple triggering timing, thereby improving the reliability and accuracy of the constant ratio triggering timing.

[0059] In some embodiments, Figure 2 As shown, the signal source module divides the electric pulse signal into two, and linearizes the signal with the characteristics of fast linear rise and slow decay, and then outputs two initial signals f 原 (x), the expression is:

[0060]

[0061] Among them, f 原 (x) represents the initial signal, A represents the peak value of the initial signal, t0 represents the time when the initial signal reaches the peak value, and t1 represents the time when the initial signal ends attenuation.

[0062] In some embodiments, the signal source module outputs f 原 (x) The signal is amplified by a times by the signal amplifier module and delayed by Δt by the signal delay module to obtain f 放+延 (x) signal, f 放+延 The expression of (x) signal is:

[0063]

[0064] Among them, f 放+延 (x) represents the delayed signal, ɑ represents the signal amplification factor of the signal amplification module, and Δt represents the delay time of the signal delay module.

[0065] In addition, in some embodiments, the LVDS comparator uses the differential port LVDS of the FPGA-ZYNQ series, whose two pins constitute a pair of differential pins "P" and "N", that is, the differential port LVDS has the function of comparing the voltage amplitude of the "P" and "N" terminals, f 放+延 (x) The signal is used as the input of the LVDS comparator "P" terminal, f 原 The (x) signal is used as the input to the “N” terminal of the LVDS comparator.

[0066] In addition, the LVDS comparator is specifically used to detect the voltage amplitude of the delayed signal and the voltage amplitude of the initial signal. For example, when the voltage amplitude of the "P" terminal signal 1 (the signal 1 here is actually the delayed signal obtained after amplification and delay processing) is lower than the voltage amplitude of the "N" terminal signal 2, the LVDS comparator outputs a low level; when the voltage amplitude of the "P" terminal signal 1 is higher than the voltage amplitude of the "N" terminal signal 2, the LVDS comparator outputs a high level. The analog pulse signals 1 and 2 are converted into digital pulse signals by the LVDS comparator. The rising edge of the digital pulse signal represents the moment when the voltage amplitudes of the analog pulse signals 1 and 2 are equal, also known as the intersection moment of the signals 1 and 2.

[0067] like Figure 2 As shown, f 原 (x) and f 放+延 (x) Two signals at t x Before the moment, when the delayed signal f is detected 放+延 The voltage amplitude of (x) is less than or equal to the initial signal f 原 (x) voltage amplitude, a low-level digital signal (logic state "0") is output, f 原 (x) and f 放+延 (x) Two signals at t x When f 原 (x) The voltage amplitude begins to exceed f 放+延(x) The voltage amplitude, that is, when the voltage amplitude of the delayed signal is greater than that of the initial signal, a digital signal with a high level is output, triggering the LVDS comparator to generate a digital pulse signal that flips from the logical state "0" to the logical state "1". The two signals intersect at the trailing edge of f 原 (x) and the leading edge of f 放+延 (x), showing a cross shape. The output signal of the LVDS comparator is as Figure 2 shown.

[0068] In addition, in some alternative embodiments, in order to precisely control the intersection moment, first let f 原 (x) = f 放+延 (x) to obtain the intersection moment of the initial signal and the delayed signal:

[0069]

[0070] where t x represents the intersection moment of the initial signal and the delayed signal, ɑ represents the signal amplification coefficient of the signal amplification module, and Δt represents the delay duration of the signal delay module.

[0071] It can be seen from the above formula that the intersection moment t x of the two signals is only related to the amplification coefficient ɑ and the delay Δt. Regardless of how the peak value A of the signal changes, t x triggers at a fixed ratio of the signal peak and is independent of the signal peak A, that is, the function of constant ratio timing.

[0072] In order to ensure that the intersection of the constant ratio timing of the signal is located at the trailing edge of the original signal and the leading edge of the amplified and delayed signal, showing a cross-shaped feature, it is necessary to control the amplification multiple a of the signal amplification module and the delay Δt of the signal delay module, effectively avoiding the phenomenon of multiple trigger timings and improving the reliability and accuracy of the constant ratio trigger timing.

[0073] Specifically, the delay Δt of the signal delay module first needs to satisfy t o ≤Δt < t1;

[0074] And when t o ≤Δt < t1, the amplification multiple needs to satisfy Otherwise, it cannot be guaranteed that the intersection of signal 1 and signal 2 is located at the trailing edge of the original signal and the leading edge of the amplified and delayed signal, showing a cross shape.

[0075] In addition, in some alternative embodiments, such as Figure 3As shown, the time digital conversion module includes a trigger signal source (Trigger) electrically connected to the output end of the LVDS comparator, a delay chain (Delay Chain) electrically connected to the output end of the trigger signal source, a coarse counter (Counter), an encoder (Decoder) electrically connected to the output end of the delay chain, and a control unit (Control) electrically connected to the output end of the encoder and the output end of the coarse timer, wherein:

[0076] The trigger signal source is used to forward the digital signal, that is, forward it to the delay chain and the coarse counter, see Figure 4 , which shows the signal of the system clock (clk), and defines that whenever the rising edge of the system clock clk arrives, the coarse count value of the coarse counter is increased by 1, such as Figure 4 As shown, the starting point of any count value corresponds to a clk rising edge of the system clock, and the end point of the count value corresponds to the next clk rising edge of the system clock. That is to say, one cycle of the system clock is exactly one count value, and the Counter count value increases by "1" with each clk rising edge.

[0077] Specifically, the coarse counter is used to output a coarse count value corresponding to the rising edge of the digital signal, and the delay chain is used to output an order of magnitude signal, which includes at least one character, and the number of characters is proportional to the distance from the rising edge of the digital signal to the rising edge of the clk of the next system clock. The order of magnitude signal is triggered by detecting the rising edge of the digital signal and terminated when the rising edge of the clk of the next system clock arrives.

[0078] Exemplarily, the rising edge of the digital signal forwarded by the Trigger triggers the Counter to output the rough count value at that time. At the same time, the rising edge of the Trigger triggers the Delay Chain to work. According to the moment when the rising edge of the Trigger enters the Delay Chain, the Delay Chain outputs continuous characters of different orders of magnitude. The number of continuous characters is proportional to the time interval from the rising edge of the Trigger signal to the rising edge of the next clk. In this embodiment, the character is "1". In some other embodiments, the character can also be other numbers.

[0079] The output of the Delay Chain is a series of continuous "1" digital signals. The output of the Delay Chain serves as the input of the encoder Decoder. The encoder Decoder calculates the number of continuous "1" output by the Delay Chain, that is, the fine count value; combined with the average delay of each bit "1" in the underlying carry chain, the time interval from the rising edge of the Trigger signal to the rising edge of the next clk can be obtained, that is, the fine measurement time fine.

[0080] Furthermore, the fine measurement time result fine and the coarse measurement time result T2 form a timestamp T1. Finally, the control unit Control stores and sends the time information and calculates the time information of the constant ratio timing trigger:

[0081] Coarse measurement time T2 = coarse count value × coarse counter clock cycle;

[0082] Fine measurement time fine = fine count value × average delay of each bit "1" in the carry chain;

[0083] Constant ratio timing trigger time T1 = coarse measurement time T2 - fine measurement time fine;

[0084] The TDC based on time interpolation technology cleverly uses the adder with low carry delay characteristics inside the FPGA as a delay unit Delay Chain and combines it with coding technology to push the time measurement accuracy from nanoseconds to picoseconds, effectively ensuring a wider time measurement dynamic range while improving measurement accuracy. While achieving the ability to record the trigger moment of constant ratio timing, it also improves the programmability and scalability of the system.

[0085] It should also be pointed out that the signal amplification module and signal delay module used in this embodiment are common signal amplifiers / chips and signal delayers / chips, and the control unit is generally an MCU chip or a CPU, etc.

[0086] In summary, according to the above-mentioned cross-type constant ratio timing system based on LVDS, by dividing the initial signal into two paths, and amplifying and delaying the initial signal of one path in turn, and not processing the initial signal of the other path, and then comparing the voltage amplitude of the delayed signal obtained after the amplification delay with the other initial signal through the LVDS comparator, it is ensured that the intersection of the constant ratio timing is located at the trailing edge of the original signal and the leading edge of the amplified delay signal, effectively avoiding the phenomenon of multiple trigger timing, thereby improving the reliability and accuracy of the constant ratio trigger timing. In addition, by utilizing the underlying carry delay chain and using the method of combining time interpolation, coarse time and fine time, a time digital conversion module is constructed, and its measurement accuracy can reach picoseconds. In addition, the interpolation technology combines the respective advantages of the coarse counter and the delay chain, while improving the measurement accuracy, it effectively guarantees a wider time measurement dynamic range, further improving the measurement accuracy.

[0087] An embodiment of the present invention further provides a cross-type constant ratio timing method based on LVDS, the method comprising steps S101 to S105, wherein:

[0088] S101: used to send two identical initial signals;

[0089] S102: amplifying one of the initial signals to obtain an amplified signal;

[0090] S103: delaying the amplified signal to obtain a delayed signal;

[0091] S104: comparing the voltage amplitudes of the initial signal and the delayed signal of another path, and outputting a digital signal;

[0092] S105: Record the time information of the constant ratio timing trigger of the digital signal.

[0093] In addition, in some optional embodiments, the method further includes:

[0094] The initial signal is generated according to the following formula:

[0095]

[0096] Among them, f 原 (x) represents the initial signal, A represents the peak value of the initial signal, t0 represents the time when the initial signal reaches the peak value, and t1 represents the time when the initial signal ends attenuation.

[0097] The method further comprises: detecting the voltage amplitude of the delayed signal and the voltage amplitude of the initial signal;

[0098] When it is detected that the voltage amplitude of the delayed signal is less than or equal to the voltage amplitude of the initial signal, a low-level digital signal is output;

[0099] When it is detected that the voltage amplitude of the delayed signal is greater than the voltage amplitude of the initial signal, a high-level digital signal is output.

[0100] Also included: obtaining a delay signal according to the following formula:

[0101]

[0102] Among them, f 放+延 (x) represents the delayed signal, ɑ represents the signal amplification coefficient of the signal amplification module, and Δt represents the delay time of the signal delay module.

[0103] The method further includes: calculating the intersection time of the initial signal and the delayed signal according to the following formula:

[0104]

[0105] Among them, t x represents the intersection time of the initial signal and the delayed signal, ɑ represents the signal amplification coefficient of the signal amplification module, and Δt represents the delay time of the signal delay module;

[0106] Setting the signal amplification factor of the signal amplification module and the delay time of the signal delay module so that the intersection time is located at the trailing edge of the initial signal and the leading edge of the delayed signal;

[0107] Also includes: setting the signal amplification factor and delay time according to the following formulas:

[0108] t o ≤Δt <t1

[0109]

[0110] It also includes: forwarding the digital signal;

[0111] Outputting a coarse count value corresponding to a rising edge of the digital signal;

[0112] Outputting an order of magnitude signal, the order of magnitude signal comprising at least one character, the number of the characters being proportional to the distance from the rising edge of the digital signal to the rising edge of the next system clock clk;

[0113] Calculate the number of characters to output the detailed count value;

[0114] Outputting time information of a rising edge of a digital signal according to the coarse count value and the fine count value;

[0115] The time information of the rising edge of the digital signal is calculated according to the following formula:

[0116] Time information = coarse measurement time - fine measurement time

[0117] Coarse measurement time = coarse count value × coarse counter clock cycle

[0118] Detailed measurement time = detailed count value × average delay of each character in the delay chain.

[0119] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A cross-type constant ratio timing system based on LVDS, characterized in that: The system comprises: A signal source module, used for sending out two identical initial signals; A signal amplification module, whose input end is electrically connected to the output end of the signal source module, and is used to amplify one of the initial signals to obtain an amplified signal; A signal delay module, whose input end is electrically connected to the output end of the signal amplification module, and is used to delay the amplified signal to obtain a delayed signal; An LVDS comparator, whose input P terminal is electrically connected to the output terminal of the signal delay module, and whose input N terminal is electrically connected to the output terminal of the signal source module, is used to compare the voltage amplitudes of the other path of the initial signal and the delayed signal, and output a digital signal; The time digital conversion module has an input end electrically connected to the output end of the LVDS comparator and is used to record the time information of the constant ratio timing trigger of the digital signal.

2. The LVDS-based cross-type constant ratio timing system according to claim 1, characterized in that: The signal source module is used to send out an initial signal according to the following formula: Among them, f 原 (x) represents the initial signal, A represents the peak value of the initial signal, t0 represents the time when the initial signal reaches the peak value, and t1 represents the time when the initial signal ends attenuation.

3. The LVDS-based cross-type constant ratio timing system according to claim 1, characterized in that: The LVDS comparator is used to detect the voltage amplitude of the delayed signal and the voltage amplitude of the initial signal; When it is detected that the voltage amplitude of the delayed signal is less than or equal to the voltage amplitude of the initial signal, a low-level digital signal is output; When it is detected that the voltage amplitude of the delayed signal is greater than the voltage amplitude of the initial signal, a high-level digital signal is output.

4. The LVDS-based cross-type constant ratio timing system according to claim 2, characterized in that: The delayed signal is obtained according to the following formula: Among them, f 放+延 (x) represents the delayed signal, ɑ represents the signal amplification coefficient of the signal amplification module, and Δt represents the delay time of the signal delay module.

5. The LVDS-based cross-type constant ratio timing system according to claim 2, characterized in that: The intersection time of the initial signal and the delayed signal is calculated according to the following formula: Among them, t x represents the intersection time of the initial signal and the delayed signal, ɑ represents the signal amplification coefficient of the signal amplification module, and Δt represents the delay time of the signal delay module; The signal amplification factor of the signal amplification module and the delay time of the signal delay module are set so that the intersection time is located at the trailing edge of the initial signal and the leading edge of the delayed signal.

6. The LVDS-based cross-type constant ratio timing system according to claim 5, characterized in that: The step of setting the signal amplification coefficient of the signal amplification module and the delay time of the signal delay module so that the intersection time is located at the trailing edge of the initial signal and the leading edge of the delayed signal comprises: Set the signal amplification factor and delay time according to the following formulas: t o ≤Δt<t1 7. The LVDS-based cross-type constant ratio timing system according to claim 1, characterized in that: The time-to-digital conversion module comprises: A trigger signal source electrically connected to the output end of the LVDS comparator, the trigger signal source being used to forward the digital signal; A delay chain and a coarse counter are respectively electrically connected to the output end of the trigger signal source, and it is defined that whenever the rising edge of the clk of the system clock arrives, the coarse count value of the coarse counter is increased by 1, and the coarse counter is used to output the coarse count value corresponding to the rising edge of the digital signal, and the delay chain is used to output an order of magnitude signal, and the order of magnitude signal includes at least one character, and the number of the characters is proportional to the distance from the rising edge of the digital signal to the next rising edge of the clk of the system clock; an encoder electrically connected to the output end of the delay chain, the encoder being used to count the number of characters to output a detailed count value; A control unit is electrically connected to the output end of the encoder and the output end of the coarse timer, and the control unit is used to output the time information of the rising edge of the digital signal according to the coarse count value and the fine count value.

8. The LVDS-based cross-type constant ratio timing system according to claim 7, characterized in that: The magnitude signal is triggered by detecting a rising edge of a digital signal and terminated when the next rising edge of the system clock clk arrives.

9. The LVDS-based cross-type constant ratio timing system according to claim 7, characterized in that: The time information of the rising edge of the digital signal is calculated according to the following formula: Time information = coarse measurement time - fine measurement time Coarse measurement time = coarse count value × coarse counter clock cycle Detailed measurement time = detailed count value × average delay of each character in the delay chain.

10. A cross-type constant ratio timing method based on LVDS, characterized in that: The method comprises: Used to send out two identical initial signals; amplifying one of the initial signals to obtain an amplified signal; Delaying the amplified signal to obtain a delayed signal; Comparing the voltage amplitudes of the initial signal and the delayed signal of the other path, and outputting a digital signal; Record the time information of the constant ratio timing trigger of the digital signal.

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