Design rule checking and verifying method based on shared database

Abstract

The invention discloses a design rule checking and verifying method based on a shared database. The method comprises the following steps: inputting a layout file to a shared database; obtaining a design rule file; preprocessing the shared database; obtaining physical information and electrical information; whether the physical size, the shape and the layout of the integrated circuit meet the design requirements or not is checked by means of an EDA tool for physical verification, and meanwhile error reporting is avoided by means of electrical information; outputting a detection report, and storing a result in a DRC result database; and correcting the errors, and circularly executing the process until all the errors are corrected. According to the method, the over-conservative interval requirement caused by static voltage calculation in a general design rule checking and verifying method can be avoided, false report errors are reduced, the area utilization rate is increased, the detection accuracy is improved, and the cycle time of an actual process is shortened.

Description

Technical Field

[0001] The technical field to which the present invention belongs is Electronic Design Automation (EDA), and mainly relates to a new type of design rule check (DRC) verification process in physical verification (Physical Verification). Background Art

[0002] Physical verification is a critical step in the integrated circuit (IC) design process, and its purpose is to ensure that the design meets all manufacturing-related physical requirements and design rules. The physical verification process includes multiple checking and verification steps to ensure the accuracy and manufacturability of the design data.

[0003] Design rule checking is a step in physical verification that automatically verifies that a design complies with specific manufacturing process rules, which define minimum dimensions, spacing, alignment, and other constraints in the layout to ensure that the circuit can be manufactured correctly and performs as expected.

[0004] DRC inspections include: minimum / maximum width and spacing rules, layer alignment and coverage rules, shape and pattern integrity, connectivity, ensuring there are no breaks or shorts, device matching and symmetry, heat-affected areas, and current density limitations.

[0005] The checking process is generally divided into six steps. First, design preparation, the designer creates the layout and prepares it for DRC checking. Second, rule loading, loading the design rule file of DRC. Third, check execution, using the DRC tool to automatically check the layout. Fourth, analyzing the results of the DRC check and identifying violations. Fifth, design correction, correcting the violations in the design based on the DRC results. Sixth, re-checking, the corrected design is checked again with DRC until all rules are met.

[0006] With the continuous advancement of technology nodes and the reduction of feature sizes, DRC faces many challenges. The increase in rule complexity requires the processing of more layers and more complex design rules; process variation requires the consideration of the impact of variation in the manufacturing process on the design; and multi-physical effects require the consideration of the impact of multiple physical effects such as heat and electromagnetics on the design. Summary of the invention

[0007] The present invention provides a novel database-based design rule checking and verification method. With the help of a shared database, the physical verification software can access more comprehensive design data, and thus can complete the verification process more quickly and efficiently in the face of problems with high rule complexity, process variation, and multiple physical effects. The present invention can avoid the overly conservative spacing requirements in general design rule checking and verification methods, reduce false alarms, and thus improve area utilization, detection accuracy, and reduce the cycle time of the actual process.

[0008] The present invention also provides a process for interacting with a shared database and an electrical simulation tool, as well as converting simulation data, including accessing electrical performance data and physical layout data, so that the DRC verification process can obtain more comprehensive analysis data.

[0009] The technical solution of the present invention is specifically as follows.

[0010] A design rule checking and verification method based on a shared database comprises the following steps:

[0011] 1) Input the layout file into the shared database;

[0012] 2) Obtain the design rule file;

[0013] 3) Preprocessing the shared database, including simulation extraction of physical information and electrical information of the layout;

[0014] 4) Obtain physical and electrical information of the layout from a shared database;

[0015] 5) Perform design rule checking with the help of electrical design automation (EDA) tools for physical verification;

[0016] Based on physical information inspection:

[0017] Minimum / maximum width and spacing rules for integrated circuits to ensure that the wire width and spacing in the layout meet process requirements to avoid breakage or short circuits during manufacturing;

[0018] Inter-layer alignment and coverage rules, check the alignment between different layers to ensure that the structures between layers are correctly covered;

[0019] The integrity of shapes and patterns ensures that the graphic shapes in the layout meet the design requirements without omissions or errors.

[0020] Based on the electrical information check:

[0021] Connectivity, ensuring there are no breaks or shorts in the layout and that the circuits are connected correctly;

[0022] Device matching and symmetry, checking whether the devices in the layout are arranged symmetrically to meet specific electrical performance requirements;

[0023] Clearance check to ensure electrical connections are correct and no electrical regulations are violated;

[0024] Heat-affected zone and current density limitations, assessing areas of the layout where performance may be affected by excessive heat or current density;

[0025] 6) Output the test report and store the results in the design rule check DRC result database;

[0026] 7) Fix the errors and repeat this process until all errors are fixed.

[0027] In the present invention, the main carrier of the physical information of the layout is the layer, including the original layer representing the original layout data, the derived polygon layer, the derived edge layer and the derived error layer.

[0028] In the present invention, in step 3), the preprocessing of the shared database includes:

[0029] ①Interaction between shared database and electrical simulation tools;

[0030] The layout file in the GDSII format in the shared database is transferred to the electrical simulation tool, and the simulation report of the electrical simulation tool is transferred to the shared database;

[0031] ② Analyze and obtain electrical simulation data with the help of electrical simulation tools;

[0032] The electrical simulation data includes voltage simulation results of shapes, the maximum value of voltage difference between shapes with voltage correlation at the same time, and the minimum spacing between two shapes is determined through voltage data;

[0033] ③Compress and convert the result data;

[0034] The result data of electrical simulation is the report file of the simulation tool. In order to obtain the voltage simulation results, the report file is converted into a virtual layer structure and stored in the GDSII layout file format;

[0035] ④Store the final results in a shared database.

[0036] In the present invention, in step 5), the method for checking whether the physical size, shape and layout of the integrated circuit meet the design requirements includes:

[0037] ① Extracting the original layer representing the original layout data from the layout;

[0038] ②Perform layer operations on the original layer; layer operations are specified by the rule file and are the basic unit of the rule file. Their function is to create a new derived layer from the original layer or other derived layers;

[0039] ③ Generate intermediate layers, including derived polygon layers and derived edge layers, and continue to execute step ② until all layer operations are completed, that is, traverse all layer operations defined in the rule file, and perform layer operations on the original layer and derived layer according to the rule file;

[0040] ④ Generate a derived error layer based on the mismatches found during the detection process;

[0041] ⑤ Take the polygon layer, derived edge layer and derived error layer as results to output to the DRC result database.

[0042] In the present invention, in step 5), the method for checking the spacing includes:

[0043] ① Extract electrical simulation information from the layout;

[0044] ② Analyze the cross-correlation between networks and accurately determine the voltage differences between them;

[0045] ③ Obtain more accurate voltage behavior with the help of dynamic information of voltage difference;

[0046] ④The DRC tool performs spacing checks based on the actual voltage difference.

[0047] In the present invention, the required spacing between two shapes depends on the relative voltage difference between the shapes. The voltage difference of the DRC is statically calculated as the difference between the maximum and minimum voltages of the two shapes: If there is a correlation between the voltages of the two shapes, and the maximum and minimum voltages do not occur at the same time, then the statically calculated voltage difference will result in a required spacing that is too large. If the maximum voltage difference between the two shapes is calculated at the same time: A looser spacing requirement can be obtained, thereby improving integration and reducing costs. In step 5) of the present invention, the required spacing between the two shapes depends on the relative voltage difference between the shapes, which is obtained by calculating the maximum voltage difference between the voltages V1 and V2 when the two shapes are the same, and the formula is as follows: ΔV = max{|V1-V2|}.

[0048] The present invention also includes the construction, initialization, updating and maintenance of a shared database.

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] The present invention introduces electrical simulation information into design rule detection by designing a shared database, aiming to eliminate overly conservative spacing requirements that may be caused by static rule detection, thereby avoiding waste of some chip areas and other unnecessary requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a general flow chart of design rule checking.

[0052] Figure 2 It is a flowchart of a design rule checking and verification process based on a shared database provided in an embodiment of the present application.

[0053] Figure 3 yes Figure 2 File flow diagram of the design rule checking verification process.

[0054] Figure 4 It is a flow chart of the interaction between a shared database and related tools provided in an embodiment of the present application.

[0055] Figure 5 It is a schematic diagram of the electrical performance data transmission process provided in an embodiment of the present application.

[0056] Figure 6 It is a schematic diagram of the physical layout data transmission process provided in an embodiment of the present application.

[0057] Figure 7 yes Figure 6 Figure 1 shows the relationship between physical layout and data transfer. DETAILED DESCRIPTION

[0058] In order to further understand the content, features and effects of the present invention, the following embodiments are cited and described in detail with reference to the accompanying drawings.

[0059] Design rule checking is a key technology in the integrated circuit design process. It is used to automatically verify whether the design meets the specific manufacturing process requirements. The main purpose is to ensure that the design meets the design rules of the manufacturing process. These rules define the minimum size, spacing, alignment and other restrictions in the layout to ensure that the circuit can be manufactured correctly and the performance meets expectations. DRC is an important step to avoid manufacturing errors and reduce costs.

[0060] Design rules are usually provided by the foundry, and they are based on the capabilities of their manufacturing processes, including limitations of lithography, etching, ion implantation and other steps. These rules become more stringent as technology nodes advance. DRC checks include but are not limited to the following: minimum / maximum width and spacing rules; layer alignment and coverage rules; shape and pattern integrity; connectivity, ensuring there are no breaks or shorts; device matching and symmetry; heat-affected area and current density limitations.

[0061] See also Figure 1 , the general DRC process includes the following steps:

[0062] Step S11, designing and reading a layout file, wherein the layout mainly includes information such as the physical size, shape and layout of the integrated circuit;

[0063] Step S12, obtaining a design rule file, which is usually provided by the wafer fab and is used to set the rules that need to be tested. The design rule file mainly includes two formats, the standard verification rule format (SVRF) or the Tcl verification format (TVF);

[0064] Step S13, using a physical verification EDA tool to check whether the physical size, shape and layout of the integrated circuit meet the design requirements;

[0065] Step S14, output the test report and store the error result in the DRC result database;

[0066] Step S15, correct the violation in the design according to the DRC result, and return to step 3 to perform DRC check again until all rules are met.

[0067] In the example of the present invention, electrical simulation information is introduced into the design rule detection by designing a shared database, with the aim of eliminating overly conservative spacing requirements that may be caused by static rule detection, thereby avoiding waste of some chip areas and other unnecessary requirements.

[0068] In general DRC, spacing rules are calculated based on static voltage differences, which usually assume the worst-case voltage difference, resulting in overly conservative spacing requirements. This may limit designers from taking advantage of the shrinking benefits brought by new process nodes. Some networks may have functional correlations, that is, their signals may be related in some cases. By analyzing the cross-correlations between these networks, the voltage differences between them can be more accurately determined. The present invention introduces electrical simulation information, which can provide actual dynamic information on the voltage differences between networks, more accurately reflecting the voltage behavior under different operating conditions. In this way, the DRC tool performs spacing checks based on the actual voltage behavior, rather than the worst-case static calculation.

[0069] Therefore, please refer to Figure 2 , the DRC process steps after the introduction of the shared database are:

[0070] Step S21: input the layout file into the shared database;

[0071] Step S22: obtaining a design rule file;

[0072] Step S23: preprocessing the shared database, mainly simulating and extracting physical and electrical information;

[0073] Step S24: Obtain physical and electrical information from the shared database;

[0074] Step S25: Using physical verification EDA tools, check whether the physical size, shape and layout of the integrated circuit meet the design requirements, and use electrical information to avoid false alarms and improve area utilization and detection accuracy;

[0075] Step S26: Output the test report and store the error result in the DRC result database;

[0076] Step S27: Correct the errors and return to step S23 until all errors are corrected.

[0077] See also Figure 3 ,for Figure 2 The file flow diagram of the flowchart shown describes the file interaction process of design rule files, layout files, test reports, shared databases, and result databases.

[0078] After receiving the layout file, the shared database needs to be preprocessed to obtain the electrical simulation information, which involves data extraction, conversion and compression. The result data of the electrical simulation is the report file of the simulation tool. It is necessary to obtain the voltage simulation results and convert them into a virtual layer structure and store them in the GDSII layout file format. Because the EDA tool that performs physical verification performs geometric checks from the GDSII flow when executing DRC, it is necessary to convert the voltage data set into a virtual layer structure so that it can be specially recognized by the EDA software without participating in the final mask.

[0079] See also Figure 4 , the steps of interacting with a shared database and related tools provided in an embodiment of the present application are:

[0080] Step S41, inputting the layout file into the shared database;

[0081] Step S42, the shared database interacts with the electrical simulation tool;

[0082] Step S43, analyzing the electrical simulation data with the aid of an electrical simulation tool;

[0083] Step S44, compressing and formatting the result data;

[0084] Step S45, storing the final result in a shared database.

[0085] See also Figure 5 , the electrical performance data transmission steps provided in the embodiment of the present application are:

[0086] Step S51, extracting electrical simulation information from the layout;

[0087] Step S52, analyzing the cross-correlation between the networks to accurately determine the voltage difference between them;

[0088] Step S53, obtaining more accurate voltage behavior by using dynamic information of voltage difference;

[0089] In step S54 , the DRC tool performs spacing check according to the actual voltage difference.

[0090] The main carrier of the physical information of the layout involved in DRC is the layer, including the original layer, derived polygon layer, derived edge layer and derived error layer.

[0091] See also Figure 6 The steps for transferring physical layout data provided by this application example are:

[0092] Step S61, extracting the original layer from the layout;

[0093] Step S62, performing layer operations on the original layer;

[0094] Step S63, generating intermediate layers, including derived polygon layers and derived edge layers. Continue to execute step S62 until all layer operations are completed;

[0095] Step S64, generating a derived error layer according to the mismatch found during the detection process;

[0096] Step S65, outputting the polygon layer, the derived edge layer and the derived error layer as results into a result database.

[0097] See also Figure 7 ,yes Figure 6 A relational block diagram of the physical layout data transfer.

[0098] We compared the general DRC process and the DRC process with the introduction of a shared database, and designed four sets of comparison examples, involving four networks of different sizes, with the network size increasing from 1000 to 3000. For each network size, ΔV = max{(V 1,max -V 2,min ),(V 2,max -V 1,min )}, ΔV=max{|V1-V2|}. Comparing the simulation-based and static-calculation-based cases, the voltage difference of the former is smaller, and the minimum spacing requirement is more relaxed. In large-scale networks, 90% of the shape spacing violations generated by static calculations can be optimized, and the optimization rate is positively correlated with the size of the network. Considering the entire iterative process of DRC, including error detection, correction, and re-detection, the introduction of the database will reduce unnecessary errors and can greatly reduce the time of the entire design cycle.

[0099] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0100] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A design rule checking and verification method based on a shared database, It is characterized in that The following steps are involved: 1) Input the layout file into the shared database; 2) Obtain the design rule file; 3) Preprocessing the shared database, including simulation extraction of physical information and electrical information of the layout; 4) Obtain physical and electrical information of the layout from a shared database; 5) Perform design rule checking with the help of electrical design automation (EDA) tools for physical verification; Based on physical information inspection: Minimum / maximum width and spacing rules for integrated circuits to ensure that the wire width and spacing in the layout meet process requirements to avoid breakage or short circuits during manufacturing; Inter-layer alignment and coverage rules, check the alignment between different layers to ensure that the structures between layers are correctly covered; The integrity of shapes and patterns ensures that the graphic shapes in the layout meet the design requirements without omissions or errors. Based on the electrical information check: Connectivity, ensuring there are no breaks or shorts in the layout and that the circuits are connected correctly; Device matching and symmetry, checking whether the devices in the layout are arranged symmetrically to meet specific electrical performance requirements; Clearance check to ensure electrical connections are correct and no electrical regulations are violated; Heat-affected zone and current density limitations, assessing areas of the layout where performance may be affected by excessive heat or current density; 6) Output the test report and store the results in the design rule check DRC result database; 7) Fix the errors and repeat this process until all errors are fixed.

2. The rule checking and verification method according to claim 1, It is characterized in that The main carrier of the physical information of the layout is the layer, including the original layer representing the original layout data, the derived polygon layer, the derived edge layer and the derived error layer.

3. The design rule checking and verification method according to claim 1, It is characterized in that In step 3), the preprocessing of the shared database includes: ①Interaction between shared database and electrical simulation tools; The layout file in the GDSII format in the shared database is transferred to the electrical simulation tool, and the simulation report of the electrical simulation tool is transferred to the shared database; ② Analyze and obtain electrical simulation data with the help of electrical simulation tools; The electrical simulation data includes voltage simulation results of shapes, the maximum value of voltage difference between shapes with voltage correlation at the same time, and the minimum spacing between two shapes is determined through voltage data; ③Compress and convert the result data; The result data of electrical simulation is the report file of the simulation tool. In order to obtain the voltage simulation results, the report file is converted into a virtual layer structure and stored in the GDSII layout file format. ④Store the final results in a shared database.

4. The design rule checking and verification method according to claim 1, It is characterized in that In step 5), the method for checking whether the physical size, shape and layout of the integrated circuit meet the design requirements includes: ① Extracting the original layer representing the original layout data from the layout; ②Perform layer operations on the original layer; layer operations are specified by the rule file and are the basic unit of the rule file. Their function is to create a new derived layer from the original layer or other derived layers; ③ Generate intermediate layers, including derived polygon layers and derived edge layers, and continue to execute step ② until all layer operations are completed, that is, traverse all layer operations defined in the rule file, and perform layer operations on the original layer and derived layer according to the rule file; ④ Generate a derived error layer based on the mismatches found during the detection process; ⑤ Take the polygon layer, derived edge layer and derived error layer as results to output to the DRC result database.

5. The design rule checking and verification method according to claim 1, It is characterized in that In step 5), the spacing inspection method includes: ① Extract electrical simulation information from the layout; ② Analyze the cross-correlation between networks and accurately determine the voltage differences between them; ③ Obtain more accurate voltage behavior with the help of dynamic information of voltage difference; ④The DRC tool performs spacing checks based on the actual voltage difference.

6. The design rule checking and verification method according to claim 5, It is characterized in that In step 5), the required spacing between the two shapes depends on the relative voltage difference between the shapes, which is calculated by calculating the voltage V when the two shapes are the same. 1 、V 2 The maximum value of the voltage difference is obtained by the following formula: ΔV = max{|V 1 -V 2 |}.

7. The design rule checking and verification method according to claim 1, It is characterized in that It also includes the construction, initialization, updating and maintenance of shared databases.

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