Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer; the circuit layer is arranged on the insulating layer; and a protective layer disposed on the insulating layer, in which the circuit layer includes a 1-1 pad and a 1-2 pad spaced apart from each other in a first horizontal direction, the protective layer including: a first protective pattern disposed on the first horizontal direction, and a second protective pattern disposed on the second horizontal direction; a first protection pattern provided so as to surround at least a portion of a side surface of the (1-1)-th pad and the (1-2)-th pad, and provided between the (1-1)-th pad and the (1-2)-th pad; and a second protection pattern disposed to surround the first protection pattern, a top surface of the first protection pattern being positioned lower than top surfaces of the 1-1 pad and the 1-2 pad, the top surface of the second protection pattern is positioned higher than the top surfaces of the 1-1 pad and the 1-2 pad. And each of the (1-1) th pad and the (1-2) th pad has a different width in the first horizontal direction and a different width in a second horizontal direction perpendicular to the first horizontal direction.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the circuit board. Background Art

[0002] Generally, a printed circuit board (PCB) is a laminated structure in which insulating layers and conductor layers are alternately laminated, and the conductor layers may be formed into a circuit pattern by patterning.

[0003] The printed circuit board is provided with a solder resist (SR) which protects the circuit pattern formed on the outermost side of the laminate structure, prevents oxidation of the conductor layer, and also serves as an insulator when electrically connected to a chip or other substrate mounted on the printed circuit board.

[0004] A typical solder resist has an opening area (SRO: solder resist opening) which is an electrical connection path formed by combining a connection device such as solder or a bump, and, due to the high performance and high density of printed circuit boards, as the I / O (input / output) performance increases, the number of solder resist opening areas needs to increase, and therefore, a small bump pitch of the opening area is required. At this time, the bump pitch of the solder resist opening area refers to the distance between the centers of adjacent opening areas.

[0005] Meanwhile, the solder resist opening area (SRO) includes an SMD (Solder Mask Defined Type) type and an NSMD (Non Solder Mask Defined Type) type.

[0006] The SMD type is characterized in that the width of an open region (SRO) is smaller than the width of a pad exposed through the open region (SRO), and thus at least a portion of an upper surface of the pad in the SMD type is covered with a solder resist.

[0007] In addition, the NSMD type is characterized in that the width of the opening area (SRO) is greater than the width of the pad exposed through the opening area (SRO), and therefore, the solder resist in the NSMD type is arranged at a certain distance from the pad and thus has a structure in which both the upper surface and the side surface of the pad are exposed.

[0008] However, in the case of the SMD type, after combining the semiconductor package with the main board, there is a problem that the solder ball is separated from the pad exposed through the opening area (SRO) during the solder ball bonding reliability test for the bonding strength of the solder ball. In addition, in the case of the NSMD type, there is a problem that the pad on which the solder ball is arranged is separated from the circuit board. Therefore, conventionally, the SMD type and the NSMD type are appropriately combined and applied to one circuit board.

[0009] At this time, the conventional circuit board provides a space for mounting components such as a multilayer ceramic capacitor (MLCC). At this time, the solder resist in the space where the multilayer ceramic capacitor is arranged in the conventional circuit board has an SMD type. Therefore, a semiconductor package in which the multilayer ceramic capacitor is mounted on the conventional circuit board has a problem that the total thickness of the semiconductor package increases by as much as the thickness of the solder resist.

[0010] To solve this problem, solder resist is not arranged in the space where the multilayer ceramic capacitor is arranged in the conventional circuit board. In addition, the bonding member such as the solder ball has a structure extending along the side surface of the pad. Therefore, the structure without solder resist has a short circuit problem: the bonding members arranged on each adjacent pad are interconnected.

[0011] (Patent Document 1) KR 10-2013-0046726 A

[0012] (Patent Document 2) KR 10-1877963 B Summary of the invention

[0013] [Technical issues]

[0014] The embodiment provides a circuit board that can be thinned and a semiconductor package including the same.

[0015] Furthermore, the embodiment provides a circuit board capable of reducing a spacing between adjacent pads and a semiconductor package including the same.

[0016] Furthermore, the embodiment provides a circuit board capable of solving a short circuit problem between adhesive members arranged on a pad and a semiconductor package including the same.

[0017] Furthermore, the embodiment provides a circuit board having improved physical and electrical reliability and a semiconductor package including the same.

[0018] Furthermore, the embodiment provides a circuit board capable of solving the problem of communication of an adhesive member between an insulating layer and a pad, and a semiconductor package including the same.

[0019] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, but other technical problems not mentioned can be clearly understood by those skilled in the art to which the proposed embodiments belong from the following description.

[0020] [Technical solution]

[0021] A circuit board according to an embodiment includes: an insulating layer; a circuit layer arranged on the insulating layer; and a protective layer arranged on the insulating layer, wherein the circuit layer includes a 1-1 pad and a 1-2 pad spaced apart from each other in a first horizontal direction, wherein the protective layer includes: a first protection pattern arranged between the 1-1 pad and the 1-2 pad and surrounding at least a portion of a side surface of the 1-1 pad and a side surface of the 1-2 pad; and a second protection pattern arranged to surround the first protection pattern, an upper surface of the first protection pattern being positioned lower than an upper surface of the 1-1 pad and an upper surface of the 1-2 pad, an upper surface of the second protection pattern being positioned higher than an upper surface of the 1-1 pad and an upper surface of the 1-2 pad, and each of the 1-1 pad and the 1-2 pad has different widths in the first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction.

[0022] In addition, the thickness of the first protection pattern satisfies the range of 40% to 90% of the thickness of at least one of the 1-1 pad and the 1-2 pad.

[0023] In addition, a thickness of at least one of the 1-1 pad and the 1-2 pad satisfies a range of 10 μm to 25 μm, and a thickness of the first protection pattern satisfies a range of 3 μm to 21 μm.

[0024] In addition, a vertical distance between an upper surface of at least one of the 1-1 pad and the 1-2 pad and an upper surface of the first protection pattern satisfies a range of 3 μm to 10 μm.

[0025] Furthermore, at least one of the upper surfaces of the 1-1st pad and the 1-2nd pad includes a curved surface, and the vertical distance is a vertical distance from the uppermost surface of the at least one of the 1-1st pad and the 1-2nd pad to the uppermost surface of the first protection pattern.

[0026] In addition, the thickness of the second protective pattern satisfies the range of 17 μm to 45 μm.

[0027] Furthermore, the width of each of the 1-1 pad and the 1-2 pad in the second horizontal direction is within a range of 125% to 220% of the width of each of the 1-1 pad and the 1-2 pad in the first horizontal direction.

[0028] In addition, the interval between the 1-1 pad and the 1-2 pad satisfies the range of 70% to 120% of the width of each of the 1-1 pad and the 1-2 pad in the first horizontal direction.

[0029] In addition, an inner wall of the second protection pattern is spaced apart from a side surface of at least one of the 1-1th pad and the 1-2th pad by a spacing of 15 μm to 23 μm.

[0030] Furthermore, the first protection pattern is disposed to partially surround the side surface of the 1-1th pad and the side surface of the 1-2th pad, and at least a portion of the second protection pattern contacts the side surface of the 1-1th pad or the side surface of the 1-2th pad.

[0031] In addition, the 1-1 pad includes a 1-1 side surface facing the 1-2 pad and a 1-2 side surface other than the 1-1 side surface, and the 1-2 pad includes a 2-1 side surface facing the 1-1 side surface and a 2-2 side surface other than the 2-1 side surface, and the second protection pattern is in direct contact with at least a portion of the 1-2 side surface of the 1-1 pad and the 2-2 side surface of the 1-2 pad.

[0032] In addition, the circuit layer further includes a second pad having a width in the range of 3 μm to 30 μm and a second trace having a width in the range of 1 μm to 10 μm, and a spacing between the second pad and the second trace having a range of 1 μm to 10 μm.

[0033] In addition, the second pads are provided in plurality, the second traces are provided in plurality, and the protection layer has through holes vertically overlapping the plurality of second pads, the plurality of second traces, and areas between the plurality of second pads and the plurality of second traces.

[0034] In addition, the second pads are arranged in plurality, the second traces are arranged in plurality, the protection layer further comprises a third protection pattern arranged between the plurality of second pads and the plurality of second traces, and the third protection pattern does not overlap with the second pads and the second traces in a vertical direction.

[0035] In addition, an upper surface of the third protection pattern is positioned lower than an upper surface of each of the second pad and the second trace.

[0036] In addition, the circuit layer further includes a plurality of third pads and a plurality of third traces, the width of the third pads meets the range of 30 μm-70 μm, and the spacing between the third pads and the third traces meets the range of 10 μm-40 μm.

[0037] In addition, the protection layer further includes a fourth protection pattern having a width smaller than that of the third pad and overlapping the third pad in a vertical direction.

[0038] [Beneficial Effects]

[0039] A circuit board of an embodiment includes a first region in which a first semiconductor device is arranged.

[0040] In addition, the circuit board includes a 1-1 pad and a 1-2 pad. The 1-1 pad and the 1-2 pad are arranged to overlap with the first semiconductor device in the vertical direction. For example, the 1-1 pad and the 1-2 pad are arranged in the first area of ​​the circuit board. In addition, the embodiment includes a protective layer. The protective layer includes a first protection pattern, which is arranged between the 1-1 pad and the 1-2 pad and surrounds at least a portion of the side surface of the 1-1 pad and the side surface of the 1-2 pad. In addition, the protective layer includes a second protection pattern arranged around the first protection pattern.

[0041] The first protection pattern contacts at least a portion of the side surfaces of the 1-1st pad and the 1-2nd pad, but does not contact the upper surface of the 1-1st pad and the upper surface of the 1-2nd pad. For example, the upper surface of the first protection pattern is positioned lower than the upper surface of the 1-1st pad and the upper surface of the 1-2nd pad. Therefore, the embodiment can reduce the thickness and width of the contact member to be arranged on the 1-1st pad and the 1-2nd pad by using the first protection pattern.

[0042] For example, the first comparative example has a problem in which the thickness of the contact member increases due to the arrangement of the protective layer, and the second comparative example has a problem in which the expansion degree of the contact member increases due to the non-arrangement of the protective layer, thereby increasing the width of the contact member.

[0043] In contrast, the present embodiment can reduce the expansion degree of the contact member and reduce the width of the contact member by using a combination of the first protection pattern and the second protection pattern. In addition, the present embodiment provides only the first protection pattern in the region vertically overlapping with the first semiconductor device. For example, the second protection pattern does not overlap with the first semiconductor device vertically. Therefore, the present embodiment can prevent the thickness of the contact member from increasing due to the height of the protection layer.

[0044] Therefore, the present embodiment can reduce the thickness of the semiconductor package, thereby achieving miniaturization. In addition, the present embodiment can solve the problem of short circuit between adjacent contact members by reducing the expansion degree of the contact member. As a result, the present embodiment can improve the electrical reliability and product reliability of the semiconductor package. In addition, the present embodiment can solve the problem of circuit short circuit without increasing the spacing between the 1-1 pad and the 1-2 pad, thereby improving the circuit integration.

[0045] In addition, the present embodiment can solve the problem of the adhesive member being connected between the insulating layer and the pad by using the first protection pattern, thereby further improving product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a cross-sectional view of a semiconductor package according to a first comparative example.

[0047] Figure 2 is a cross-sectional view of a semiconductor package according to a second comparative example.

[0048] Figure 3 is a cross-sectional view showing the entire layer structure of a circuit board according to one embodiment.

[0049] Figure 4 is a view showing the structure of the second area of ​​the circuit board according to the first embodiment.

[0050] Figure 5 is a view showing the structure of the second area of ​​the circuit board according to the second embodiment.

[0051] Figure 6 is a view showing a structure of a third region of a circuit board according to an embodiment.

[0052] Figure 7a is a plan view of a first region of a circuit board according to the first embodiment.

[0053] Figure 7b is along Figure 7a A cross-sectional view taken along the C-C' direction.

[0054] Figure 7c is along Figure 7a A cross-sectional view taken along the D-D' direction.

[0055] Figure 8 is a perspective view showing a semiconductor device mounted on a first area of ​​a circuit board according to an embodiment.

[0056] Fig. 9 is a plan view of a first region of a circuit board according to a second embodiment.

[0057] Fig.10a is a plan view of a first region of a circuit board according to a third embodiment.

[0058] Fig.10b is along Fig.10a A cross-sectional view taken along the E-E' direction.

[0059] Fig.10c is along Fig.10a A cross-sectional view taken along the FF′ direction.

[0060] Fig.10d yes Fig.10c A variation of the structure of .

[0061] Fig.11a is a plan view of a first region of a circuit board according to a fourth embodiment.

[0062] Fig.11b is along Fig.10a A cross-sectional view taken along the G-G' direction.

[0063] Fig.12 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0064] Fig.13a According to the first embodiment Fig.12 An enlarged view of a first semiconductor device arrangement area.

[0065] Fig.13b According to the second embodiment Fig.12 An enlarged view of a first semiconductor device arrangement area.

[0066] Figures 14 to 21 2 is a cross-sectional view showing a process of manufacturing a circuit board according to an embodiment in order of processes. DETAILED DESCRIPTION

[0067] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein the same reference numerals are used to represent the same or similar elements, and their repeated description will be omitted. The suffixes "module" and "section" of the components used in the following description are given or mixed only in consideration of the ease of preparing the description, and they do not distinguish meanings or functions from each other. Moreover, in the following description of the embodiments of the present invention, when it is determined that the key points of the embodiments disclosed herein may be confusing, the detailed description of the related art will be omitted. Moreover, the accompanying drawings are included to provide a further understanding of the present invention, and the accompanying drawings are incorporated herein and constitute a part of this specification, and it should be understood that the present invention is intended to cover all modifications, equivalents or alternatives that fall within the spirit and scope of the present invention.

[0068] Terms including orders such as "first", "second", etc. may be used to describe various components, but the elements are not limited to these terms. These terms are only used to distinguish one component from another.

[0069] When a component is referred to as being "connected to" or "contacting" another component, it may be directly connected or joined to the other component, but it should be understood that other components may exist between the two. When a component is referred to as being "directly connected to" or "directly contacting" another component, it should be understood that other components may not exist between the two.

[0070] Unless the context clearly implies otherwise, a singular expression includes a plural expression.

[0071] In this application, terms such as "include" or "have" are used to indicate the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification. However, it should be understood that these terms do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0072] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0073] -Comparative Example-

[0074] Before describing the present embodiment, a comparative example to be compared with the circuit board of the embodiment of the present invention will be described.

[0075] Figure 1 is a cross-sectional view of a semiconductor package according to a first comparative example, and Figure 2 is a cross-sectional view of a semiconductor package according to a second comparative example.

[0076] Reference Figure 1 , a semiconductor package according to a first comparative example includes a circuit board and a device mounted on the circuit board.

[0077] The circuit board of the first comparative example includes an insulating layer 10 , a circuit layer 20 , and a protective layer 30 .

[0078] The circuit layer 20 is disposed on the upper surface of the insulating layer 10. The circuit layer 20 may represent the outermost layer among a plurality of circuit layers disposed on the circuit board. For example, the circuit layer 20 represents a circuit layer of a region on the circuit board where a chip is mounted.

[0079] For example, the circuit layer 20 represents a pad on which a multilayer ceramic capacitor is arranged.

[0080] The protection layer 30 is disposed on the insulating layer 10 .

[0081] At this time, the protective layer 30 is disposed on the insulating layer 10 with a certain thickness. Specifically, the protective layer 30 is disposed on the insulating layer 10 with a thickness greater than that of the circuit layer 20.

[0082] The protective layer 30 includes an opening (not shown) overlapping with the upper surface of the circuit layer 20 in the thickness direction. The plane area of ​​the opening of the protective layer 30 is smaller than the plane area of ​​the circuit layer 20. That is, the protective layer 30 is arranged to cover a portion of the upper surface of the circuit layer 20. In addition, the protective layer 30 overlaps with at least a portion of the upper surface of the circuit layer 20 in the thickness direction, so as not to contact with at least a portion of the upper surface of the circuit layer 20.

[0083] The adhesive member 50 is disposed in the opening of the protective layer 30. The adhesive member 50 may be a solder ball.

[0084] In addition, the device 40 can be mounted on the circuit layer 20 through the adhesive member 50. The device 40 has a structure of a body 41 and terminals 42 formed on both sides of the body 41. That is, the device 40 is a passive device. For example, the device 40 is a multilayer ceramic capacitor.

[0085] At this time, in the first comparative example, the protective layer 30 in the region where the device 40 is mounted is arranged higher than the upper surface of the circuit layer 20. Therefore, in the first comparative example, there is a problem that the total thickness of the semiconductor package increases by the protruding thickness of the protective layer 30.

[0086] That is, the circuit layer 20 includes a pad electrically connected to the device 40. The pad has a size corresponding to the terminal 42 of the device 40. For example, the width w1 of the pad in the first horizontal direction exceeds 140 μm. For example, the width w1 of the pad in the first horizontal direction exceeds 190 μm. For example, the width w1 of the pad in the first horizontal direction exceeds 300 μm. For example, the width w1 of the pad in the first horizontal direction exceeds 450 μm. The first horizontal direction refers to the separation direction of the plurality of terminals 42 of the device 40.

[0087] Furthermore, in the circuit board of the first comparative example, the pitch w2 between the plurality of pads connected to the device 40 exceeds 120 μm. For example, in the circuit board of the first comparative example, the pitch w2 between the plurality of pads connected to the device 40 exceeds 200 μm. For example, in the circuit board of the first comparative example, the pitch w2 between the plurality of pads connected to the device 40 exceeds 300 μm.

[0088] Meanwhile, the maximum width w3 of the adhesive member 50 in the first horizontal direction has a level similar to the width w1 of the pad. For example, the maximum width w3 of the adhesive member 50 in the first horizontal direction has a level of 80% to 105% of the width of the pad.

[0089] Meanwhile, the thickness t1 of the circuit layer 20 of the first comparative example ranges from 10 μm to 20 μm. In addition, the thickness t2 of the portion protruding on the upper surface of the circuit layer 20 in the total thickness of the protective layer 30 ranges from 7 μm to 20 μm.

[0090] At this time, the adhesive member 50 is disposed to have a certain thickness t3 from the upper surface of the protective layer 30. The thickness t3 is set based on a condition that allows the device 40 to be stably mounted on the circuit layer 20.

[0091] At this time, the thickness t3 of the first comparative example is set based on the upper surface of the protective layer 30 instead of the upper surface of the circuit layer 20. That is, when the thickness t3 is set based on the upper surface of the circuit layer 20, the following problem may occur: during the process of mounting the device 40, a portion of the device 40 contacts the upper surface of the protective layer 30. As a result, the device 40 may be mounted in a skewed state.

[0092] Therefore, the thickness t4 from the upper surface of the insulating layer 10 to the upper surface of the device 40 in the first comparative example reflects not only the thickness t1 of the circuit layer 20 and the thickness t3 of the adhesive member 50, but also the thickness t2 of the protruding portion of the protective layer 30. Therefore, in the first comparative example, there is a problem that the total thickness of the structure in which the device 40 is mounted increases by the thickness t2 of the protruding portion of the protective layer 30.

[0093] At the same time, Figure 2 In the second comparative example, in order to solve the problem of the first comparative example, the protective layer 30 is not arranged in the region where the device 40 is mounted.

[0094] At this time, the protective layer 30 may not be arranged in the area where the circuit layer 20 is arranged, and therefore, the structure has no insulating member between the plurality of pads of the circuit layer 20. Therefore, the second comparative example has a problem of dendrites occurring between the plurality of pads. For example, a circuit board on which a semiconductor device is mounted may have the following electrical problem: a voltage corresponding to the driving power of the semiconductor device is applied, and due to the applied voltage, the metal forming the plurality of pads may grow into a dendrite shape, thereby causing two adjacent pads to short-circuit with each other, which means a short circuit caused by the occurrence of migration. For example, when a certain level of voltage is applied to the circuit layer, metal ions may grow into a dendrite shape from the positive electrode pattern toward the negative electrode pattern, and therefore, there may be a problem of the plurality of pads being electrically short-circuited with each other.

[0095] In addition, the second comparative example can reduce the thickness of the semiconductor package by the thickness t2 of the protruding portion of the protective layer 30 of the first comparative example. The thickness t4' between the insulating layer 10 and the device 40 in the second comparative example can be smaller than the thickness t4 of the first comparative example by the thickness t2 of the protruding portion of the protective layer 30.

[0096] Furthermore, since the second comparative example has a structure in which the protective layer 30 does not exist, there is a problem in that the width of the adhesive member 50 becomes relatively large.

[0097] Specifically, the adhesive member 50 is disposed on the circuit layer 20. At this time, the adhesive member 50 is disposed on the circuit layer 20 and has a structure in which it is disposed along the surface of the metal circuit layer 20.

[0098] At this time, in the first comparative example, since the adhesive member 50 does not contact the side surface of the circuit layer 20 , the width w3 of the adhesive member 50 is similar to the width w1 of the pad of the circuit layer 20 .

[0099] In contrast, the second comparative example has a structure in which the side surface of the circuit layer 20 is completely exposed. Therefore, the adhesive member 50 of the second comparative example is arranged to cover not only the upper surface of the circuit layer 20 but also the entire side surface.

[0100] That is, the width w3' of the adhesive member 50 of the second comparative example is greater than the width of the pad of the circuit layer 20. Specifically, the width w3' of the adhesive member 50 of the second comparative example exceeds 130% of the width of the pad. More specifically, the width w3' of the adhesive member 50 of the second comparative example exceeds 140% of the width of the pad.

[0101] At this time, the device 40 includes two terminals 42. In addition, since the bonding member 50 of the second comparative example has a structure in which it extends along the side surface of the circuit layer 20, there is the following problem: the spacing between the two bonding members in contact with the two terminals is narrowed. In addition, as the thickness or width of the circuit layer 20 increases, the spacing between the two bonding members is narrowed. Therefore, the structure in the second comparative example where the protective layer 30 is not arranged has the following problem: the spacing between the two contact members is narrowed. In addition, the second comparative example has the following problem: depending on the expansion degree of the bonding member 50, a short circuit occurs between the two bonding members. In addition, the second comparative example makes the spacing w2 between the two pads greater than the spacing w2 of the first comparative example to solve the circuit short circuit problem. Therefore, the thickness of the semiconductor package of the second comparative example can be less than the thickness of the semiconductor package of the first comparative example. However, due to the problem of reduced circuit integration, the size of the semiconductor package has increased in the horizontal direction.

[0102] In addition, as the performance of electrical / electronic products has been improved in recent years, technologies for mounting a greater number of components on a substrate of a limited size have been studied, and therefore, miniaturization of the width and spacing of the circuit layer is required. However, in the case of the semiconductor packages of the first comparative example and the second comparative example, it is difficult to reduce the total thickness, or there is a limit to reducing the spacing between the circuit layers due to the circuit short circuit problem. In addition, in recent years, the functions processed by the application processor (AP) have been increasing, and therefore, it has become difficult to implement them in a single chip. However, in the comparative example, it is difficult to install two application processors (APs) with different functions or multiple passive devices in a limited space.

[0103] The present embodiment aims to solve the problems of these comparative examples by dividing the circuit board into a plurality of regions and making the protective layers in the plurality of regions have different opening structures. Therefore, the present embodiment can reduce the spacing between the pads on which the devices are mounted without increasing the total thickness of the semiconductor package. Thus, the present embodiment can improve the integration of the circuit board, so that multiple chips can be mounted on a single circuit board. For example, the present embodiment can provide a circuit board having a new structure and a semiconductor package including the circuit board, and this new structure can mount multiple processor chips or memory chips with different functions on a single circuit board.

[0104] -Electronic equipment-

[0105] Before describing the embodiment, an electronic device including a semiconductor package of an embodiment will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically connected and / or electrically connected to various components. For example, according to an embodiment, the mainboard can be connected to the semiconductor package. Various chips can be mounted on the semiconductor package. For broad interpretation, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM) and flash memory, application processor chips such as central processing units (e.g., CPUs), graphics processors (e.g., GPUs), antenna chips, digital signal processors, cryptographic processors, microprocessors and microcontrollers, and logic chips such as analog-to-digital converters and ASICs (application specific ICs) and passive devices can be mounted on a package substrate. In addition, the circuit board of the present embodiment can also be used as a package substrate on which a memory chip or a logic chip is mounted.

[0106] Specifically, the semiconductor package of the present embodiment may be equipped with at least one chip, and the chip may include at least one of a processor chip, a passive chip, and an active chip. Specifically, an electronic component such as a chip may be equipped in the semiconductor package. In addition, the chip may be an active chip or a passive chip. An active chip refers to a chip that actively utilizes a nonlinear part of a signal characteristic. In addition, a passive chip refers to a chip that does not utilize nonlinear signal characteristics despite the presence of linear signal characteristics and nonlinear signal characteristics. For example, an active chip may include a transistor, an IC semiconductor chip, etc., and a passive chip may include a capacitor, a resistor, an inductor, etc. A passive chip may increase the signal processing speed of a semiconductor chip that is an active chip, or performs a filtering function, etc. In addition, the chip may be a wireless communication chip that can be used for Wi-Fi or 5G communication.

[0107] At the same time, the product group applied to the semiconductor package of this embodiment can be any one of CSP (chip scale packaging), FC-CSP (flip chip - chip scale packaging), FC-BGA (flip chip ball grid array), POP (package on package), SIP (system in package), but it is not limited to this.

[0108] In this case, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game, a smart watch, a car, etc. However, the embodiment is not limited thereto but may be any other electronic device that processes data in addition to these.

[0109] -Example-

[0110] Figure 3 is a cross-sectional view showing the entire layer structure of a circuit board according to the embodiment.

[0111] Reference Figure 3 , the circuit board includes a plurality of insulating layers.

[0112] At this time, the circuit board may be a core board including a core layer. However, the present invention is not limited thereto, and the circuit board of the present invention may be a coreless board not including a core layer.

[0113] However, for convenience of explanation, the circuit board of the present invention will be described as a core board including a core layer.

[0114] In addition, although the circuit board of the embodiment in the drawings is shown as having a five-layer structure based on multiple insulating layers, the embodiment is not limited thereto. For example, the circuit board of the embodiment may have four or fewer layers based on multiple insulating layers, or alternatively, may have six or more layers.

[0115] Hereinafter, as one example of an embodiment, a circuit board having a five-layer insulating layer structure including a core layer will be described.

[0116] The insulating layer 110 of the present embodiment includes a first insulating layer 111. The first insulating layer 111 may be an insulating layer having copper foil laminated on both surfaces. Preferably, the first insulating layer 111 may be a copper clad laminate (CCL).

[0117] In particular, the copper clad laminate is a general base plate on which a circuit board is manufactured, and is a laminated structure in which copper foil is laminated on an insulating layer. Depending on the application, the copper clad laminate may include a glass / epoxy copper clad laminate, a heat-resistant resin copper clad laminate, a paper / phenol copper clad laminate, a high-frequency copper clad laminate, a flexible copper clad laminate (e.g., a polyimide film), and a composite copper clad laminate. At this time, the first insulating layer 111 of the present embodiment may use a glass / epoxy copper clad laminate to manufacture a double-sided circuit board and a multi-layer circuit board, but is not limited thereto.

[0118] The first insulating layer 111 may have a thickness in the range of 100 μm to 500 μm. Preferably, the first insulating layer 111 may have a thickness in the range of 120 μm to 480 μm. More preferably, the first insulating layer 111 may have a thickness in the range of 150 μm to 450 μm.

[0119] If the thickness of the first insulating layer 111 is less than 100 μm, the rigidity and warpage characteristics of the circuit board may be deteriorated. In addition, if the thickness of the first insulating layer 111 exceeds 500 μm, the thickness of the circuit layer arranged on or in the first insulating layer 110, the line width of the circuit layer, the spacing between the circuit layers, and the thickness of the through-electrode may increase.

[0120] The insulating layer 110 may include a plurality of insulating layers respectively laminated on the upper and lower portions of the first insulating layer 111. For example, the insulating layer 110 may include a second insulating layer 112 disposed on an upper surface of the first insulating layer 111, a third insulating layer 113 disposed on an upper surface of the second insulating layer 112, a fourth insulating layer 114 disposed on a lower surface of the first insulating layer 111, and a fifth insulating layer 115 disposed on a lower surface of the fourth insulating layer 114.

[0121] The second to fifth insulating layers 115 may include prepreg (PPG). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet (the fabric sheet is, for example, glass fiber woven with glass fiber yarn) with epoxy resin or the like, and then performing hot pressing. However, the present embodiment is not limited thereto, but the prepreg constituting the second to fifth insulating layers 115 may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

[0122] In addition, at least one of the second to fifth insulating layers 115 may be rigid or flexible. For example, at least one of the second to fifth insulating layers 115 may include RCC (resin coated copper), ABF (Ajinomoto build film), FR-4, BT (bismaleimide triazine), PID (photo imageable dielectric resin), BT, etc.

[0123] Each of the second to fifth insulating layers 115 may have a thickness in the range of 10 μm to 60 μm. Preferably, each of the second to fifth insulating layers 115 may have a thickness in the range of 12 μm to 50 μm. More preferably, each of the second to fifth insulating layers 115 may have a thickness in the range of 15 μm to 40 μm.

[0124] If the thickness of each of the second to fifth insulating layers 115 is less than 10 μm, the circuit layer included in the circuit board may not be stably protected. If the thickness of each of the second to fifth insulating layers 115 exceeds 60 μm, the thickness of the circuit board and the semiconductor package including the circuit board may increase. If the thickness of each of the second to fifth insulating layers 115 exceeds 60 μm, the thickness of the circuit layer and the thickness of the through electrode may increase accordingly. In addition, if the thickness of the circuit layer and the thickness of the through electrode increase, the signal transmission loss may increase.

[0125] The circuit board of this embodiment includes a circuit layer.

[0126] The circuit layer may be arranged on each surface of the insulating layer 110. For example, the circuit layer may include a first circuit layer 121 arranged on an upper surface of the first insulating layer 111, a second circuit layer 122 arranged on an upper surface of the second insulating layer 112, a third circuit layer 123 arranged on an upper surface of the third insulating layer 113, a fourth circuit layer 124 arranged on a lower surface of the first insulating layer 111, a fifth circuit layer 125 arranged on a lower surface of the fourth insulating layer 114, and a sixth circuit layer 126 arranged on a lower surface of the fifth insulating layer 115.

[0127] At least one of the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 may have a thickness of 10 μm to 25 μm. Preferably, at least one of the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 may have a thickness of 12 μm to 23 μm. More preferably, at least one of the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 may have a thickness of 15 μm to 20 μm.

[0128] The first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 may include a conductive material. For example, the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 may include at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 may be formed of copper (Cu) having high conductivity and being relatively inexpensive.

[0129] The first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125 and the sixth circuit layer 126 can be formed by conventional circuit board manufacturing processes, such as additive processes, subtractive processes, modified semi-additive processes (MSAP) and semi-additive processes (SAP), and their detailed descriptions are omitted here.

[0130] The circuit board includes a through electrode. For example, the circuit board includes a through electrode that penetrates the insulating layer and electrically connects circuit layers arranged on different layers.

[0131] For example, the through-electrode includes a first through-electrode 131 penetrating the first insulating layer 111. The first through-electrode 131 may be electrically connected between the first circuit layer 121 and the fourth circuit layer 124.

[0132] In addition, the through-electrode includes a second through-electrode 132 penetrating the second insulating layer 112. The second through-electrode 132 may be electrically connected between the first circuit layer 121 and the second circuit layer 122.

[0133] In addition, the through electrodes include a third through electrode 133 penetrating the third insulating layer 113. The third through electrode 133 may be electrically connected between the second circuit layer 122 and the third circuit layer 123.

[0134] In addition, the through electrodes include a fourth through electrode 134 penetrating the fourth insulating layer 114. The fourth through electrode 134 may be electrically connected between the fourth circuit layer 124 and the fifth circuit layer 125.

[0135] In addition, the through electrodes include a fifth through electrode 135 penetrating the fifth insulating layer 115. The fifth through electrode 135 may be electrically connected between the fifth circuit layer 125 and the sixth circuit layer 126.

[0136] In addition, the circuit board includes a protective layer. The protective layer can be arranged on the uppermost side or the lowermost side of the circuit board. The protective layer can protect the surface of the circuit layer or the insulating layer arranged on the uppermost side or the lowermost side of the circuit board.

[0137] Preferably, the protective layer may include a first protective layer 140 disposed on the upper surface of the third insulating layer 113. The first protective layer 140 may protect the upper surface of the third insulating layer 113 and the upper surface of the third circuit layer 123. In addition, the first protective layer 140 may include a first opening (not shown) overlapping at least a portion of the upper surface of the third circuit layer 123 in the thickness direction. The first opening may be formed to correspond to the mounting position of the electronic device or the contact position with the external substrate.

[0138] In addition, the protective layer may include a second protective layer 150 disposed on the lower surface of the fifth insulating layer 115. The second protective layer 150 may protect the lower surface of the fifth insulating layer 115 and the lower surface of the sixth circuit layer 126. In addition, the second protective layer 150 may include a second opening (not shown) overlapping at least a portion of the lower surface of the sixth circuit layer 126 in the thickness direction. The second opening may be formed to correspond to the mounting position of the electronic device or the contact position with the external substrate.

[0139] At this time, the first protection layer 140 and the second protection layer 150 may be solder resists, but are not limited thereto.

[0140] Meanwhile, the circuit board of the present embodiment may include a plurality of regions. For example, the circuit board may include a first region R1, a second region R2, and a third region R3. For example, the insulating layer 110 may include a first region R1, a second region R2, and a third region R3. For example, the circuit layer 120 may include a first region R1, a second region R2, and a third region R3. For example, the first protective layer 140 may include a first region R1, a second region R2, and a third region R3.

[0141] At this time, the first protective layer 140 of the present embodiment may have different structures for each region. For example, the first protective layer 140 of the present embodiment may have different heights or opening structures in the first region R1, the second region R2, and the third region R3. Hereinafter, the outermost insulating layer, the outermost circuit layer, and the outermost protective layer will be described. Preferably, the insulating layer arranged on the uppermost side of the circuit board, the circuit layer arranged on the uppermost side, and the protective layer arranged on the uppermost side will be described below. The insulating layer, circuit layer, and protective layer described below may refer to the insulating layer, circuit layer, and protective layer arranged on the uppermost side of the circuit board, but are not limited thereto. For example, the insulating layer, circuit layer, and protective layer described below may refer to the insulating layer, circuit layer, and protective layer arranged on the lowermost side of the circuit board.

[0142] Therefore, hereinafter, the third insulating layer 113 arranged on the uppermost side of the circuit board is referred to as the insulating layer 110 , the third circuit layer 123 arranged on the uppermost side is referred to as the circuit layer 120 , and the first protective layer 140 arranged on the uppermost side is referred to as the protective layer 140 .

[0143] The first region R1, the second region R2, and the third region R3 may be distinguished based on the difference in the structure of the opening region of the protective layer 140. The first region R1, the second region R2, and the third region R3 may be distinguished based on the type of configuration arranged on the circuit board. The first region R1, the second region R2, and the third region R3 may be distinguished based on the line width and spacing of the pads and traces of the circuit layer 120 arranged on the insulating layer 110.

[0144] The first region R1 may refer to an area where chips such as passive devices are mounted on a circuit board. The second region R2 may refer to an area where application chips are mounted on a circuit board. The third region R3 may refer to an area where a separate upper substrate (e.g., a memory substrate) is attached to the circuit board. Therefore, the structures of the openings of the protective layer 140 in the first region R1, the second region R2, and the third region R3 may be different from each other.

[0145] Hereinafter, the first region R1 , the second region R2 , and the third region R3 of the present embodiment will be described in detail.

[0146] For ease of explanation, the structures of the second region R2 and the third region R3 will be described first, and the structure of the first region R1 will be described last.

[0147] Figure 4 is a view showing the structure of the second area of ​​the circuit board according to the first embodiment, and Figure 5 is a view showing the structure of the second area of ​​the circuit board according to the second embodiment.

[0148] refer to Figure 4 , the second pattern portion 120 - 2 of the circuit layer 120 is arranged on the second region R2 of the insulating layer 110 . Figure 4 (a) is a plan view of a second region of the circuit board according to the first embodiment, and Figure 4 (b) is along Figure 4 (a) Cross-sectional view taken along the AA' direction.

[0149] At this time, the second region R2 may refer to a region where a fine circuit is required to mount a processor chip or a driver IC. Hereinafter, description will be made assuming that the chip mounted in the second region R2 is a processor chip.

[0150] The second pattern part 120-2 may represent a circuit pattern arranged in a second chip mounting region where a processor chip is mounted in the circuit layer 120. The second pattern part 120-2 includes a second pad 120-21 corresponding to a terminal of the processor chip and a second trace 120-22 connected to the second pad 120-21.

[0151] The second pattern section 120-2 needs to be miniaturized. For example, in the second region R2, pads connected to all terminals of the processor chip must be arranged in a limited space, and traces connected to the pads connected to the terminals must be arranged. Therefore, the second pattern section 120-2 may include a fine pattern.

[0152] In addition, in recent years, the functions processed by the processor chip are increasing. Therefore, it is difficult to realize all functions with one processor chip. Therefore, it is necessary to install two or more processor chips with different functions on one circuit board.

[0153] Therefore, if the processor chip includes first and second processor chips, miniaturization of the second pattern part 120 - 2 is required in order to connect all wirings between the first processor chip and the second processor chip within a limited space.

[0154] In addition, due to reasons such as 5G, Internet of Things (IoT), improved image quality, improved communication speed, etc., the number of terminals in the first processor chip and the second processor chip is gradually increasing. Therefore, in recent years, the connection wiring between the first processor chip and the second processor chip may be two or more times, three or more times, or ten or more times the conventional connection wiring.

[0155] Therefore, in order to mount the first processor chip and the second processor chip on a single circuit board while minimizing the interval therebetween and connecting the first processor chip and the second processor chip within a limited space, the second pattern part 120 - 2 is required to be ultra-fine.

[0156] The second pads 120-21 of the second pattern section 120-2 correspond to the terminals of the processor chip to be mounted on the circuit board. Therefore, the number of the second pads 120-21 corresponds to the number of the terminals of the processor chip.

[0157] The width of the second pad 120-21 in the first horizontal direction and the width of the second pad 120-21 in the second horizontal direction perpendicular to the first horizontal direction may be different from each other. In this case, the width of the second pad 120-21 in the separation direction of adjacent pads or traces may be smaller than the width in the direction perpendicular to the separation direction. In addition, the width of the second pad 120-21 in the separation direction has a great influence on the circuit integration.

[0158] That is, the second pad 120-21 may have an elliptical shape, and its width in the separation direction is smaller than the width in the direction perpendicular to the separation direction. However, the present embodiment is not limited thereto. For example, the second pad 120-21 may have a circular shape as a whole, and it has a certain width in the separation direction.

[0159] The width W1 of the second pad 120 - 21 may be 3 μm to 30 μm. For example, the width W1 of the second pad 120 - 21 may be 4 μm to 28 μm. For example, the width W1 of the second pad 120 - 21 may be 5 μm to 25 μm.

[0160] If the width W1 of the second pad 120-21 is less than 3 μm, it is difficult to stably position the adhesive member connected to the terminal of the processor chip. If the width W1 of the second pad 120-21 is less than 3 μm, the connection reliability between the second pad 120-21 and the processor chip may deteriorate. If the width W1 of the second pad 120-21 is greater than 30 μm, it may be difficult to place all the patterns connected to the processor chip in a limited space. If the width W1 of the second pad 120-21 is greater than 30 μm, the size of the circuit board may increase. If the width W1 of the second pad 120-21 is greater than 30 μm, the spacing between adjacent patterns is narrowed, and thus reliability problems such as circuit short circuits may occur.

[0161] The second pattern section 120-2 arranged in the second region R2 includes a second trace 120-22 connected to the second pad 120-21. The second trace 120-22 may refer to an elongated signal line connected to the second pad 120-21. In addition, when two processor chips are mounted on the second pattern section 120-2, the second trace 120-22 may include a signal line connecting the two chips.

[0162] The second trace 120-22 may include an ultra-fine pattern. For example, the line width W2 of the second trace 120-22 may meet the range of 1μm to 10μm. For example, the line width W2 of the second trace 120-22 may meet the range of 1.2μm to 8μm. For example, the line width W2 of the second trace 120-22 may meet the range of 1.5μm to 7μm. If the line width W2 of the second trace 120-22 is less than 1μm, the resistance of the second trace 120-22 increases, and therefore, normal communication with the processor chip may become difficult. In addition, if the line width W2 of the second trace 120-22 is less than 1μm, it may be difficult to apply a conventional circuit pattern manufacturing process. If the line width W2 of the second trace 120-22 is less than 1μm, a physical reliability problem in which the second trace 120-22 breaks due to various factors may occur. If the line width W2 of the second trace 120-22 is greater than 10 μm, it may be difficult to arrange all signal lines connected to the terminals of the processor within a limited space. For example, if the line width W2 of the second trace 120-22 is greater than 10 μm, it may be difficult to arrange all traces for connecting multiple processor chips within a limited space. For example, if the line width W2 of the second trace 120-22 is greater than 10 μm, the area of ​​the second region R2 may increase, and therefore, the size of the circuit board and the semiconductor package may increase.

[0163] Meanwhile, the second pattern section 120-2 may be spaced apart from each other by a certain spacing W3 on the second region R2. The spacing W3 may represent the spacing between the second pads 120-21 of the second pattern section 120-2. In addition, the spacing W3 may represent the spacing between the second traces of the second pattern section 120-2. In addition, the spacing W3 may represent the spacing between the second pads 120-21 and the second traces 120-22 of the second pattern section 120-2 that are adjacent to each other.

[0164] The spacing W3 may have a range of 1 μm to 10 μm. The spacing W3 may have a range of 1.2 μm to 8 μm. The spacing W3 may have a range of 1.5 μm to 7 μm. If the spacing W3 is less than 1 μm, there is a problem that adjacent second traces or second pads are connected to each other, resulting in an electrical short circuit. For example, if the spacing W3 is greater than 10 μm, it may be difficult to place all traces for connecting multiple processor chips in a limited space.

[0165] As described above, relatively dense circuit patterns are arranged in the second region R2. For example, the second pattern portion 120-2 having a smaller width and pitch than the first region R1 or the third region R3 is arranged in the second region R2. In addition, it may be difficult to form an SRO on the second pad 120-21 of the second pattern portion 120-2 with an exposure resolution of a conventional solder resist. Therefore, as Figure 4In (b), the protective layer 140 may not be arranged in the second region R2. In other words, the protective layer 140 may not overlap the second region R2 in the vertical direction. That is, the second pattern portion 120-2 arranged in the second region R2 is a fine pattern, and due to the limitation of the resolution of the SRO used to form the protective layer 140, the SRO of the protective layer 140 may be difficult to form corresponding to the fine pattern in the second region R2.

[0166] At the same time, reference Figure 5 , the second trace 120-22 arranged in the second region R2 is a fine pattern and is a pattern arranged on the outermost layer. In addition, the second trace 120-22 has a structure protruding on the upper surface of the insulating layer 110. Therefore, during the subsequent manufacturing process, the second trace 120-22 may be damaged while being formed. As a result, problems may occur in terms of physical reliability of the second trace 120-22.

[0167] Therefore, the third protection pattern 142 of the protection layer 140 may be formed in the second region R2 a of the second embodiment.

[0168] At this time, the third protection pattern 142 may have the same height or thickness as a whole in the second region R2a. Here, the third protection pattern 142 having the same height or thickness as a whole may mean that the height difference of the upper surface of the third protection pattern 142 in the second region R2a is less than 3 μm, less than 2 μm, less than 1 μm, and less than 0.5 μm.

[0169] At this time, the thickness T1 of the second pattern part 120 - 2 arranged in the second region R2 a may be 10 μm to 25 μm.

[0170] In addition, the third protection pattern 142 of the protection layer 140 may have a thickness T2 that is smaller than the thickness T1 of the second pattern portion 120-2. For example, the thickness T2 of the third protection pattern 142 may satisfy a range of 40% to 90% of the thickness T1 of the second pattern portion 120-2. Preferably, the thickness T2 of the third protection pattern 142 may satisfy a range of 45% to 85% of the thickness T1 of the second pattern portion 120-2. For example, the thickness T2 of the third protection pattern 142 may satisfy a range of 50% to 80% of the thickness T1 of the second pattern portion 120-2.

[0171] For example, the thickness T2 of the third protection pattern 142 may be 4 μm to 22 μm. For example, the thickness T2 of the third protection pattern 142 may be 4.5 μm to 21 μm. For example, the thickness T2 of the third protection pattern 142 may be 5 μm to 20 μm.

[0172] If the thickness T2 of the third protection pattern 142 is less than 40% of the thickness T1 of the second pattern portion 120-2, the effect of the third protection pattern 142 in protecting the second pattern portion 120-2 may be insufficient. In addition, if the thickness T2 of the third protection pattern 142 is greater than 90% of the thickness T1 of the second pattern portion 120-2, residual resin of the protection layer 140 may remain on the upper surface of the second pattern portion 120-2. In addition, if the residual resin remains, problems may occur in terms of electrical reliability.

[0173] As in the first embodiment, the upper surface and the side surface of the second pattern section 120 - 2 in the second region R2 may not completely contact the protective layer 140 .

[0174] In addition, the upper surface of the second pattern portion 120-2 in the second region R2a in the second embodiment may not completely contact the protective layer 140. In addition, the side surface of the second pattern portion 120-2 in the second region R2a in the second embodiment may be partially covered by the protective layer 140. For example, at least a portion of the side surface of the second pattern portion 120-2 may be covered by the protective layer 140, while another portion of the side surface of the second pattern portion 120-2 may not contact the protective layer 140.

[0175] That is, in the second embodiment, a process of thinning the thickness of the protective layer (e.g., a thinning process, or a process of forming the protective layer of the first region described below) may be performed in a state where the protective layer covering the entire upper surface of the second pattern portion 120-2 is formed on the second region R2a. Therefore, the protective layer 140 of the second embodiment may include a third protective pattern that is arranged in the second region R2a and has a height lower than that of the upper surface of the second pattern portion 120-2 as a whole.

[0176] Figure 6 is a view showing a structure of a third region of a circuit board according to an embodiment.

[0177] Figure 6 (a) is a plan view of the third region of the circuit board of this embodiment, and Figure 6 (b) is along Figure 6 (a) Cross-sectional view taken along the BB' direction.

[0178] refer to Figure 6 (a) and (b), the third pattern section 120 - 3 having a relatively larger width and interval than the second pattern section 120 - 2 arranged in the second region R2 is arranged in the third region R3 .

[0179] The third region R3 refers to a region in which pads or bumps connected to a separate package substrate (eg, a memory substrate) are arranged.

[0180] The third pattern part 120 - 3 includes a third pad 120 - 31 and a third trace 120 - 3 .

[0181] The width W4 of the third pad 120 - 31 satisfies the range of 30 μm to 70 μm. For example, the width W4 of the third pad 120 - 31 satisfies the range of 35 μm to 65 μm. For example, the width W4 of the third region R3 satisfies the range of 35 μm to 50 μm.

[0182] In addition, the spacing W5 between adjacent patterns in the third region R3 satisfies the range of 10 μm to 40 μm. For example, the spacing W5 between adjacent patterns in the third region R3 satisfies the range of 12 μm to 30 μm. For example, the spacing W5 between adjacent patterns in the third region R3 satisfies the range of 13 μm to 25 μm.

[0183] Furthermore, unlike the second region R2, the third trace 120-3 of the third pad 120-31 arranged in the third region R3 does not require a fine line width or a fine pitch.

[0184] Therefore, a protective layer 140 having a structure different from that in the second region R2 is formed in the third region R3.

[0185] For example, the protection layer 140 includes a fourth protection pattern 143 arranged in the third region R3 .

[0186] The fourth protection pattern 143 is arranged in the third region R3, and its thickness is greater than the thickness of the third pad 120-31. At this time, the fourth protection pattern 143 can be arranged to cover at least a portion of the upper surface of the third pad 120-31. In addition, the fourth protection pattern 143 includes an opening 143-1 that overlaps at least a portion of the upper surface of the third pad 120-31 in the thickness direction.

[0187] That is, the side surface of the third pad 120 - 31 may be completely covered by the fourth protection pattern 143 of the protection layer 140 .

[0188] In addition, the upper surface of the third pad 120 - 31 may be partially covered by the fourth protection pattern 143 of the protection layer 140 .

[0189] Specifically, the third pad 120 - 31 may include a first portion 120 - 31 a overlapping the opening 143 - 1 of the fourth protection pattern 143 of the protection layer 140 in the thickness direction, and a second portion 120 - 31 b covered by the fourth protection pattern 143 .

[0190] Furthermore, the upper surface of the third trace 120-3 may be completely covered by the fourth protection pattern 143 of the protection layer 140. However, the present embodiment is not limited thereto, but a portion of the upper surface of the third trace 120-3 adjacent to the third pad 120-31 may not contact the fourth protection pattern 143 of the protection layer 140.

[0191] In summary, the protection layer 140 in the third region R3 may have a SMD structure.

[0192] As described above, the protection layer 140 of the present embodiment has different structures in the second region R2 and the third region R3 .

[0193] For example, the protective layer 140 may not be arranged in the second region R2. In contrast, the protective layer 140 may not completely contact the upper surface of the second pattern portion 120-2 in the second region R2a. For example, the protective layer 140 may be positioned lower than the upper surface of the second pattern portion 120-2 in the second region R2a.

[0194] In addition, the protective layer 140 may be positioned higher than the upper surface of the third pattern portion 120-3 in the third region R3. For example, the protective layer 140 may cover at least a portion of the upper surface of the third pattern portion 120-3 in the third region R3. For example, the protective layer 140 may have an SMD structure in the third region R3.

[0195] Meanwhile, the protective layer 140 in the first region R1 may have a different structure from that in the second region R2 and / or the third region R3. Here, the different structure may mean that the structure of the opening portion formed in the protective layer 140 is different, and may mean that the height or thickness is different.

[0196] Figure 7a is a plan view of a first region of a circuit board according to a first embodiment, Figure 7b It is along Figure 7a The cross-sectional view taken along the C-C' direction, Figure 7c It is along Figure 7a A cross-sectional view taken along the D-D' direction, and Figure 8 is a perspective view showing a semiconductor device mounted on a first area of ​​a circuit board according to an embodiment.

[0197] In the following, reference will be made to FIGS. 7 to 8. Figure 8 A first region of a circuit board according to an embodiment is described in detail.

[0198] In the first region R1, a first pattern portion 120-1 is arranged, which has a relatively larger width and spacing than the pattern portions arranged in the second region R2 and the third region R3. At this time, the first pattern portion 120-1 includes a plurality of pads. At this time, no trace may be arranged in the first region R1. That is, the first pattern portion 120-1 may include only a plurality of pads. For example, the first pattern portion 120-1 may include only island pads that are not directly connected to other patterns arranged on the upper surface of the insulating layer 110, and may be arranged in the first region R1. However, the present embodiment is not limited thereto, and in some cases, the trace connected to the first pattern portion 120-1 may be arranged in the first region R1.

[0199] The first pattern portion 120 - 1 includes a first pad. For example, the first pattern portion 120 - 1 includes a 1-1 pad 120 - 11 and a 1-2 pad 120 - 12 connected to the same first semiconductor device.

[0200] The 1-1 pad 120-11 may be a pad connected to a first terminal of a first semiconductor device, and the 1-2 pad 120-12 may be a pad connected to a second terminal of the first semiconductor device. In addition, although the figure shows a first pad connected to the same first semiconductor device, the embodiment is not limited thereto. For example, a plurality of first pads connected to at least two or more first semiconductor devices may be arranged in the first region R1. In addition, each of the plurality of first pads may include a 1-1 pad and a 1-2 pad.

[0201] The 1-1 pad 120-11 and the 1-2 pad 120-12 may be large-area pads. For example, the terminals of the first chip have a relatively large size. Here, "having a relatively large size" may mean that the size of each terminal provided in the first chip is larger than the size of each terminal of the second chip (e.g., a processor chip).

[0202] The 1-1st pad 120-11 and the 1-2nd pad 120-12 may be spaced apart from each other in a first horizontal direction. The first horizontal direction may refer to a width direction, an x-axis direction, and a horizontal direction in the drawing.

[0203] The 1-1 pad 120 - 11 and the 1-2 pad 120 - 12 may have a width W6 in a second horizontal direction perpendicular to the first horizontal direction, the width W6 being greater than a width W7 in the first horizontal direction.

[0204] The width W6 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the second horizontal direction may satisfy the range of 125% to 220% of the width W7 in the first horizontal direction. The width W6 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the second horizontal direction may satisfy the range of 130% to 210% of the width W7 in the first horizontal direction. The width W6 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the second horizontal direction may satisfy the range of 140% to 200% of the width W7 in the first horizontal direction.

[0205] If the width W6 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 in the second horizontal direction is less than 125% of the width W7 in the first horizontal direction, it may be difficult to stably place the first semiconductor device. If the width W6 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 in the second horizontal direction is less than 125% of the width W7 in the first horizontal direction, the mounting characteristics of the first chip or the electrical reliability with the first semiconductor device may be deteriorated. If the width W6 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 in the second horizontal direction exceeds 220% of the width W7 in the first horizontal direction, the arrangement space of the first pattern portion 120-1 may increase, and thus, the size of the circuit board may increase.

[0206] For example, each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 may have a width W6 in the second horizontal direction in the range of 210 μm ± 15 μm. In addition, when the width W6 in the second horizontal direction has a range of 210 μm ± 15 μm, the width W7 in the first horizontal direction may have a range of 140 μm ± 15 μm.

[0207] For example, each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 may have a width W6 in the second horizontal direction of 310 μm ± 15 μm. In addition, when the width W6 in the second horizontal direction has a range of 310 μm ± 15 μm, the width W7 in the first horizontal direction may have a range of 190 μm ± 15 μm.

[0208] For example, each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 may have a width W6 in the second horizontal direction of 660 μm ± 15 μm. In addition, when the width W6 in the second horizontal direction has a range of 660 μm ± 15 μm, the width W7 in the first horizontal direction may have a range of 450 μm ± 15 μm.

[0209] Preferably, the width W6 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the second horizontal direction may exceed 195 μm. Preferably, the width W6 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the second horizontal direction may exceed 295 μm. Preferably, the width W6 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the second horizontal direction may exceed 645 μm.

[0210] Preferably, the width W7 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the first horizontal direction may exceed 125 μm. Preferably, the width W7 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the first horizontal direction may exceed 175 μm. Preferably, the width W7 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the first horizontal direction may exceed 435 μm.

[0211] Meanwhile, the spacing W8 between the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the first region R1 may satisfy a range of 70% to 120% of the width W7 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the first horizontal direction. The spacing W8 between the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the first region R1 may satisfy a range of 75% to 115% of the width W7 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the first horizontal direction. The spacing W8 between the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the first region R1 may satisfy a range of 80% to 110% of the width W7 of each of the 1-1st pad 120-11 and the 1-2nd pad 120-12 in the first horizontal direction.

[0212] If the spacing W8 between the 1-1 pad 120-11 and the 1-2 pad 120-12 in the first region R1 is less than 70% of the width W7 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 in the first horizontal direction, a circuit short circuit problem may occur when a plurality of adhesive members are connected to each other during mounting of the first chip. If the spacing W8 between the 1-1 pad 120-11 and the 1-2 pad 120-12 in the first region R1 exceeds 120% of the width W7 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 in the first horizontal direction, connectivity with the first semiconductor device may be deteriorated.

[0213] As described above, the first pattern portion 120-1 having a relatively large width and a relatively large pitch is arranged in the first region R1 of the circuit board. Therefore, the opening structure of the protective layer 140 in the first region R1 generally has an SMD structure. That is, as in the first comparative example, the protective layer 140 in the first region of the general circuit board has an SMD structure covering at least a portion of the upper surface of the first pattern portion.

[0214] In contrast, the present embodiment allows the protection layer 140 to have a new opening structure so as not to increase the thickness of the semiconductor package due to the protection layer 140 when arranged in the first region R1 .

[0215] That is, the protection layer 140 includes the protection portion 141 disposed in the first region R1 .

[0216] The protective portion 141 may have different heights depending on the position. Preferably, the protective portion 141 contacts at least a portion of the side surface of the first pattern portion 120-1, but does not contact the upper surface of the first pattern portion 120-1. Here, the fact that the protective portion 141 contacts at least a portion of the side surface of the first pattern portion 120-1 means that at least a portion of the side surface of the first pattern portion 120-1 does not contact the first protective layer 140.

[0217] The protection portion 141 includes a first protection pattern 141 - 1 adjacent to the first pattern portion 120 - 1 in the first region R1 and a second protection pattern 141 - 2 except for the first protection pattern 141 - 1 .

[0218] At this time, the present embodiment may perform a thinning process for the thickness of the protective layer 140, thereby providing the first protection pattern 141-1 and the second protection pattern 141-2 in the protective layer 140. At this time, the inner wall of the second protection pattern 141-2 may have a slope along the thickness direction of the protective layer 140. For example, the inner wall of the second protection pattern 141-2 may have a slope whose width changes along the thickness direction. Preferably, the inner walls of the first protection pattern 141-1 and the second protection pattern 141-2 of the present embodiment are provided by a process of selectively thinning the thickness of the protective layer 140, and thus may have a curved surface with a certain curvature, the width of which decreases along the thickness direction.

[0219] Therefore, the present embodiment can make the inner wall of the second protection pattern 141-2 have a curved surface, and thus can increase the contact area between the second protection pattern 141-2 and the mold layer. Therefore, the present embodiment can solve the problem that the mold layer is peeled off from the protection layer, and then can make the mold layer more stably fix the semiconductor device.

[0220] In addition, since the inner wall of the second protection pattern 141-2 has a curved surface, the present embodiment can increase the distance between the upper surface of the protection layer 140 corresponding to the curvature of the curved surface and the first pattern portion 120-1. At this time, the semiconductor package may be subjected to stress due to thermal cycles such as expansion and / or contraction in the manufacturing process and / or the use environment. At this time, the stress may be transmitted to the first pattern portion 120-1, and thus the electrical reliability of the first semiconductor device mounted on the first pattern portion 120-1 may be affected. For example, when the stress is transmitted to the interface between the first pattern portion 120-1 and the first semiconductor device, cracks may occur, and reliability problems in which the first semiconductor device is electrically separated from the first pattern portion 120-1 may occur. On the other hand, the present embodiment can allow the inner wall of the second protection pattern 141-2 to have a curved surface, thereby preventing the stress from being transmitted to the interface between the first semiconductor device and the first pattern portion 120-1, thereby improving the electrical reliability and / or physical reliability of the semiconductor package.

[0221] The first protection pattern 141-1 may be disposed in a region adjacent to the first pattern portion 120-1 in the first region R1. The second protection pattern 141-2 may be disposed in an edge region of the first region R1 except for a region where the first protection pattern 141-1 is disposed.

[0222] For example, the first protection pattern 141-1 may be disposed to surround at least a portion of the side surfaces of the 1-1st and 1-2nd pads of the first pattern portion 120-1 and may be disposed between the 1-1st and 1-2nd pads. In addition, the second protection pattern 141-2 may be disposed to surround the first protection pattern 141-1.

[0223] For example, the first protection pattern 141-1 may be arranged in the peripheral region of the surface of the 1-1st pad 120-11 and the 1-2nd pad 120-12. In addition, the first protection pattern 141-1 may be arranged in the region between the 1-1st pad 120-11 and the 1-2nd pad 120-12. For example, the first protection pattern 141-1 includes a first portion 141-11 arranged between the 1-1st pad 120-11 and the 1-2nd pad 120-12. In addition, the first protection pattern 141-1 includes a second portion 141-12 surrounding the side surface of the 1-1st pad 120-11, the side surface of the 1-2nd pad 120-12, and the side surface of the first portion 141-11.

[0224] That is, the first protection pattern 141 - 1 may be arranged in the first region R1 to surround a peripheral region of the first pattern portion 120 - 1 , including a region between the 1-1st pad 120 - 11 and the 1-2nd pad 120 - 12 .

[0225] An upper surface of the first protection pattern 141-1 may be positioned lower than an upper surface of the first pattern portion 120-1. That is, a thickness T2 of the first protection pattern 141-1 may be less than a thickness T1 of the first pattern portion 120-1.

[0226] The thickness T1 of the first pattern portion 120 - 1 may be 10 μm to 25 μm. Preferably, the thickness T1 of the first pattern portion 120 - 1 may be 12 μm to 23 μm. More preferably, the thickness T1 of the first pattern portion 120 - 1 may have a thickness of 12 μm to 20 μm.

[0227] The thickness T2 of the first protection pattern 141 - 1 may be 3 μm to 21 μm. The thickness T2 of the first protection pattern 141 - 1 may be 4 μm to 19 μm. The thickness T2 of the first protection pattern 141 - 1 may be 5 μm to 16 μm.

[0228] If the thickness T2 of the first protection pattern 141-1 is less than 3 μm, the effect produced by the first protection pattern 141-1 according to the embodiment may be insufficient. For example, if the thickness T2 of the first protection pattern 141-1 is less than 3 μm, the anti-short circuit effect between the multiple adhesive members arranged on the 1-1 pad 120-11 and the 1-2 pad 120-12 may be insufficient. For example, if the thickness T2 of the first protection pattern 141-1 is less than 3 μm, there may be a limitation in reducing the spacing between the 1-1 pad 120-11 and the 1-2 pad 120-12. For example, if the thickness T2 of the first protection pattern 141-1 exceeds 21 μm, there may be a problem that the residual resin of the protective layer 140 remains on the 1-1 pad 120-11 or the 1-2 pad 120-12. For example, if the thickness T2 of the first protection pattern 141 - 1 exceeds 21 μm, a reliability problem may occur in which at least a portion of the upper surface of the 1-1th pad 120 - 11 or the 1-2th pad 120 - 12 is covered by the first protection pattern 141 due to process errors.

[0229] In addition, the thickness T2 of the first protection pattern 141-1 may satisfy the range of 40% to 90% of the thickness T1 of the first pattern portion 120-1. Preferably, the thickness T2 of the first protection pattern 141-1 may satisfy the range of 45% to 85% of the thickness T1 of the first pattern portion 120-1. For example, the thickness T2 of the first protection pattern 141-1 may satisfy the range of 50% to 80% of the thickness T1 of the first pattern portion 120-1.

[0230] Meanwhile, in the present embodiment, the height difference (TΔ) between the upper surfaces of the first pattern section 120-1 and the first protection pattern 141-1 is set to be 3 μm or more. The height difference (TΔ) may represent a vertical distance between the upper surfaces of the first pattern section 120-1 and the first protection pattern 141-1.

[0231] In the present embodiment, the height difference (TΔ) between the upper surface of the first pattern portion 120-1 and the upper surface of the first protection pattern 141-1 is set to be 3.5 μm or more. More preferably, in the present embodiment, the height difference (TΔ) between the upper surface of the first pattern portion 120-1 and the upper surface of the first protection pattern 141-1 is set to be 4 μm or more. At this time, the upper surface of the first pattern portion 120-1 may not be a plane, and the upper surface of the protection portion 141 may not be a plane. At this time, the height difference (TΔ) may represent the height difference between the uppermost end of the first pattern portion 120-1 and the uppermost end of the first protection pattern 141-1.

[0232] If the height difference (TΔ) between the upper surfaces of the first pattern portion 120-1 and the first protection pattern 141-1 is less than 3 μm, there may be a problem that residual resin remains on the upper surface of the first pattern portion 120-1 or at least a portion of the upper surface of the first pattern portion 120-1 is covered by the first protection pattern 141-1 due to a process error.

[0233] Preferably, the height difference (TΔ) between the upper surface of the first pattern portion 120-1 and the upper surface of the first protection pattern 141-1 is 3 μm to 10 μm. As a result, the first protection pattern 141-1 having an optimal height can be provided regardless of the thickness of the first pattern portion 120-1. That is, if the height difference (TΔ) exceeds 10 μm, the effect produced by the first protection pattern 141-1 may be insufficient.

[0234] Meanwhile, the protection part 141 includes a second protection pattern 141-2 arranged around the first protection pattern 141-1. The second protection pattern 141-2 may have a thickness greater than that of the first protection pattern 141-1. In addition, the second protection pattern 141-2 may have a thickness greater than that of the first pattern part 120-1.

[0235] Preferably, the upper surface of the second protection pattern 141-2 may be positioned higher than the upper surface of the first protection pattern 141-1. In addition, the upper surface of the second protection pattern 141-2 may be positioned higher than the upper surface of the first pattern part 120-1.

[0236] The thickness T3 of the second protection pattern 141 - 2 may be 17 μm to 45 μm. Preferably, the thickness T3 of the second protection pattern 141 - 2 may be 19 μm to 43 μm. More preferably, the thickness T3 of the second protection pattern 141 - 2 may have a thickness of 19 μm to 40 μm.

[0237] The second protection pattern 141 - 2 is arranged to surround the first protection pattern 141 - 1 .

[0238] At this time, the width W9 between the first pattern portion 120-1 and the second protection pattern 141-2 in the first protection pattern 141-1 may have a range of 13 μm to 25 μm. Preferably, the width W9 between the first pattern portion 120-1 and the second protection pattern 141-2 in the first protection pattern 141-1 may have a range of 15 μm to 23 μm. The width W9 between the first pattern portion 120-1 and the second protection pattern 141-2 in the first protection pattern 141-1 may have a range of 16 μm to 20 μm.

[0239] Specifically, the 1-1st pad 120-11 includes a plurality of side surfaces. The plurality of side surfaces of the 1-1st pad 120-11 include a 1-1st side surface facing the side surface of the 1-2nd pad 120-12, and a 1-2nd side surface other than the 1-1st side surface. In addition, the width W9 may represent a horizontal distance between the 1-2nd side surface of the 1-1st pad 120-11 and the inner wall of the second protection pattern 141-2 adjacent to the 1-2nd side surface.

[0240] In addition, the 1-2nd pad 120-12 includes a plurality of side surfaces. The plurality of side surfaces of the 1-2nd pad 120-12 include a 2-1st side surface facing the 1-1st side surface of the 1-1st pad 120-11, and a 2-2nd side surface other than the 2-1st side surface. In addition, the width W9 may represent a horizontal distance between the 2-2nd side surface of the 1-2nd pad 120-12 and the inner wall of the second protection pattern 141-2 of the first protection layer 140 adjacent to the 2-2nd side surface.

[0241] If the width W9 is less than 13 μm, the following problem may occur: wherein, due to a manufacturing process error, the second protection pattern 141-2 of the protection layer 140 overlaps with the first chip in the thickness direction. For example, the design of the 1-1 pad 120-11 and the 1-2 pad 120-12 is performed by considering the process error in the arrangement process of the first semiconductor device. For example, the first semiconductor device can be arranged on the 1-1 pad 120-11 and the 1-2 pad 120-12 with a certain error range. In addition, the width W9 may be a value taking into account the error range. At this time, if the width W9 is less than 13 μm, the following problem may occur: wherein, the error range is not fully covered, and accordingly, the following problem may occur, wherein during the installation process of the first chip, at least a portion of the first chip contacts the second protection pattern 141-2. In addition, if the width W9 exceeds 25 μm, the area of ​​the first region R1 increases, and therefore, the overall size of the circuit board may increase.

[0242] At the same time, refer to Figure 8 The design of the first region R1 as described above is set based on the size of the first semiconductor device 200 arranged on the 1-1 pad 120-11 and the 1-2 pad 120-12. At this time, the first semiconductor device 200 may be various devices, but it may be, for example, a multilayer ceramic capacitor.

[0243] The first semiconductor device 200 includes a body 210. In addition, the first semiconductor device 200 includes a first terminal 220 arranged on one side of the body 210 and connected to the 1-1 pad 120-11. In addition, the first semiconductor device 200 includes a second terminal 230 arranged on the other side of the body 210 and connected to the 1-2 pad 120-12. The first terminal 220 and the second terminal 230 may be arranged to be spaced apart in a second horizontal direction, which is a separation direction of the 1-1 pad 120-11 and the 1-2 pad 120-12.

[0244] The width (L) of the first semiconductor device 200 in the second horizontal direction may be greater than the width (W) in the first horizontal direction perpendicular to the second horizontal direction.

[0245] The width (L) of the first semiconductor device 200 in the second horizontal direction may satisfy a range of 125% to 220% of the width (W) in the first horizontal direction. The width (L) of the first semiconductor device 200 in the second horizontal direction may satisfy a range of 130% to 210% of the width (W) in the first horizontal direction. The width (L) of the first semiconductor device 200 in the second horizontal direction may satisfy a range of 140% to 200% of the width (W) in the first horizontal direction.

[0246] For example, the first semiconductor device 200 may have a width (W) in the first horizontal direction of 200 μm ± 15 μm, and a width (L) in the second horizontal direction of 400 μm ± 15 μm. In this case, the thickness (T) of the first semiconductor device 200 may have a range of 200 μm ± 50 μm.

[0247] As another example, the first semiconductor device 200 may have a width (W) in the first horizontal direction in the range of 300 μm ± 15 μm, and a width (L) in the second horizontal direction in the range of 600 μm ± 15 μm. In this case, the thickness (T) of the first semiconductor device 200 may have a range of 400 μm ± 100 μm.

[0248] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 500 μm ± 15 μm, and the width (L) in the second horizontal direction may have a range of 1000 μm ± 15 μm. In addition, in this case, the thickness (T) of the first semiconductor device 200 may have a range of 450 μm ± 250 μm.

[0249] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 800 μm±15 μm, and the width (L) in the second horizontal direction may have a range of 1500 μm±15 μm.

[0250] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 1300 μm±15 μm, and the width (L) in the second horizontal direction may have a range of 2000 μm±15 μm.

[0251] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 2000 μm±15 μm, and the width (L) in the second horizontal direction may have a range of 2500 μm±15 μm.

[0252] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 1500 μm±15 μm, and the width (L) in the second horizontal direction may have a range of 3000 μm±15 μm.

[0253] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 2500 μm±15 μm, and the width (L) in the second horizontal direction may have a range of 3200 μm±15 μm.

[0254] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 1600 μm±15 μm, and the width (L) in the second horizontal direction may have a range of 4500 μm±15 μm.

[0255] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 3000 μm±15 μm, and the width in the second horizontal direction may have a range of 4600 μm±15 μm.

[0256] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 250 μm±15 μm, and the width (L) in the second horizontal direction may have a range of 5000 μm±15 μm.

[0257] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 3200 μm±15 μm, and the width (L) in the second horizontal direction may have a range of 6300 μm±15 μm.

[0258] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 6300 μm±15 μm, and the width in the second horizontal direction may have a range of 6900 μm±15 μm.

[0259] As another example, the width (W) of the first semiconductor device 200 in the first horizontal direction may have a range of 5100 μm±15 μm, and the width (L) in the second horizontal direction may have a range of 7400 μm±15 μm.

[0260] The circuit board of the present embodiment includes a first region in which a first semiconductor device is arranged.

[0261] In addition, the circuit board includes a 1-1 pad and a 1-2 pad. The 1-1 pad and the 1-2 pad are arranged to overlap with the first semiconductor device in the vertical direction. For example, the 1-1 pad and the 1-2 pad are arranged in the first area of ​​the circuit board. In addition, the present embodiment includes a protective layer. The protective layer includes a first protection pattern, which is arranged between the 1-1 pad and the 1-2 pad and surrounds at least a portion of the side surface of the 1-1 pad and the side surface of the 1-2 pad. In addition, the protective layer includes a second protection pattern arranged around the first protection pattern.

[0262] The first protection pattern contacts at least a portion of the side surfaces of the 1-1st pad and the 1-2nd pad, but does not contact the upper surfaces of the 1-1st pad and the 1-2nd pad. For example, the upper surface of the first protection pattern is positioned lower than the upper surfaces of the 1-1st pad and the 1-2nd pad. Therefore, the present embodiment can reduce the thickness and width of the contact member to be arranged on the 1-1st pad and the 1-2nd pad by using the first protection pattern.

[0263] For example, the first comparative example has a problem in which the thickness of the contact member increases due to the arrangement of the protective layer, and the second comparative example has a problem in which the expansion degree of the contact member increases due to the non-arrangement of the protective layer, thereby increasing the width of the contact member.

[0264] In contrast, the present embodiment can reduce the expansion degree of the contact member and reduce the width of the contact member by using a combination of the first protection pattern and the second protection pattern. In addition, the present embodiment provides only the first protection pattern in the region vertically overlapping with the first semiconductor device. For example, the second protection pattern does not overlap with the first semiconductor device vertically. Therefore, the present embodiment can prevent the thickness of the contact member from increasing due to the height of the protection layer.

[0265] Therefore, the present embodiment can reduce the thickness of the semiconductor package, thereby achieving miniaturization. In addition, the present embodiment can solve the problem of short circuit between adjacent contact members by reducing the expansion degree of the contact member. As a result, the present embodiment can improve the electrical reliability and product reliability of the semiconductor package. In addition, the present embodiment can solve the problem of circuit short circuit without increasing the spacing between the 1-1 pad and the 1-2 pad, thereby improving the circuit integration.

[0266] In addition, the present embodiment can solve the problem of the adhesive member being connected between the insulating layer and the pad by using the first protection pattern, thereby further improving product reliability.

[0267] Meanwhile, it has been explained that the vertical cross-section of the first pattern portion 120-1 in the first embodiment has a rectangular shape, and therefore, the upper surface of the first pattern portion 120-1 is flat, and at least a portion of the side surface of the first pattern portion 120-1 does not contact the first protection pattern 141 of the protective layer 140.

[0268] Fig. 9 is a plan view of a first region of a circuit board according to a second embodiment.

[0269] refer to Fig. 9 During the process of forming the circuit pattern, the first pattern portion 120-1a may be deformed. For example, the upper surface of the first pattern portion 120-1a may have a curved surface instead of a flat surface.

[0270] Therefore, upper surfaces of the first pad 120 - 11 a and the second pad 120 - 12 a of the first pattern portion 120 - 1 a may change in height in a horizontal direction.

[0271] like Fig. 9 As shown, when the upper surfaces of the first and second pads 120 - 11 a and 120 - 12 a have curved surfaces, it may be difficult to accurately determine the positions at which the upper surfaces of the first and second pads 120 - 11 a and 120 - 12 a extend.

[0272] In this case, the upper surface of the first pad 120 - 11 a and the second pad 120 - 12 a in the second embodiment may refer to from a start portion to an end portion of the curved surface.

[0273] Therefore, the first protection pattern 141 - 1 of the protection layer 140 may completely cover the side surfaces of the first pad 120 - 11 a and the second pad 120 - 12a , or may partially cover the side surfaces of the first pad 120 - 11a and the second pad 120 - 12a .

[0274] However, the uppermost end UM2 of the first protection pattern 141 - 1 may be positioned lower than the uppermost ends UM1 of the first and second pads 120 - 11 a and 120 - 12 a .

[0275] Fig.10a is a plan view of a first region of a circuit board according to a third embodiment, Fig.10b It is along Fig.10a The cross-sectional view taken along the E-E' direction is Fig.10c It is along Fig.10a A cross-sectional view taken along the F-F' direction, and Fig.10d yes Fig.10c A variation of the structure of .

[0276] In the following, reference will be made to Figures 10a to 10d The first area of ​​the circuit board according to the third embodiment will be described in detail.

[0277] The first pattern section 120 - 1 is arranged in the first region R1a of the third embodiment. The first pattern section 120 - 1 includes a 1-1st pad 120 - 11 and a 1-2nd pad 120 - 12 .

[0278] The protection portion 141 a of the protection layer 140 is arranged in the first region R1 a .

[0279] The protective portion 141a may have different heights depending on the position. Preferably, the protective portion 141a does not contact the upper surface of the first pattern portion 120-1, but contacts at least a portion of the side surface of the first pattern portion 120-1. Here, the fact that the protective portion 141 contacts at least a portion of the side surface of the first pattern portion 120-1 means that at least a portion of the side surface of the first pattern portion 120-1 does not contact the first protective layer 140.

[0280] The protection portion 141 a includes a first protection pattern 141 - 1 a adjacent to the first pattern portion 120 - 1 in the first region R1 a , and a second protection pattern 141 - 2 a except for the first protection pattern 141 - 1 a .

[0281] For example, the first protection pattern 141-1a may be arranged on at least a portion of the peripheral area of ​​the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12. At this time, the first protection pattern 141-1 of the previous embodiment is arranged to completely surround the peripheral area of ​​the first pad 120-11 and the second pad 120-12. The first protection pattern 141-1 of the previous embodiment is arranged to surround the peripheral area of ​​the first pad 120-11 and the second pad 120-12 in a closed loop shape.

[0282] Different from this, the first protection pattern 141-1a of the third embodiment may be arranged on at least a portion of the peripheral area of ​​the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12. That is, the first protection pattern 141-1a may not be arranged in at least some areas surrounding the first pad 120-11 and the second pad 120-12. For example, the first protection pattern 141-1a is arranged to surround the peripheral area of ​​the first pad 120-11 and the second pad 120-12 in a closed loop shape.

[0283] That is to say, Fig.10b As shown, the first protection pattern 141-1a includes a first portion 141-11a arranged between the 1-1st pad 120-11 and the 1-2nd pad 120-12. In addition, the first protection pattern 141-1a includes a second portion 141-12a, which is arranged to surround the side surface of the 1-1st pad 120-11, the side surface of the 1-2nd pad 120-12, and the side surface of the first portion 141-11a. The second portion 141-12a may not contact at least a portion of the side surface of the 1-1st pad 120-11 and the side surface of the 1-2nd pad 120-12.

[0284] Meanwhile, the second protection pattern 141-2a is arranged around the first protection pattern 141-1a. The second protection pattern 141-2a may have a thickness greater than that of the first protection pattern 141-1a. In addition, the second protection pattern 141-2a may have a thickness greater than that of the first pattern portion 120-1a.

[0285] The second protection pattern 141 - 2 a is arranged to surround the first protection pattern 141 - 1 a .

[0286] In addition, at least a portion of the second protection pattern 141 - 2 a may be in direct contact with a side surface of the 1-1th pad 120 - 11 and a side surface of the 1-2th pad 120 - 12 .

[0287] For example, the 1-1st pad 120-11 includes a plurality of side surfaces. The plurality of side surfaces of the 1-1st pad 120-11 include a 1-1st side surface facing the side surface of the 1-2nd pad 120-12, and a 1-2nd side surface opposite to the 1-1 side surface. Furthermore, the second protection pattern 141-2a may directly contact at least a portion of the 1-2nd side surface of the 1-1st pad 120-11.

[0288] In addition, the 1-2nd pad 120-12 includes a plurality of side surfaces. The plurality of side surfaces of the 1-2nd pad 120-12 include a 2-1st side surface facing the 1-1st side surface of the 1-1st pad 120-11, and a 2-2nd side surface opposite to the 2-1st side surface. And, the second protection pattern 141-2a may directly contact at least a portion of the 2-2nd side surface of the 1-2nd pad 120-12.

[0289] Therefore, the present embodiment can prevent the adhesive member from falling off to the outside of the 1-1 pad 120-11 and the 1-2 pad 120-12 by using the second protection pattern 141-2a, thereby improving reliability. However, although the second protection pattern 141-2a is in direct contact with a portion of the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12, in this structure, when the first semiconductor device is mounted on the 1-1 pad 120-11 and the 1-2 pad 120-12, the second protection pattern 141-2a has a structure that does not overlap with the first semiconductor device in the thickness direction.

[0290] At the same time, if Fig.10d As shown, the second protection pattern 141 - 2 a may contact one side surface of the 1-1th pad 120 - 11 and the 1-2th pad 120 - 12 but not contact the other side surface.

[0291] That is, the second protection pattern 141 - 2 a may include a first portion 141 - 22 a directly contacting at least a portion of the 1 - 2 nd side surface of the 1 - 1 th pad 120 - 11 .

[0292] In addition, the second protection pattern 141 - 2 a may include a second portion 141 - 21 a which is arranged around the first protection pattern 141 - 1 a without contacting the entire side surface of the 1 - 2 th pad 120 - 12 .

[0293] Fig.11a is a plan view of a first region of a circuit board according to a fourth embodiment, and Fig.11b It is along Fig.10a A cross-sectional view taken along the G-G' direction.

[0294] In the following, reference will be made to Fig.11a and Fig.11b The first area of ​​the circuit board according to the fourth embodiment will be described in detail.

[0295] The first pattern portion 120 - 1 is arranged in the first region R1 b of the fourth embodiment. The first pattern portion 120 - 1 includes a 1-1st pad 120 - 11 and a 1-2nd pad 120 - 12 .

[0296] The protection portion 141 b of the protection layer 140 is arranged in the first region R1 b.

[0297] The protection part 141b may have different heights depending on the position. Preferably, the protection part 141b includes a first protection pattern 141-1b adjacent to the first pattern part 120-1 in the first region R1b, and a second protection pattern 141-2b other than the first protection pattern 141-1b.

[0298] For example, the first protection pattern 141-1b may be arranged on at least a portion of the peripheral area of ​​the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12. At this time, the first protection pattern 141-1 of the previous embodiment is arranged to completely surround the peripheral area of ​​the first pad 120-11 and the second pad 120-12. The first protection pattern 141-1 of the previous embodiment is arranged to surround the peripheral area of ​​the first pad 120-11 and the second pad 120-12 in a closed loop shape.

[0299] Different from this, the first protection pattern 141-1b of the fourth embodiment may be arranged on at least a portion of the peripheral area of ​​the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12. That is, the first protection pattern 141-1b may not be arranged on at least a portion of the peripheral area of ​​the first pad 120-11 and the second pad 120-12. For example, the first protection pattern 141-1b may be arranged to surround the peripheral area of ​​the first pad 120-11 and the second pad 120-12 in a closed loop shape.

[0300] That is to say, Fig.11a and Fig.11b As shown, the first protection pattern 141 - 1 b is disposed between the 1-1st pad 120 - 11 and the 1-2nd pad 120 - 12 .

[0301] In addition, the first protection pattern 141 - 1 b may contact at least a portion of a side surface of the 1-1th pad 120 - 11 and a side surface of the 1-2th pad 120 - 12 .

[0302] Meanwhile, the second protection pattern 141 - 2 b may have a thickness greater than that of the first protection pattern 141 - 1 b. In addition, the second protection pattern 141 - 2 b may have a thickness greater than that of the first pattern portion 120 - 1 b.

[0303] The second protection pattern 141 - 2 b is arranged to surround the first protection pattern 141 - 1 b .

[0304] In addition, at least a portion of the second protection pattern 141 - 2 b may directly contact the upper surface and the side surface of the 1-1 th pad 120 - 11 and the upper surface and the side surface of the 1-2 th pad 120 - 12 .

[0305] For example, the 1-1st pad 120-11 includes a plurality of side surfaces. The plurality of side surfaces of the 1-1st pad 120-11 include a 1-1st side surface facing the side surface of the 1-2nd pad 120-12, and a 1-2nd side surface S12 opposite to the 1-1st side surface S11. In addition, the second protection pattern 141-2b may contact the 1-2nd side surface S12 of the 1-1st pad 120-11 and a portion of the upper surface of the 1-1st pad 120-11 adjacent to the 1-2nd side surface S12.

[0306] In addition, the 1-2nd pad 120-12 includes a plurality of side surfaces. The plurality of side surfaces of the 1-2nd pad 120-12 include a 2-1st side surface S21 facing the 1-1st side surface S11 of the 1-1st pad 120-11, and a 2-2nd side surface S22 opposite to the 2-1st side surface S21. In addition, the second protection pattern 141-2b can contact the 2-2nd side surface S22 of the 1-2nd pad 120-12 and a portion of the upper surface of the 1-2nd pad 120-12 adjacent to the 2-2nd side surface S22.

[0307] Therefore, the present embodiment can prevent the adhesive member from falling off to the outside of the 1-1 pad 120-11 and the 1-2 pad 120-12 by using the second protection pattern 141-2b, thereby improving reliability. However, although the second protection pattern 141-2b is in direct contact with a portion of the upper surface and the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12, in this structure, when the first semiconductor device is mounted on the 1-1 pad 120-11 and the 1-2 pad 120-12, the second protection pattern 141-2b has a structure that does not overlap with the first semiconductor device in the thickness direction.

[0308] Fig.12 is a cross-sectional view showing a semiconductor package according to an embodiment, and Fig.13a According to the first embodiment Fig.12 An enlarged view of a first semiconductor device arrangement area.

[0309] The semiconductor package of the present embodiment may have a structure in which a semiconductor device is mounted on at least one circuit board as described above.

[0310] For example, the semiconductor package may include a first connection part 310 disposed on the first pattern part 121 of the circuit layer 120 .

[0311] The first connection portion 310 may have a spherical shape. For example, the cross section of the first connection portion 310 may include a circular shape or a semicircular shape. For example, the cross section of the first connection portion 310 may include a partially circular shape or a completely circular shape. The cross-sectional shape of the first connection portion 310 may be flat on one side and curved on the other side. The first connection portion 310 may be a solder ball, but is not limited thereto.

[0312] Alternatively, the first connection portion 310 may have a hexahedral shape. For example, the cross-section of the first connection portion 310 may include a square shape. The cross-section of the first connection portion 310 may include a rectangular or square shape.

[0313] The first semiconductor device 200 may be mounted on the first connection portion 310. The first semiconductor device 200 may be a passive chip. For example, the first semiconductor device 200 may be a multilayer ceramic capacitor, but is not limited thereto. Meanwhile, although the figure shows that one first semiconductor device 200 is arranged in the semiconductor package, a plurality of first semiconductor devices may be arranged in the first region of the present embodiment.

[0314] In addition, the semiconductor package includes a second connection part 320 disposed on the second pattern part 122 of the circuit layer 120 .

[0315] In addition, the second semiconductor element 400 is arranged on the second connection portion 320. The second chip 420 may be a processor chip. For example, the second semiconductor device 400 may be an application processor (AP) chip of any one of a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller.

[0316] At this time, the second semiconductor device 400 may include a terminal 425 on a lower surface thereof, and the terminal 425 may be electrically connected to the second pattern portion 120 - 2 of the circuit board through the second connection portion 320 .

[0317] Meanwhile, the semiconductor package of the present embodiment may have a plurality of second semiconductor devices arranged on one circuit board at a predetermined distance. For example, the second semiconductor device may include a 2-1 semiconductor device and a 2-2 semiconductor device separated from each other.

[0318] In addition, the 2-1st semiconductor device and the 2-2nd semiconductor device may be different types of application processor (AP) chips.

[0319] Meanwhile, the 2-1st semiconductor device and the 2-2nd semiconductor device may be separated from each other by a predetermined distance on the circuit board. For example, the distance between the 2-1st semiconductor device and the 2-2nd semiconductor device may be 150 μm or less. For example, the distance between the 2-1st semiconductor device and the 2-2nd semiconductor device may be 120 μm or less. For example, the distance between the 2-1st semiconductor device and the 2-2nd semiconductor device may be 100 μm or less.

[0320] Preferably, for example, the distance between the 2-1st semiconductor device and the 2-2nd semiconductor device may have a range of 60 μm to 150 μm. For example, the distance between the 2-1st semiconductor device and the 2-2nd semiconductor device may have a range of 70 μm to 120 μm. For example, the distance between the 2-1st semiconductor device and the 2-2nd semiconductor device may have a range of 80 μm to 110 μm. For example, if the spacing between the 2-1st semiconductor device and the 2-2nd semiconductor device is less than 60 μm, problems may occur in the operational reliability of the 2-1st semiconductor device and the 2-2nd semiconductor device due to interference between the 2-1st semiconductor device and the 2-2nd semiconductor device. For example, if the distance between the 2-1st semiconductor device and the 2-2nd semiconductor device is greater than 150 μm, the signal transmission loss may increase as the distance between the 2-1st semiconductor device and the 2-2nd semiconductor device increases.

[0321] In addition, the semiconductor package further includes a third connection portion 330 disposed in the third region R3. The third connection portion 330 may be disposed on the third pattern portion 120-3 of the circuit layer 120 of the present embodiment. The third connection portion 330 may be a connection portion for connecting with a separate external substrate (eg, a memory substrate).

[0322] In addition, the semiconductor package may include a molding layer 500. The molding layer 500 may be arranged to cover the first semiconductor device 200 and the second chip 400. For example, the molding layer 500 may be an EMC (epoxy molding compound) formed to protect the mounted first semiconductor device 200 and the second chip 400, but is not limited thereto. The molding layer 500 may include an opening that exposes the upper surface of the third connection portion 330. For example, the upper surface of the third connection portion 330 may not be in contact with the molding layer 500. The third connection portion 330 may be a solder ball, or alternatively, may be a columnar bump.

[0323] At this time, the mold layer 500 may have a low dielectric constant to enhance the heat dissipation characteristics. For example, the dielectric constant (Dk) of the mold layer 500 may be 0.2 to 10. For example, the dielectric constant (Dk) of the mold layer 500 may be 0.5 to 8. For example, the dielectric constant (Dk) of the mold layer 500 may be 0.8 to 5. Therefore, in the present embodiment, the mold layer 500 is made to have a low dielectric constant, thereby enhancing the heat dissipation characteristics of the heat generated from the first semiconductor device 200 and the second chip 400.

[0324] Meanwhile, the package substrate may include a fourth connection portion 340 disposed at the lowest side of the circuit board. The fourth connection portion 340 may be used for coupling between the semiconductor package and an external substrate (eg, a main board of an external device).

[0325] At the same time, if Fig.13a As shown, in the present embodiment, the first connection portion 310 is disposed on the 1-1 pad 120 - 11 and the 1-2 pad 120 - 12 of the first pattern portion 120 - 1 .

[0326] At this time, the first connection portion 310 contacts at least a portion of the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12. In addition, the first connection portion 310 does not contact at least a portion of the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12. For example, the first connection portion 310 may contact the upper surface of the first protection pattern 141-1 of the protection layer 140.

[0327] Therefore, the lowermost end of the first connection part 310 in this embodiment may be positioned higher than the upper surface of the insulating layer 110. In addition, the lowermost end of the first connection part 310 in this embodiment is positioned higher than the lower surface of the first pattern part 120-1 but lower than the upper surface of the first pattern part 120-1.

[0328] Therefore, in the present embodiment, the width W10 of the first connection portion 310 may be reduced compared to the comparative example. For example, the width W10 of the first connection portion 310 may be less than 125% of the width of the 1-1 pad 120-11 and the 1-2 pad 120-12 in the second horizontal direction. For example, the width W10 of the first connection portion 310 may be less than 120% of the width of the 1-1 pad 120-11 and the 1-2 pad 120-12 in the second horizontal direction. Therefore, in the present embodiment, the spacing W11 between the first connection portion arranged on the 1-1 pad 120-11 and the first connection portion arranged on the 1-2 pad 120-12 may be increased compared to the comparative example.

[0329] For example, when the spacing between the 1-1 solder pad and the 1-2 solder pad of the comparative example is the same as the spacing between the 1-1 solder pad and the 1-2 solder pad of the present embodiment, the spacing W11 between the multiple first connection portions of the present embodiment can be less than 90%, less than 80% or further less than 70% of the spacing between the multiple first connection portions of the comparative example.

[0330] at the same time, Fig.13a The first connection portion 310 in the embodiment has a shape of a circular solder ball.

[0331] Differently, such as Fig.13b As shown, the first connection portion 310B of the second embodiment may have a solder fillet shape. For example, the first connection portion 310B of the second embodiment may be a paste.

[0332] Furthermore, when the first semiconductor device 200B is mounted while being arranged on the 1-1th pad 120 - 11 and the 1-2th pad 120 - 12 , the first connection portion 310B may form a solder fillet extending to a side surface of the first semiconductor device 200B.

[0333] In addition, when the first connection portion 310B of the second embodiment is applied and the first semiconductor device 200B is installed, the distance between the first pattern portion 120-1 and the first semiconductor device 200B (for example, the distance in the vertical direction or the thickness direction) can be further reduced compared to the first embodiment. At this time, when the first connection portion 310B of the second embodiment is applied, the first protection pattern 141-1 of the protective layer 140 between the 1-1 pad 120-11 and the 1-2 pad 120-12 can be omitted. However, even when the first connection portion 310B of the second embodiment is applied, the following problem may occur: the first connection portion 310B is connected between the insulating layer and the first pattern portion. In addition, a circuit short circuit problem may occur: wherein the 1-1 pad 120-11 and the 1-2 pad 120-12 are electrically connected to each other through the first connection portion 310B. Therefore, in the second embodiment, the first protection pattern 141 - 1 of the protection layer 140 is disposed between the 1-1th pad 120 - 11 and the 1-2th pad 120 - 12 , thereby solving the reliability problem caused by the flow of the first connection portion 310B.

[0334] The circuit board of the present embodiment includes a first region in which a first semiconductor device is arranged.

[0335] In addition, the circuit board includes a 1-1 pad and a 1-2 pad. The 1-1 pad and the 1-2 pad are arranged to overlap with the first semiconductor device in the vertical direction. For example, the 1-1 pad and the 1-2 pad are arranged in the first area of ​​the circuit board. In addition, the present embodiment includes a protective layer. The protective layer includes a first protection pattern, which is arranged between the 1-1 pad and the 1-2 pad and surrounds at least a portion of the side surface of the 1-1 pad and the side surface of the 1-2 pad. In addition, the protective layer includes a second protection pattern arranged around the first protection pattern.

[0336] The first protection pattern contacts at least a portion of the side surfaces of the 1-1st pad and the 1-2nd pad, but does not contact the upper surfaces of the 1-1st pad and the 1-2nd pad. For example, the upper surface of the first protection pattern is positioned lower than the upper surfaces of the 1-1st pad and the 1-2nd pad. Therefore, the present embodiment can reduce the thickness and width of the contact member arranged on the 1-1st pad and the 1-2nd pad by using the first protection pattern.

[0337] For example, the first comparative example has a problem in which the thickness of the contact member increases due to the arrangement of the protective layer, and the second comparative example has a problem in which the expansion degree of the contact member increases due to the non-arrangement of the protective layer, thereby increasing the width of the contact member.

[0338] In contrast, the present embodiment can reduce the expansion degree of the contact member and reduce the width of the contact member by using a combination of the first protection pattern and the second protection pattern. In addition, the present embodiment provides only the first protection pattern in the region vertically overlapping with the first semiconductor device. For example, the second protection pattern does not overlap with the first semiconductor device vertically. Therefore, the present embodiment can prevent the thickness of the contact member from increasing due to the height of the protection layer.

[0339] Therefore, the present embodiment can reduce the thickness of the semiconductor package, thereby achieving miniaturization. In addition, the present embodiment can solve the problem of short circuit between adjacent contact members by reducing the expansion degree of the contact member. As a result, the present embodiment can improve the electrical reliability and product reliability of the semiconductor package. In addition, the present embodiment can solve the problem of circuit short circuit without increasing the spacing between the 1-1 pad and the 1-2 pad, thereby improving the circuit integration.

[0340] In addition, the present embodiment can solve the problem of the adhesive member penetrating between the insulating layer and the pad by using the first protection pattern, thereby further improving product reliability.

[0341] Figures 14 to 21 2 is a cross-sectional view showing a process of manufacturing a circuit board according to an embodiment in order of processes.

[0342] Reference Fig.14 In this embodiment, a first insulating layer 111 is prepared, and the first insulating layer 111 is used as a basis for manufacturing a circuit board. The first insulating layer 111 may be a core layer, but is not limited thereto.

[0343] Next, the present embodiment forms a first through electrode 131 penetrating the first insulating layer 111. And, with the formation of the first through electrode 131, the present embodiment continues the following process: forming the first circuit layer 121 on the upper surface of the first insulating layer 111 and forming the fourth circuit layer 124 on the lower surface of the first insulating layer 111.

[0344] Next, refer to Fig.15 In this embodiment, the second insulating layer 112 is stacked on the upper surface of the first insulating layer 111 , and the fourth insulating layer 114 is stacked on the lower surface of the first insulating layer 111 .

[0345] Thereafter, the present embodiment performs a process of forming the second through electrode 132 and the second circuit layer 122 on the second insulating layer 112. Furthermore, the present embodiment performs a process of forming the fourth through electrode 132 and the fifth circuit layer 125 on the fourth insulating layer 114.

[0346] Next, refer to Fig.16 In this embodiment, the third insulating layer 113 is stacked on the upper surface of the second insulating layer 112 , and the fifth insulating layer 115 is stacked on the lower surface of the fourth insulating layer 114 .

[0347] Thereafter, the present embodiment performs a process of forming a third through electrode 133 and a third circuit layer 123 on the third insulating layer 113. Furthermore, the present embodiment performs a process of forming a fifth through electrode 135 and a sixth circuit layer 126 on the fifth insulating layer 115.

[0348] Next, refer to Fig.17 In this embodiment, a first solder resist layer 140L is formed on the third insulating layer 113, and a second solder resist layer 150L is formed under the fifth insulating layer 115. At this time, the first solder resist layer 140L is arranged to completely cover the third circuit layer 123 on the third insulating layer 113. In addition, the second solder resist layer 150L is arranged to completely cover the sixth circuit layer 126 under the fifth insulating layer 115.

[0349] Next, refer to Fig.18 , the present embodiment may perform the process of partially exposing and curing the first solder resist layer 140L and the second solder resist layer 150L, ​​respectively.

[0350] Therefore, the first solder resist layer 140L according to the embodiment may be subjected to different exposure and curing in each of the first region R1, the second region R2, and the third region R3. Therefore, the first region R1 may include a cured region 140L1 and an uncured region 140L2. In this case, the cured region 140L1 in the first region R1a does not overlap vertically with the third circuit layer 123 arranged in the first region R1a.

[0351] Also, the uncured area 140L2 may be included only in the second region R2. Also, the third region R3 may include the cured area 140L1 and the uncured area 140L2.

[0352] Next, refer to Fig.19 In this embodiment, a thinning process of washing the uncured area 140L2 may be performed. The height of the uncured area 140L2 may be reduced by the thinning process. In this case, the height of the uncured area 140L2 may be freely adjusted by adjusting the thinning process conditions (eg, process time).

[0353] The thinning process may include a process of thinning the uncured region 140L2 using an organic alkaline compound including tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0354] Next, refer to Fig. 20 , in this embodiment, a process of curing the uncured area 140L2 of the first region R1 may be performed. In this case, according to the first embodiment, since the protective layer 140 is not arranged in the second region R2, the uncured area 140L2 in the second region R2 may not be cured. However, since the third protective pattern 142 remains in the second region R2 of the second embodiment, a process of curing the uncured area of ​​the second region R2 may be performed.

[0355] Next, refer to Fig.21 In this embodiment, the process of thinning the uncured area of ​​the second region R2 to remove all the protective layers 140 present in the second region R2 may be continued.

[0356] On the other hand, when the circuit board having the above-mentioned features of the present invention is used in IT equipment or household appliances such as smart phones, server computers, televisions, etc., it can stably perform functions such as signal transmission or power supply. For example, when the circuit board having the features of the present invention performs a semiconductor packaging function, it can be used to safely protect the semiconductor chip from external moisture or pollutants, or alternatively, it can solve the problems of leakage current, electrical short circuit between terminals, and electrical disconnection of terminals provided to the semiconductor chip. In addition, when the function of signal transmission is dominant, the noise problem can be solved. Thus, the circuit board having the above-mentioned features of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and the circuit board applying the present invention can achieve functional unification or technical linkage with each other.

[0357] When the circuit board having the above-mentioned features of the present invention is used in a transport device such as a vehicle, the problem of signal distortion transmitted to the transport device can be solved, or alternatively, the safety of the transport device can be further improved by safely protecting the semiconductor chip controlling the transport device from external influences and solving the problem of leakage current or electrical disconnection between terminals or electrical disconnection of terminals provided to the semiconductor chip. Therefore, the transport device and the circuit board to which the present invention is applied can achieve functional unification or technical linkage with each other.

[0358] The characteristics, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, the characteristics, structures and effects shown in each embodiment can be combined or even modified relative to other embodiments by a person skilled in the art of the embodiment. Therefore, it should be understood that the contents related to such combination and such modification are also included in the scope of the embodiment.

[0359] The above description focuses on the embodiments, but it is merely illustrative and not limiting. It will be appreciated by those skilled in the art that various modifications and applications not described above are possible without departing from the essential features of the embodiments. For example, each component specifically shown in the embodiments may be modified and implemented. In addition, it should be explained that the differences associated with such modifications and applications are all included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: Insulation layer; a circuit layer, the circuit layer being arranged on the insulating layer; as well as a protective layer, the protective layer being arranged on the insulating layer; The circuit layer includes a 1-1 pad and a 1-2 pad spaced apart from each other in a first horizontal direction, Wherein, the protective layer comprises: a first protection pattern disposed between the 1-1 pad and the 1-2 pad and surrounding at least a portion of a side surface of the 1-1 pad and a side surface of the 1-2 pad; and a second protection pattern, the second protection pattern being arranged to surround the first protection pattern, wherein the upper surface of the first protection pattern is positioned lower than the upper surface of the 1-1 pad and the upper surface of the 1-2 pad; wherein an upper surface of the second protection pattern is positioned higher than an upper surface of the 1-1 pad and an upper surface of the 1-2 pad; and Each of the 1-1 pad and the 1-2 pad has a different width in the first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction.

2. The circuit board according to claim 1, wherein: The thickness of the first protection pattern satisfies a range of 40% to 90% of a thickness of at least one of the 1-1 pad and the 1-2 pad.

3. The circuit board according to claim 1 or 2, wherein: A thickness of at least one of the 1-1 pad and the 1-2 pad satisfies a range of 10 μm to 25 μm; and The thickness of the first protection pattern is within a range of 3 μm to 21 μm.

4. The circuit board according to claim 1 or 2, wherein: A vertical distance between an upper surface of at least one of the 1-1 pad and the 1-2 pad and an upper surface of the first protection pattern satisfies a range of 3 μm to 10 μm.

5. The circuit board according to claim 4, wherein: At least one of an upper surface of the 1-1 pad and an upper surface of the 1-2 pad includes a curved surface, and The vertical distance is a vertical distance from the uppermost surface of at least one of the 1-1 pad and the 1-2 pad to the uppermost surface of the first protection pattern.

6. The circuit board according to claim 3, wherein: The thickness of the second protection pattern satisfies the range of 17 μm to 45 μm.

7. The circuit board according to claim 1, wherein: A width of each of the 1-1 pad and the 1-2 pad in the second horizontal direction is within a range of 125% to 220% of a width of each of the 1-1 pad and the 1-2 pad in the first horizontal direction.

8. The circuit board according to claim 7, wherein: A spacing between the 1-1 pad and the 1-2 pad satisfies a range of 70% to 120% of a width of each of the 1-1 pad and the 1-2 pad in the first horizontal direction.

9. The circuit board according to claim 1, wherein: An inner wall of the second protection pattern is spaced apart from a side surface of at least one of the 1-1 pad and the 1-2 pad by a distance of 15 μm to 23 μm.

10. The circuit board according to claim 1, wherein: The first protection pattern is disposed to partially surround a side surface of the 1-1 pad and a side surface of the 1-2 pad, and At least a portion of the second protection pattern is in contact with a side surface of the 1-1 pad or a side surface of the 1-2 pad.

Images