Self-aligned structure, preparation method thereof and semiconductor device

Abstract

The invention relates to a self-alignment structure, a preparation method thereof and a semiconductor device. The preparation method of the self-aligned structure comprises the following steps: depositing a self-aligned functional film on the first region of the substrate through a selective atomic layer deposition process; and then, through a plasma atomic layer etching process, carrying out etching treatment on a second region, except for the first region, of the substrate. Selective atomic layer deposition and post-processing plasma atomic layer etching are innovatively combined, the purposes of removing ASD defects, improving ASD selectivity and preparing a self-alignment structure without a photoetching process are achieved, and the method has positive significance on preparation of a semiconductor device structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a self-alignment structure and a preparation method thereof, and a semiconductor device. Background Art

[0002] With the continuous development of IC (integrated circuit) technology, the size of transistors and the complexity of devices are increasing, requiring the manufacturing process to have higher precision and complexity, and traditional manufacturing technology is facing challenges. Self-aligned structures are mainly used in the manufacturing process of various types of semiconductor devices, such as transistors, capacitors, contact points, etc., aiming to improve the performance of devices and the accuracy of manufacturing. The manufacture of self-aligned structures is one of the key technologies in the semiconductor field. Self-aligned technology realizes automatic alignment of components by utilizing the characteristics of the material itself or specific manufacturing process steps, thereby reducing alignment errors and improving device performance and manufacturing yield and stability.

[0003] Self-aligned structure manufacturing technology was first used in traditional CMOS (complementary metal oxide semiconductor) processes to reduce alignment errors in the manufacturing process and improve device manufacturing accuracy. In recent years, as manufacturing processes have developed towards smaller sizes, traditional manufacturing technologies have faced greater challenges. Self-aligned technology helps achieve higher integration and performance, and is particularly important in advanced processes. At present, self-aligned structures are not only used in traditional CMOS processes, but are also widely used in the manufacture of new structures such as FinFET (fin field effect transistor) to support more advanced electronic device designs.

[0004] In traditional technology, self-aligned structures need to rely on photolithography. Photolithography is a key process used in semiconductor manufacturing to transfer designed patterns to the surface of silicon wafers or other semiconductor materials. Its basic principle is to use optical exposure and chemical development processes to accurately copy the fine structures in integrated circuit design to the surface of semiconductor materials. However, with the reduction of critical dimensions (CD) and the adoption of three-dimensional structures, photolithography must continue to improve resolution to achieve smaller features. Current optical exposure technology has approached its physical limits, so it is difficult to achieve the generation of higher-precision structures. For complex three-dimensional structures, multi-layer exposure technology is often required to achieve the required structure, and the process is relatively complicated. In addition, the cost of photolithography equipment and photolithography materials is very high, especially for advanced processes and large-scale production. These costs limit the popularity and widespread application of photolithography. Summary of the invention

[0005] Based on this, it is necessary to provide a self-aligned structure and a preparation method thereof, and a semiconductor device to solve the problem that the self-aligned structure needs to rely on photolithography technology.

[0006] One of the purposes of the present invention is to provide a method for preparing a self-aligned structure, the scheme is as follows:

[0007] A method for preparing a self-aligned structure comprises the following steps:

[0008] Depositing a self-aligned functional film on a first region of the substrate by a selective atomic layer deposition process;

[0009] Afterwards, a second region outside the first region of the substrate is etched by a plasma atomic layer etching process.

[0010] In one of the embodiments, the material of the self-aligned functional film includes one or more of aluminum oxide, gallium oxide, silicon dioxide, gallium nitride, silicon nitride, tungsten, ruthenium, platinum, chromium, and silicon.

[0011] In one embodiment, the thickness of the self-aligned functional film is 0.1-10 nm.

[0012] In one embodiment, before forming the self-aligned functional film, the method for preparing the self-aligned structure further comprises the following steps:

[0013] A self-assembled monolayer is formed on the second region, and the self-assembled monolayer can prevent the self-aligned functional film from being deposited on the second region.

[0014] In one embodiment, the substrate includes a semiconductor substrate and a patterned metal layer disposed on the second region of the semiconductor substrate;

[0015] The step of forming the self-assembled monolayer on the second region comprises:

[0016] The substrate is immersed in a solution containing the self-assembled monolayer, so that the self-assembled monolayer is self-assembled on the patterned metal layer.

[0017] In one embodiment, before performing the plasma atomic layer etching process, the method for preparing the self-aligned structure further includes the following steps:

[0018] The substrate is subjected to hydrogen plasma treatment.

[0019] In one embodiment, the plasma atomic layer etching process uses inert gas plasma for etching.

[0020] In one embodiment, the plasma atomic layer etching process includes the following steps:

[0021] In the first process, a modified gas is introduced to perform surface modification to reduce the binding energy of the substrate;

[0022] In the second process, the first purge gas is introduced for purge;

[0023] In the third process, an inert gas plasma is introduced for etching;

[0024] In the fourth step, the second purge gas is introduced for purge.

[0025] In one of the embodiments, in the third process, the flow rate of the inert gas plasma is 20-200 sccm, and the duration is 1-120 s.

[0026] Another object of the present invention is to provide a self-aligned structure, which is prepared by the preparation method described in any of the above embodiments.

[0027] Another object of the present invention is to provide a semiconductor device comprising the self-aligned structure.

[0028] Compared with the conventional technology, the self-aligned structure and the preparation method thereof, and the semiconductor device have the following beneficial effects:

[0029] The above-mentioned method for preparing the self-aligned structure selectively deposits a self-aligned functional film through a selective atomic layer deposition process (ASD), and innovatively combines the selective atomic layer deposition with post-processing plasma atomic layer etching (ALE) to achieve the purpose of removing ASD defects and improving the selectivity of ASD. It can prepare the self-aligned structure without the need for a photolithography process, which has positive significance for the preparation of semiconductor device structures.

[0030] The ASD process can achieve the selective deposition of thin films on different semiconductor substrates. For complex surface structures or nano-level preparation requirements, especially for large-sized or non-flat substrates, ASD can ensure the uniformity of the grown film and achieve uniform nano-level film preparation. The process is relatively simple and the cost is low. The post-processing uses the ALE process. The ALE process can remove defects in non-growth areas at the atomic level, and its etching is self-limiting, so it will not cause damage to the film structure. Secondly, since the defect removal is atomic-level peeling, nano-level precision control can be achieved without increasing the surface roughness of the film.

[0031] The semiconductor device has the self-aligned structure of any of the above embodiments, and thus can achieve corresponding beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 (a) to (e) are schematic flow diagrams of a method for preparing a self-aligned structure according to an embodiment;

[0033] Figure 2This is a broad spectrum of the non-self-aligned functional film growth region before the plasma atomic layer etching process in Example 1;

[0034] Figure 3 This is a broad spectrum of the non-self-aligned functional film growth region after the plasma atomic layer etching process in Example 1. DETAILED DESCRIPTION

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0037] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0039] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] The invention provides a method for preparing a self-aligning structure.

[0041] A method for preparing a self-aligned structure according to an embodiment of the present invention comprises the following steps:

[0042] Depositing a self-aligned functional film on a first area of ​​the substrate by a selective atomic layer deposition (ASD) process;

[0043] Afterwards, a plasma atomic layer etching (ALE) process is used to etch the second region of the substrate outside the first region.

[0044] The above-mentioned method for preparing the self-aligned structure selectively deposits a self-aligned functional film through a selective atomic layer deposition process (ASD), and innovatively combines the selective atomic layer deposition with post-processing plasma atomic layer etching (ALE) to achieve the purpose of removing ASD defects and improving the selectivity of ASD. It can prepare the self-aligned structure without the need for a photolithography process, which has positive significance for the preparation of semiconductor device structures.

[0045] The ASD process can achieve the selective deposition of thin films on different semiconductor substrates. For complex surface structures or nano-level preparation requirements, especially for large-sized or non-flat substrates, ASD can ensure the uniformity of the grown film and achieve uniform nano-level film preparation. The process is relatively simple and the cost is low. The post-processing uses the ALE process. The ALE process can remove defects in non-growth areas at the atomic level, and its etching is self-limiting, so it will not cause damage to the film structure. Secondly, since the defect removal is atomic-level peeling, nano-level precision control can be achieved without increasing the surface roughness of the film.

[0046] The substrate includes a semiconductor substrate and a patterned metal layer disposed on the second region of the semiconductor substrate, wherein the semiconductor substrate is, for example, a silicon wafer, and the patterned metal layer is, for example, a copper (Cu) layer, but is not limited thereto.

[0047] Optionally, the material of the self-aligned functional film can be but is not limited to metal oxides such as aluminum oxide and gallium oxide; common semiconductor compounds such as silicon dioxide, gallium nitride, silicon nitride; metal elements such as tungsten, ruthenium, platinum, chromium; and non-metal elements such as silicon.

[0048] In some of the examples, the thickness of the self-aligned functional film is 0.1 nm to 10 nm, for example, 0.5 nm, 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, etc.

[0049] In some of the examples, before forming the self-aligned functional film, the method for preparing the self-aligned structure further includes the following steps:

[0050] A self-assembled monolayer is formed on the second region, and the self-assembled monolayer can prevent the self-aligned functional film from being deposited on the second region.

[0051] In some examples, the self-assembled monolayer includes, but is not limited to, one or more of n-octadecanethiol (ODT), n-dodecylthiol (DDT), and the like.

[0052] The above-mentioned thiol has an alkyl group and a thiol group (-SH), wherein the thiol group is more likely to combine with the surface of the metal, thereby self-assembling on the patterned metal layer, and the alkyl group on the side away from the patterned metal layer can prevent the self-aligned functional film from being deposited on the second area. For example, the material of the alignment functional film is aluminum oxide, and the process gas for depositing the alignment functional film is trimethylaluminum, which mainly combines with the hydroxyl group on the surface of the substrate to form aluminum oxide. Before depositing aluminum oxide, a self-assembled monolayer is formed on the patterned metal layer on the second area. Due to the presence of the alkyl group in the self-assembled monolayer, trimethylaluminum cannot be combined, thereby preventing the self-aligned functional film from being deposited on the second area.

[0053] In some examples, the step of forming a self-assembled monolayer on the second region includes:

[0054] The substrate is immersed in a solution containing the self-assembled monolayer, so that the self-assembled monolayer is self-assembled on the patterned metal layer.

[0055] In some of the examples, the temperature of the solution containing the self-assembled monolayer is 75-85°C.

[0056] In some of these examples, the substrate is soaked for a period of 1 to 24 hours.

[0057] In some examples, after the substrate is soaked, the soaked substrate is cooled to room temperature and then cleaned to remove excess self-assembled monolayers, for example, using anhydrous ethanol. After the cleaning, the substrate is dried. The drying process can be blown dry with nitrogen, for example.

[0058] In some of the examples, before performing the plasma atomic layer etching process, the method for preparing the self-aligned structure further includes the following steps:

[0059] The substrate is subjected to hydrogen plasma treatment.

[0060] The self-assembled monolayer remaining on the substrate surface is removed by hydrogen plasma treatment to prevent it from affecting subsequent reactions.

[0061] In some of the examples, the power of the hydrogen plasma treatment is 100-300 W. In some of the examples, the time of the hydrogen plasma treatment is 5-15 minutes.

[0062] In some examples, the plasma atomic layer etching process uses an inert gas plasma for etching. For example, the inert gas plasma can be, but is not limited to, Ar plasma.

[0063] In some examples, the plasma atomic layer etching process includes the following processes:

[0064] In the first process, a modifying gas is introduced to perform surface modification to reduce the binding energy of the substrate;

[0065] In the second process, the first purge gas is introduced for purge;

[0066] In the third process, an inert gas plasma is introduced for etching;

[0067] In the fourth step, the second purge gas is introduced for purge.

[0068] The first process, the second process, the third process and the fourth process can be repeated in sequence, and the required number of cycles is determined according to the thickness of the defect layer in the non-growth area to be removed.

[0069] In the first process, for a substrate made of aluminum oxide, the modifying gas is preferably BCl3, HF, etc. For a substrate made of silicon dioxide, the modifying gas is preferably at least one of C4F8, CF4, CHF3, etc. For a substrate made of silicon nitride, the modifying gas is preferably at least one of C4F8, CHF3, etc. For a substrate made of gallium nitride, the modifying gas is preferably at least one of O2, Cl2, etc. For a substrate made of a single metal, the modifying gas is preferably Cl2.

[0070] Optionally, in the first process, a carrier gas may be introduced, and the carrier gas may be, but is not limited to, argon.

[0071] In some of the examples, in the first process, the flow rate of the introduced modifying gas is 20-100 sccm, the flow rate of the carrier gas is 0-50 sccm, and the duration is 1-30 s.

[0072] Optionally, in the second process, the first purge gas may be, but is not limited to, argon.

[0073] In some examples, in the second process, the flow rate of the first purge gas is 20-200 sccm, and the duration is 15-60 s.

[0074] In some of the examples, in the third process, the flow rate of the introduced inert gas plasma is 20-200 sccm, and the duration is 1-120 s.

[0075] Optionally, in the fourth process, the second purge gas may be, but is not limited to, argon gas.

[0076] In some of the examples, in the fourth process, the flow rate of the second purge gas is 20-200 sccm, and the duration is 15-60 s.

[0077] The first process, the second process, the third process and the fourth process can be repeated in sequence, and the required number of cycles is determined according to the thickness of the defect layer in the non-growth area to be removed.

[0078] In some of these examples, during a plasma atomic layer etching process, the pressure in the process chamber is 20-50 mTorr.

[0079] Figure 1 The flowchart of a method for preparing a self-aligned structure according to an embodiment is shown.

[0080] like Figure 1 As shown in (a), a substrate 100 is provided, and the substrate 100 includes a semiconductor substrate 110 and a patterned metal layer 120. The patterned metal layer 120 is disposed on the semiconductor substrate 110 and located on the second region 102, and the first region 101 is outside the second region 102.

[0081] like Figure 1 As shown in (b), the substrate 100 is immersed in a solution containing a self-assembled monolayer, so that the self-assembled monolayer 200 is self-assembled on the patterned metal layer.

[0082] like Figure 1As shown in (c), a self-aligned functional film 300 is deposited on the substrate 100 by a selective atomic layer deposition process. Due to the presence of the self-assembled monolayer 200 on the second region, the self-aligned functional film 300 is blocked from being deposited on the second region 102, so that the self-aligned functional film 300 is deposited on the first region 101.

[0083] like Figure 1 As shown in (d), the immersed substrate 100 is cooled to room temperature and then cleaned to remove the excess self-assembled monolayer 200. At this time, a defective layer 400 caused by the selective atomic layer deposition process still exists on the substrate.

[0084] like Figure 1 As shown in (e), the substrate 100 is etched by a plasma atomic layer etching process to remove the defective layer 400 on the second region 102 .

[0085] The above-mentioned method for preparing the self-aligned structure innovatively combines selective atomic layer deposition (ASD) with post-processing plasma atomic layer etching (ALE) to achieve the purpose of removing ASD defects, improving the selectivity of ASD, and preparing the self-aligned structure, which has positive significance for the preparation of semiconductor device structures.

[0086] The ASD process can achieve the selective deposition of thin films on different semiconductor substrates. For complex surface structures or nano-level preparation requirements, especially for large-sized or non-flat substrates, ASD can ensure the uniformity of the grown film and achieve uniform nano-level film preparation. The process is relatively simple and the cost is low. The post-processing uses the ALE process. The ALE process can remove defects in non-growth areas at the atomic level, and its etching is self-limiting, so it will not cause damage to the film structure. Secondly, since the defect removal is atomic-level peeling, nano-level precision control can be achieved without increasing the surface roughness of the film.

[0087] By precisely controlling the process parameters of plasma atomic layer etching, such as gas type, pressure, power, etc., atomic-level etching can be achieved without damaging the original structure. The prepared structure growth area has low roughness, good uniformity, and good bonding with the semiconductor substrate, which makes it possible to study its dielectric properties.

[0088] Furthermore, the present invention also provides a self-aligned structure. The self-aligned structure is prepared by any of the above-mentioned preparation methods.

[0089] Furthermore, the present invention also provides a semiconductor device, wherein the semiconductor device comprises any of the above-mentioned self-aligned structures.

[0090] Optionally, the semiconductor device may be, but is not limited to, a CMOS device, a FinFET (Fin Field Effect Transistor), or the like.

[0091] The following specific examples are provided to further illustrate the present invention, but the present invention is not limited to the specific implementation methods. The present invention provides the following specific examples for a better understanding of the present invention, and does not limit the scope of protection of the present invention.

[0092] Example 1

[0093] The method for preparing the self-aligned structure provided in this embodiment comprises the following steps:

[0094] Step 1, providing a substrate, the substrate comprising a semiconductor substrate and a patterned metal layer disposed on the semiconductor substrate, the patterned metal layer being a patterned array of copper.

[0095] Step 2: Soak the substrate in an 80°C ODT (n-octadecyl mercaptan) solution for 1 hour. The thiol group of ODT allows it to self-assemble on the patterned metal layer to form a self-assembled monolayer. The other end of ODT is a methyl group (-CH3), which can prevent the subsequent deposition of trimethylaluminum from binding to its surface.

[0096] Step 3, the immersed substrate is cooled to room temperature, rinsed with anhydrous ethanol to wash away excess ODT, and nitrogen is blown with an air gun to dry the ethanol on the surface of the substrate.

[0097] Step 4, placing the substrate with ODT attached in the chamber of the atomic layer deposition equipment (Jiangsu Minard Micro-Nano Technology Co., Ltd., model MNT-DP100-L2S2G2) for selective atomic layer deposition process. The reaction temperature of the chamber is set to 130°C, and the pipeline temperature is 120°C. The precursors trimethylaluminum and deionized water are introduced in sequence to deposit an aluminum oxide film. The deposition time of trimethylaluminum and deionized water is 0.5s and 0.2s, respectively, and the purge time is 15s and 20s, respectively. In order to remove unreacted precursors, nitrogen is used as a purge gas. The number of deposition cycles is 100~150 cycles until the film thickness is 10nm, and a self-aligned functional film deposited on the first area of ​​the substrate is obtained.

[0098] Step 5: In a tube furnace, the grown substrate is treated with hydrogen plasma to remove the ODT on the surface to prevent it from affecting subsequent reactions. The treatment power is 300 W and the treatment time is 10 minutes.

[0099] Step 6: Transfer the substrate with the self-aligned functional film deposited to the ALE reaction chamber for plasma atomic layer etching post-processing. Plasma etching uses an Oxford Instruments "PlasmaPro100" etching device, and ICPRF and table RF are used to jointly adjust the energy of the plasma. ICP RF is the power for generating plasma, and table RF is used to adjust the bias voltage to increase the energy applied by the plasma to the film surface.

[0100] The parameters of the ALE process are as follows:

[0101] During the experiment, the external chamber was set at 60°C and the chuck (sample stage) temperature was maintained at 20°C. The chamber pressure was set at 40mTorr.

[0102] In the first step, 50 sccm of BCl3 and 50 sccm of argon were introduced for modification, and the modification time was 5 s.

[0103] In the second step, 50 sccm of argon was introduced to remove excess unadsorbed BCl3, and the purge time was 15 s.

[0104] In the third step, 50 sccm of inert gas plasma was introduced for etching, and the etching time was 30 s.

[0105] In the fourth step, 50 sccm of argon gas was introduced to remove excess unreacted inert gas plasma, and the purge time was 30 s.

[0106] The first to fourth steps are one cycle, and the number of cycles required for the reaction is determined according to the thickness of the non-growth area to be removed. After the reaction is completed, the substrate is taken out to obtain a substrate with defects in the non-growth area removed.

[0107] Figure 2 This is a broad spectrum of the non-growth area before etching. The peak of Cu is between 915 and 920, which is the semiconductor substrate material in the non-growth area. The peak of Al is between 1350 and 1400, which is the aluminum oxide film that needs to be grown. Figure 2 It can be seen that a peak of aluminum element appears in the non-growth zone, indicating that there are aluminum oxide defects in the non-growth zone.

[0108] Figure 3 This is a broad spectrum of the non-growth area after etching. Figure 2 It can be seen that there is no peak of Al element in the non-growth zone, indicating that the defects in the non-growth zone have been removed.

[0109] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be based on the attached claims, and the description can be used to interpret the content of the claims.

Claims

1. A method for preparing a self-aligned structure, It is characterized in that The following steps are involved: Depositing a self-aligned functional film on a first region of the substrate by a selective atomic layer deposition process; Afterwards, a second region outside the first region of the substrate is etched by a plasma atomic layer etching process.

2. The method for preparing the self-aligned structure according to claim 1, It is characterized in that The preparation method meets at least one of the following characteristics (1) to (2): (1) The material of the self-aligned functional film includes one or more of aluminum oxide, gallium oxide, silicon dioxide, gallium nitride, silicon nitride, tungsten, ruthenium, platinum, chromium, and silicon; (2) The thickness of the self-aligned functional film is 0.1 nm to 10 nm.

3. The method for preparing the self-aligned structure according to claim 1, It is characterized in that Before forming the self-aligned functional film, the method for preparing the self-aligned structure further comprises the following steps: A self-assembled monolayer is formed on the second region, and the self-assembled monolayer can prevent the self-aligned functional film from being deposited on the second region.

4. The method for preparing the self-aligned structure according to claim 3, It is characterized in that The substrate comprises a semiconductor substrate and a patterned metal layer disposed on the second region of the semiconductor substrate; The step of forming the self-assembled monolayer on the second region comprises: The substrate is immersed in a solution containing the self-assembled monolayer, so that the self-assembled monolayer is self-assembled on the patterned metal layer.

5. The method for preparing the self-aligned structure according to claim 1, It is characterized in that Before performing the plasma atomic layer etching process, the method for preparing the self-aligned structure further includes the following steps: The substrate is subjected to hydrogen plasma treatment.

6. The method for preparing a self-aligned structure according to any one of claims 1 to 5, It is characterized in that The plasma atomic layer etching process uses inert gas plasma for etching.

7. The method for preparing the self-aligned structure according to claim 6, It is characterized in that The plasma atomic layer etching process includes the following processes: In the first process, a modifying gas is introduced to perform surface modification to reduce the binding energy of the substrate; In the second process, the first purge gas is introduced for purge; In the third process, an inert gas plasma is introduced for etching; In the fourth step, the second purge gas is introduced for purge.

8. The method for preparing the self-aligned structure according to claim 7, It is characterized in that In the third process, the flow rate of the inert gas plasma is 20-200 sccm, and the duration is 1-120 s.

9. A self-aligned structure, It is characterized in that It is prepared by the preparation method according to any one of claims 1 to 8.

10. A semiconductor device, It is characterized in that The self-aligned structure according to claim 9 is included.

Images