Nanoscale silicon through hole and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a nanoscale silicon through hole and a preparation method thereof, and the method comprises the following steps: providing a semiconductor substrate; preparing a nano-scale groove on the surface of the semiconductor substrate by adopting a Bosch process; etching the side wall of the nanoscale groove by adopting an atomic layer etching process to form a smooth side wall; depositing a dielectric layer by adopting an atomic layer deposition process; depositing a barrier layer by adopting an atomic layer deposition process; and depositing a metal layer by adopting an atomic layer deposition process. According to the invention, a Bosch process is combined with an accurate and controllable atomic layer etching (ALE) technology and an atomic layer deposition (ALD) technology. The surface roughness of the side wall is reduced through the ALE technology, scale generated by the Bosch technology is eliminated, so that the smooth side wall is obtained, then the dielectric layer and the metal layer are completely filled through the ALD technology, and finally the back power supply network with excellent performance is constructed. According to the method, the problem of uniform filling of scale and nano-TSV (Through Silicon Via) caused by the Bosch process is effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a nano-scale through silicon via and a preparation method thereof. Background Art

[0002] With the continuous pursuit of higher integration, smaller size and lower power consumption, the combination of 3D integration and back-side power supply technology has become a key technology to promote its development. Among them, back-side power supply technology can effectively solve the resource crowding problem between the signal network and the power supply network faced by traditional front-side power supply technology, with lower voltage drop and signal interference, higher chip utilization and faster power transmission. Through Silicon Via (TSV) etching is a key structure to achieve back-side power supply network connection. To achieve 3D integration and back-side power supply, high-quality vertical interconnection channels must be formed inside the chip, and nano-TSV, as a nanoscale vertical through-hole technology, can meet its efficient signal interconnection requirements. Therefore, how to prepare nano-TSV with excellent performance has become a key technology development direction to achieve higher integration interconnection.

[0003] At present, the Bosch plasma etching process with high selectivity and high anisotropy is often used to make high aspect ratio structures, which is mainly achieved by depositing a thin film on the lateral sidewalls of the etching to prevent or weaken the lateral etching. In this process, etching and passivation are carried out alternately. The etching gas (such as SF6) is used for physical and chemical etching, while the passivation gas (such as C4F8) forms a fluorinated carbon polymer in the plasma and is deposited on the silicon surface to prevent the reaction of fluoride ions with silicon, thereby protecting the sidewalls. Etching and passivation are switched in a short period to ensure that etching is carried out along the depth direction and reduce lateral etching. However, alternating deposition and cycling steps usually result in large-area scalloped sidewalls and large-area mask depressions, which may affect the conformal filling of the dielectric and metal layers, leading to uneven filling and the introduction of voids. It will also cause greater through-hole leakage current and increase the possibility of early dielectric breakdown under electrical and thermal cycles. In addition, the undulating structure of the sidewalls will also lead to uneven stress distribution, causing cracks, triggering atomic migration of the metal layer, and increasing conductor loss, thereby affecting the transmission speed of high-frequency signals. Therefore, smooth TSV sidewalls are very important for reliable signal interconnection. At the same time, due to the high aspect ratio, nanoscale through holes are prone to entrance blockage and incomplete bottom filling, resulting in keyhole problems.

[0004] There have been some research advances in eliminating the scallops generated by the Bosch process, but there are some defects. For example, by optimizing the Bosch process parameters, that is, shortening the etching and deposition process reaction time, the generation of scallop profiles can be reduced, but this places higher requirements on the switching time of the mass flow controller. In addition, a post-planarization process can be introduced after the Bosch process, such as introducing KOH or KOH:IPA wet etchants to chemically polish the sidewalls, but wet etching depends on the crystal orientation; and focused ion beam (FIB) milling has the problem of ion-induced lattice damage and re-deposition; using hydrogen annealing, or repeating thermal oxidation and oxide stripping steps can reduce the sidewall roughness, but there is a high thermal budget. At the same time, filling high aspect ratio trench structures usually has the problem of incomplete filling and keyhole formation.

[0005] In view of this, the present invention is proposed. Summary of the invention

[0006] The object of the present invention is to provide a method for preparing a nano-scale through silicon via, which effectively solves the problem of scallop caused by the Bosch process and the problem of uniform filling of the nano-scale through silicon via.

[0007] In a first aspect, the present invention provides a method for preparing a nanoscale through silicon via, comprising the following steps:

[0008] S1. providing a semiconductor substrate;

[0009] S2, using Bosch process to prepare nano-scale grooves on the surface of semiconductor substrate;

[0010] S3, etching the sidewalls of the nanoscale grooves using an atomic layer etching process to form smooth sidewalls;

[0011] S4, depositing a dielectric layer using an atomic layer deposition process;

[0012] S5, depositing a barrier layer using an atomic layer deposition process;

[0013] S6. Depositing a metal layer using an atomic layer deposition process.

[0014] As a preferred embodiment of the present technical solution, step S1 includes forming a window defining a through silicon via on a semiconductor substrate by using a hard mask or a photoresist as a mask.

[0015] For example, when a window defining a through silicon via is formed on a semiconductor substrate by means of a hard mask, a plasma enhanced chemical vapor deposition method can be used to grow silicon dioxide on the surface of the semiconductor substrate as a first protective layer to prevent damage to devices formed on the semiconductor substrate during subsequent etching, and to serve as an insulating layer for an interconnect structure; a layer of photoresist is then coated on the first protective layer, and then the designed pattern is transferred to the photoresist through the photoresist, and after the photoresist undergoes steps such as exposure and development, a patterned second protective layer is formed; finally, the patterned second protective layer is used as a mask to wet or dry etch the first protective layer to form a window on the semiconductor substrate to define the position of the through silicon via on the semiconductor substrate.

[0016] For example, when forming a window defining a through silicon via on a semiconductor substrate using photoresist as a mask, it is first necessary to deposit a layer of photoresist on the semiconductor substrate as a mask, and then patterning is achieved through exposure, development and other processes to form a window defining the through silicon via on the semiconductor substrate.

[0017] The etching resistance of photoresist is slightly worse than that of hard mask, but the process steps are simple. Therefore, in actual use, the appropriate process method can be selected according to the size of the nanoTSV to be manufactured.

[0018] The material of the semiconductor substrate of the present invention includes any one of silicon, germanium, silicon germanium or silicon on insulating substrate (Silicon oninsulator, SOI).

[0019] As a preferred embodiment of the present technical solution, in step S2, when the Bosch process is performed, etching gas and passivation gas are alternately introduced into the reaction chamber to perform etching and deposition to form nano-scale grooves on the semiconductor substrate.

[0020] Specifically, in the Bosch process, etching and passivation are carried out alternately. When the semiconductor substrate is a silicon base material, the etching gas (such as SF6) is used for physical and chemical etching, and the passivation gas (such as C4F8) can form a carbon fluorine polymer in the plasma, which is then deposited on the silicon surface to prevent fluorine ions and free radicals from reacting with silicon, thereby protecting the side walls. Etching and passivation are switched in a short cycle to ensure that etching is carried out along the depth direction and reduce lateral etching.

[0021] As a preferred embodiment of the present technical solution, in step S3, the atomic layer etching process includes any one of thermal atomic layer etching and plasma enhanced atomic layer etching.

[0022] Atomic layer etching (ALE) technology is a high-precision, controllable nanoscale processing technology that can etch in a self-limiting manner, remove materials layer by layer through surface modification and surface removal, and precisely control the duration and gas pressure of the etching and repair steps to precisely control the etching depth, thereby potentially reducing the surface roughness.

[0023] Atomic layer etching technology can be divided into thermal atomic layer etching (thermal ALE) and plasma enhanced atomic layer etching (PEALE) according to energy. Thermal ALE performs desorption at a relatively high temperature, is isotropic, and can cause extremely low damage; while PEALE bombards the modified surface with plasma, is anisotropic, and can be performed at a lower temperature than thermal ALE. In actual use, a specific atomic etching technology route can be selected according to the different semiconductor substrate materials and the requirements for the stability and accuracy of the atomic layer etching technology.

[0024] For example, when the semiconductor substrate is a silicon base material, when the thermal atomic layer etching technology is used, the silicon surface is first oxidized by introducing oxygen to generate SiO2, and then TMA (trimethylaluminum) gas is used to react with SiO2 to convert SiO2 into Al2O3, and further HF (hydrogen fluoride) is used to fluorinate Al2O3 into volatile AlF3 (aluminum fluoride), and then trimethylaluminum ligand exchange is performed to remove AlF3 from the surface, and the reaction product is volatilized to complete an etching cycle;

[0025] After one or more etching cycles, the scallops on the sidewalls of the nano-scale trenches are eliminated to form smooth sidewalls.

[0026] For example, when the semiconductor substrate is a silicon base material, when the plasma enhanced atomic layer etching technology is used, the silicon base oxide layer is first removed by CF4 / Ar plasma, and the silicon is further chlorinated by Cl2 plasma to generate chlorosilane, and then the generated chlorosilane is removed from the surface by Ar plasma, and a purge step is inserted between the chlorination and removal steps to eliminate any unnecessary free radicals and ions, prevent the free radicals and ions from recombining on the substrate surface to form by-products, and complete an etching cycle;

[0027] After one or more etching cycles, the scallops on the sidewalls of the nano-scale trenches are eliminated to form smooth sidewalls.

[0028] Atomic layer deposition (ALD) technology alternately passes gaseous precursor pulses into the reaction chamber, chemically adsorbs and reacts on the substrate surface to form a deposited film. Due to the characteristics of self-limited saturation of the surface, ALD technology can achieve precise control of atomic-level thickness, and can achieve good coverage on the surface of complex structures with high aspect ratios, ensuring the formation of a film of uniform thickness. Therefore, in the present invention, in the deposition process of the dielectric layer, the barrier layer and the metal layer, the atomic layer deposition technology is preferably used for filling, thereby solving the problem of uniform filling of the dielectric layer and the metal layer of the nano-scale silicon through hole.

[0029] As a preferred embodiment of the present technical solution, in step S4, the material of the dielectric layer includes any one or more of silicon oxide, silicon nitride, silicon oxynitride and polyimide, and the thickness is 0.5-20 nm, and the specific thickness can be determined according to the size of the nanoTSV.

[0030] As a preferred embodiment of the present technical solution, in step S5, the material of the barrier layer includes any one or more of tantalum, tantalum nitride, titanium, titanium nitride and silicon nitride, and the thickness is 0.5-20 nm, and the specific thickness can be determined according to the size of the nanoTSV.

[0031] As a preferred embodiment of the present technical solution, in step S6, the material of the metal layer includes any one of tungsten, cobalt, ruthenium, copper, silver, niobium and aluminum.

[0032] In the second aspect, the present invention also discloses the nano-scale silicon through-holes prepared by the above-mentioned preparation method, which should also fall within the protection scope of the present invention.

[0033] The present invention uses a technology combining atomic layer etching and atomic layer deposition to smooth and uniformly fill the sidewalls of the high aspect ratio trenches manufactured by the Bosch process, which can achieve high-precision process control, thereby forming a nano-scale silicon via with a complete structure and function. Therefore, the nano-scale silicon via prepared by the present invention can meet the requirements of efficient signal interconnection of back power supply technology, and is conducive to building a back power supply network with excellent performance.

[0034] The method for preparing nano-scale silicon through vias of the present invention has at least the following beneficial effects:

[0035] The present invention combines the Bosch process with the precisely controllable atomic layer etching (ALE) technology and atomic layer deposition (ALD) technology. The roughness of the sidewall surface is reduced by the ALE technology, and the scallops generated by the Bosch process are eliminated to obtain smooth sidewalls. Then, the ALD technology is used to completely fill the dielectric layer and the metal layer, and finally a back power supply network with excellent performance is constructed. The method effectively solves the problems of scallops caused by the Bosch process and uniform filling of nano-scale silicon through holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 It is a schematic diagram of the process of the nano-scale through silicon via etching method of the present invention;

[0038] Figure 2-3 A schematic diagram of the preparation of a semiconductor substrate and forming a through silicon via window on the semiconductor substrate according to the present invention;

[0039] Figure 4-7 The present invention uses Bosch process to perform nano-scale trench etching to form a trench with scallop sidewalls;

[0040] Figure 8 This is a schematic diagram of a smooth side wall formed after the side wall is etched using the atomic layer etching technology in the present invention;

[0041] Fig. 9 It is a schematic diagram of the dielectric layer deposited by the atomic layer deposition technology of the present invention;

[0042] Fig.10 This is a schematic diagram of the present invention after the barrier layer is deposited using the atomic layer deposition technology;

[0043] Fig.11 This is a schematic diagram of the present invention after the metal layer is completely filled by atomic layer deposition technology.

[0044] Reference numerals

[0045] 1: substrate; 2: dielectric layer; 3: barrier layer; 4: metal layer. DETAILED DESCRIPTION

[0046] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0047] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form also includes the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this description, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0048] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Example 1

[0050] refer to Figure 1 , which is a schematic flow chart of the nanoscale through silicon via etching method of the present invention.

[0051] Performing step S1: providing a semiconductor substrate, forming a protection layer on the semiconductor substrate, and forming a window penetrating the thickness of the protection layer in the protection layer;

[0052] Executing step S2: using a Bosch process to prepare nanoscale grooves on the surface of the semiconductor substrate;

[0053] Executing step S3: etching the sidewalls of the nanoscale grooves using an atomic layer etching process to form smooth sidewalls;

[0054] Executing step S4: depositing a dielectric layer using an atomic layer deposition process;

[0055] Executing step S5: depositing a barrier layer using an atomic layer deposition process;

[0056] Execute step S6: deposit a metal layer using an atomic layer deposition process.

[0057] Figure 2-11 FIG. 1 is a schematic cross-sectional view of a nano-scale through silicon via etching method according to an embodiment of the present invention. Figure 2-11 The etching method of the present invention is specifically described:

[0058] like Figure 2-3 As shown, a semiconductor substrate is prepared, a first protective layer and a second protective layer are sequentially formed on the surface of the semiconductor substrate, and the second protective layer is patterned to form a window defining a through silicon via on the semiconductor substrate;

[0059] Among them, the material of the semiconductor substrate is silicon, germanium, silicon germanium or silicon on an insulating substrate. This embodiment takes silicon material as an example of a semiconductor substrate for detailed description. When in use, the natural oxide on the surface can be removed by soaking in dilute hydrofluoric acid to form a clean surface; the material of the first protective layer is silicon dioxide, and specifically, the plasma enhanced chemical vapor deposition method can be used to grow silicon dioxide on the surface of the semiconductor substrate as the first protective layer to prevent damage to the device formed on the semiconductor substrate during the subsequent etching process, and can be used as an insulating layer of the interconnect structure; the material of the second protective layer is photoresist, and specifically, a layer of photoresist can be coated on the first protective layer, and then the designed pattern can be transferred to the photoresist through the photoresist. After the photoresist is exposed, developed and other steps, a patterned second protective layer is formed; finally, the patterned second protective layer is used as a mask to wet-etch the first protective layer to form a window on the semiconductor substrate to define the position of the silicon through hole on the semiconductor substrate.

[0060] like Figure 4-7 As shown, the Bosch process is used to alternately introduce different gases into the reaction chamber, and utilize plasma to excite these gases to produce etching and deposition reactions, thereby forming nano-scale grooves on the semiconductor substrate;

[0061] Specifically, first, the process step length is set to 0.1-2s, that is, etching and deposition reactions are performed alternately every 0.1-2s, and the target etching depth is set to 300nm;

[0062] Then, in the etching stage, SF6 (sulfur hexafluoride) gas is introduced. In the plasma environment, SF6 reacts chemically with silicon to generate volatile compounds (such as SiF4), which are then pumped away to achieve silicon etching; in the deposition stage, C4F8 (octafluorocyclobutane) gas is introduced. Under plasma conditions, C4F8 can undergo polymerization to form a thin polymer protective film on the etched sidewalls. The protective film can slow down or prevent further etching of the sidewalls in the subsequent etching process, thereby achieving vertical etching of the grooves; the etching and deposition stages are performed alternately until the desired etching depth is reached;

[0063] Finally, after etching is completed, O2 (oxygen) is used for plasma cleaning to remove chemicals and polymers that may remain on the sample surface and in the grooves during the etching process, ensuring the cleanliness of the grooves and the smooth progress of subsequent processes.

[0064] like Figure 8 As shown, the sidewall of the nano-scale groove is etched by an atomic layer etching process to eliminate the scallop on the sidewall and form a smooth sidewall;

[0065] Atomic layer etching (ALE) technology is a high-precision, controllable nano-scale processing technology that can perform etching in a self-limiting manner, achieve layer-by-layer material removal through surface modification and surface removal, and accurately control the duration and gas pressure of the etching step and the repair step to accurately control the etching depth, thereby possibly reducing the surface roughness. When the present invention uses the atomic layer etching technology to etch the groove sidewall, thermal atomic layer etching technology (thermal ALE) or plasma enhanced atomic layer etching technology (PEALE) can be used.

[0066] Wherein, when the thermal atomic layer etching technology is used to etch the trench sidewall, the following steps are specifically included:

[0067] a. Oxidation step: The silicon surface is oxidized by introducing oxygen to generate silicon dioxide, so as to form a uniform oxide layer on the silicon surface, providing a basis for subsequent reactions;

[0068] b. Aluminization step: using TMA (trimethylaluminum) gas to react with SiO2 to convert it into Al2O3 (aluminum oxide), ensuring that the oxide layer is uniformly and controllably replaced with another material that is easier to process later through a ligand exchange mechanism;

[0069] c. Fluorination step: using HF (hydrogen fluoride) to fluorinate Al2O3 to AlF3 (aluminum fluoride) to convert aluminum oxide into a fluoride that is easily volatile;

[0070] d. Volatilization step: By reintroducing TMA, the AlF3 is removed from the surface by utilizing the ligand exchange mechanism, and the reaction products are volatilized to complete a complete etching cycle, ensuring the accuracy and self-limitation of etching.

[0071] When the plasma enhanced atomic layer etching technology is used to etch the trench sidewall, the following steps are specifically included:

[0072] a. Deoxidation layer: Before PEALE begins, CF4 / Ar plasma treatment is first used for 10 seconds to remove the native oxide on the surface of the silicon substrate to ensure the cleanliness and efficiency of the subsequent etching process;

[0073] b. Chlorination step: Use Cl2 plasma to chlorinate silicon to generate volatile chlorosilane (such as SiCl4). By controlling the parameters of Cl2 plasma (such as power, flow, time, etc.), the removal rate and morphology of silicon can be precisely controlled;

[0074] c. Removal step: using Ar plasma to remove the generated chlorosilane from the surface and restore the clean state of the substrate to ensure the smooth progress of the next etching cycle;

[0075] d. Purge step: A purge step is added between the chlorination and removal steps to purge the reaction chamber with an inert gas (such as Ar) to eliminate any unnecessary free radicals and ions and prevent the free radicals and ions from recombining on the substrate surface to form by-products.

[0076] like Fig. 9 As shown, the dielectric is deposited by atomic layer deposition process, and the material of the dielectric layer can be silicon oxide, silicon nitride, silicon oxynitride or polyimide, or exists in the form of a composite insulating layer structure;

[0077] Atomic layer deposition (ALD) is a high-precision thin film deposition technology based on self-limiting surface reactions. During the ALD process, two or more precursors are alternately introduced into the reaction chamber and chemically react with the substrate surface to form a uniform thin film. Since the reaction of each precursor is self-limiting, ALD can precisely control the thickness and composition of the film.

[0078] The conditions and steps for depositing silicon oxide as a dielectric layer using an atomic layer deposition process in the present invention are as follows:

[0079] a. Precursor selection

[0080] TDMAS (tris(dimethylamino)silane) was used as the silicon source precursor;

[0081] O3 (ozone) is used as the oxygen source precursor. Ozone is converted from high-purity oxygen (99.999%) through an ozone generator;

[0082] b. Precursor treatment

[0083] TDMAS was heated to 40 °C to increase its vapor pressure so that it could evaporate at a sufficient rate and enter the reaction chamber;

[0084] The ozone generator continuously produces ozone, which is transported to the reaction chamber through a pipeline;

[0085] c.Carrier gas

[0086] Nitrogen was used as the carrier gas to ensure that no other impurities were introduced or unnecessary chemical reactions occurred during the precursor delivery process. The flow rate of nitrogen was set to 10 sccm.

[0087] d. Reaction temperature

[0088] Based on the reaction kinetics of TDMAS and ozone and the quality of the desired film, the temperature of the reaction chamber was determined to be 300°C;

[0089] e.ALD cycle

[0090] In each ALD cycle, TDMAS is first introduced, which reacts with hydroxyl groups (or other active sites) on the substrate surface to form intermediate products such as silanol (Si-OH). Then, ozone is introduced, which reacts with silanol to form silicon oxide and release water vapor or other volatile byproducts. By alternating pulses of TDMAS and ozone and purging with nitrogen between each pulse, it is ensured that the precursors in the reaction chamber are completely reacted and removed, thereby avoiding cross contamination and unnecessary reactions.

[0091] By controlling the number of ALD cycles, the thickness of the deposited silicon oxide film can be precisely controlled. In this embodiment, the deposition thickness of the dielectric layer is preferably 10 nm.

[0092] like Fig.10 As shown, an atomic layer deposition process is further used to deposit a barrier layer, and the material of the barrier layer can be tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) or silicon nitride (Si3N4), or exists in the form of a composite layer structure;

[0093] The conditions and steps for depositing titanium nitride as a barrier layer using an atomic layer deposition process are as follows:

[0094] a. Precursor selection

[0095] TiCl4: As a titanium source, TiCl4 will decompose and react with the surface during the ALD process to provide titanium.

[0096] H2-N2 plasma: H2-N2 is used as a nitrogen source and reducing agent. The plasma state can improve the reaction activity and facilitate the formation of high-quality TiN films at low temperatures.

[0097] b. Deposition Step

[0098] Ar gas purge: Before and after each precursor is introduced, an inert gas (such as argon, Ar) is used for purge to remove the residual precursors and by-products in the reaction chamber.

[0099] TiCl4 pulse: First, a TiCl4 pulse is passed into the reaction chamber. TiCl4 molecules are adsorbed on the substrate surface and react with the surface hydroxyl groups (or other active sites) to form Ti-O-Cl or similar intermediates.

[0100] Ar gas purge: Ar gas was then used to purge to remove unreacted TiCl4 and by-products produced by the reaction.

[0101] H2-N2 plasma pulse: H2-N2 plasma is then introduced to provide N element to react with Ti-O-Cl intermediate to form TiN, while removing chlorine element through its reducing property to complete the deposition of TiN.

[0102] Ar gas purge again: Use Ar gas purge again to clean the reaction chamber and prepare for the next deposition cycle.

[0103] c. Cycle and thickness control

[0104] The above steps (TiCl4 pulse-purge-H2-N2 plasma pulse-purge) are repeated many times. By controlling the number of cycles, the thickness of the TiN film can be precisely controlled to 10 nm or thinner.

[0105] like Fig.11 As shown, finally, an atomic layer deposition process is used to deposit a metal layer, where the material of the metal layer can be tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), niobium (Nb) and aluminum (Al) and the like.

[0106] The conditions and steps for depositing metal tungsten to fill the grooves by atomic layer deposition process in the present invention are as follows:

[0107] a. Precursor selection

[0108] WF6: As a tungsten source, WF6 will decompose and react with the surface during the ALD process to release tungsten element.

[0109] B2H6: As a reducing agent, B2H6 reacts with WF6 in the ALD cycle to remove fluorine and promote the deposition of tungsten.

[0110] b. Deposition Step

[0111] Substrate preparation: First, ensure that the groove surface is clean, free of contaminants, and has certain active sites for precursor adsorption;

[0112] WF6 pulse: When WF6 pulse is passed into the reaction chamber, WF6 molecules will adsorb on the substrate surface and react with the active sites on it to form a layer of tungsten-containing intermediates;

[0113] Inert gas purging: Use inert gas (such as nitrogen or argon) for purging to remove unreacted WF6 and by-products produced by the reaction;

[0114] B2H6 pulse: B2H6 pulse is passed into the reaction chamber, and B2H6 reacts with the intermediate of WF6 to remove fluorine and promote the deposition of tungsten. At the same time, B2H6 may also play a reducing role to form a pure tungsten film;

[0115] Inert gas purge: The reaction chamber is purged again with inert gas to ensure that the surface is clean and free of residue before the next ALD cycle begins.

[0116] c. Cycle repetition

[0117] Repeat the above steps (WF6 pulse-purge-B2H6 pulse-purge) until the desired tungsten film thickness is achieved.

[0118] The cross-sectional structure of the nano-scale silicon via prepared in the above embodiment is as follows: Fig.11 shown.

[0119] In summary, the present invention uses ALE technology to achieve precise control at the atomic level, has the potential to remove a single atomic layer with extremely low damage, is not restricted by crystal orientation, effectively reduces the roughness of the sidewall surface, and achieves precise material removal, thereby forming a smooth TSV sidewall; and the use of ALD technology can achieve atomic layer filling, which can be carried out at a relatively low temperature, reducing interface diffusion and oxidation, while ensuring the surface flatness and filling yield of the dielectric layer and metal layer of the nano-scale silicon through hole after filling. Therefore, the present invention combines the Bosch process with ALE and ALD technologies, can achieve atomic layer precision process control, realize the preparation of nano-scale silicon through holes with higher integration, greatly improve the preparation quality of nano-scale silicon through holes, solve the problem of sidewall scallops generated by the Bosch process and uniform filling of the dielectric layer and metal layer of the nano-scale silicon through hole, and is conducive to the construction of a back power supply network with excellent performance.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing nanoscale through silicon vias, characterized in that: The following steps are involved: S1. providing a semiconductor substrate; S2, using Bosch process to prepare nano-scale grooves on the surface of semiconductor substrate; S3, etching the sidewalls of the nanoscale grooves using an atomic layer etching process to form smooth sidewalls; S4, depositing a dielectric layer using an atomic layer deposition process; S5, depositing a barrier layer using an atomic layer deposition process; S6. Depositing a metal layer using an atomic layer deposition process.

2. The preparation method according to claim 1, characterized in that: Step S1 includes forming a window defining a through silicon via on a semiconductor substrate by using a hard mask or a photoresist as a mask.

3. The preparation method according to claim 1, characterized in that: In step S2, when the Bosch process is performed, etching gas and passivation gas are alternately introduced into the reaction chamber to perform etching and deposition to form nano-scale grooves on the semiconductor substrate.

4. The preparation method according to claim 1, characterized in that: In step S3, the atomic layer etching process includes any one of thermal atomic layer etching and plasma enhanced atomic layer etching.

5. The preparation method according to claim 1, characterized in that: In step S4, the material of the dielectric layer includes any one or more of silicon oxide, silicon nitride, silicon oxynitride and polyimide.

6. The preparation method according to claim 5, characterized in that: The thickness of the dielectric layer is 0.5-20 nm.

7. The preparation method according to claim 1, characterized in that: In step S5, the material of the barrier layer includes any one or more of tantalum, tantalum nitride, titanium and titanium nitride.

8. The preparation method according to claim 7, characterized in that: The thickness of the barrier layer is 0.5-20 nm.

9. The preparation method according to claim 1, characterized in that: In step S6, the material of the metal layer includes any one or more of tungsten, cobalt, ruthenium, copper, silver, niobium and aluminum.

10. A nanoscale through silicon via, characterized in that: Prepared according to any one of claims 1 to 9.

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