Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a display area; the width of the display panel in the first direction is D, the first center line extends in the second direction, the distance between the first center line and the first edge of the display panel in the first direction is d1, d1 = D / 4, and the two sides of the first center line in the first direction are each provided with at least one gate drive circuit. The first direction intersects with the second direction; the gate drive circuit is located in the display area. According to the embodiment of the invention, the frameless effect can be realized, and the display uniformity can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the application of display panels is becoming more and more common, and users have more and more requirements for display panels. Display panels are gradually developing towards thinness, high screen-to-body ratio, and even borderless. How to achieve borderless is an important issue faced by those skilled in the art. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a display device, which can achieve borderless display and improve display uniformity.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising a display area; a first center line, the width of the display panel in a first direction is D, the first center line extends along a second direction, the distance between the first center line and a first edge of the display panel in the first direction is d1, d1=D / 4, and at least one gate drive circuit is arranged on each side of the first center line in the first direction; the first direction and the second direction intersect; and the gate drive circuit is located in the display area.

[0005] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel as described in any embodiment of the first aspect.

[0006] The display panel and display device provided in the embodiments of the present application break the conventional design thinking and no longer limit the gate driving circuit to the edge display area. Instead, the gate driving circuit is dispersed on both sides of the first center line. In this way, even if the number of gate driving circuits is large, there is enough display area to accommodate them, thereby achieving borderless display. In addition, compared with limiting the gate driving circuit to the edge display area, dispersing the gate driving circuit on both sides of the first center line can shorten the distance between at least part of the gate driving circuit and the center of the display area, thereby shortening the distance for the gate driving circuit to charge to the center of the display area, thereby improving signal delay and voltage drop, and improving display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0008] Figure 1 A schematic diagram showing the structure of a display panel provided in an embodiment of the present application is shown;

[0009] Figure 2Another schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown;

[0010] Figure 3 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0011] Figure 4 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0012] Figure 5 A schematic diagram showing a structure of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0013] Figure 6 Another structural schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0014] Figure 7 Another structural schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0015] Figure 8 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0016] Fig. 9 Show Figure 8 A schematic diagram of a structure of the middle region Q1;

[0017] Fig.10 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0018] Fig.11 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0019] Fig.12 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0020] Fig.13 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0021] Fig.14 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0022] Fig.15 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0023] Fig.16 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0024] Fig.17Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0025] Fig.18 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown.

[0026] Description of some reference numerals:

[0027] 100. Display panel;

[0028] AA, display area; A1, first sub-display area; A2, second sub-display area;

[0029] L1, first midline, L2, second midline;

[0030] C1, first edge;

[0031] 10. Gate drive circuit; 10a. First type of gate drive circuit; 10b. Second type of gate drive circuit; 10c. Third type of gate drive circuit; 10d. Other types of gate drive circuit;

[0032] 11. a first gate drive circuit; 12. a second gate drive circuit; 13. a third gate drive circuit; 14. a fourth gate drive circuit; 15. a fifth gate drive circuit; 16. a sixth gate drive circuit; 17. a seventh gate drive circuit;

[0033] 20. pixel circuit; 201. pixel circuit column;

[0034] 21. Amplitude modulation subcircuit; 22. Pulse width modulation subcircuit;

[0035] 30. Light-emitting element;

[0036] 41. A first signal line; 42. A second signal line. DETAILED DESCRIPTION

[0037] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0038] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0039] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0040] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0041] In the embodiments of the present application, the term "electrically connected" may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components. The term "drive" may refer to "control" or "operate". The term "portion" may refer to "local". The term "pattern" may refer to "component".

[0042] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0043] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0044] The display panel includes a pixel circuit, a light-emitting element and a gate driving circuit. The pixel circuit generates a driving current under the control of the gate driving circuit to drive the light-emitting element to emit light.

[0045] The pixel circuit and the light-emitting element are located in the display area of ​​the display panel. In the related art, the pixel circuit in the edge display area is retracted to make room for the gate drive circuit. This design method can achieve borderless design when the gate drive architecture required by the pixel circuit is not complicated (that is, the number of gate drive circuits is not large). However, with the improvement of the driving performance requirements, the number of gate drive circuits will increase, so that the design method that only relies on the retraction of the pixel circuit in the edge display area to make room for the gate drive circuit can no longer meet the architectural design of multiple groups of gate drive circuits. In addition, the gate drive circuit is set in the edge display area, and the signal output by it is charged from the edge display area to the central display area. For the central display area, the charging distance is far, and there will be signal delay and voltage drop, resulting in poor charging uniformity of the pixel circuit, affecting the display uniformity.

[0046] In order to solve the above technical problems, embodiments of the present application provide a display panel and a display device. Embodiments of the display panel and the display device will be described below in conjunction with the accompanying drawings.

[0047] like Figure 1 As shown, the display panel 100 provided in the embodiment of the present application includes a display area AA. It is understandable that the display area AA includes a pixel circuit and a light emitting element ( Figure 1 (not shown in the figure), the display area AA is used to display pictures.

[0048] For example, in the embodiment of the present application, the display panel is a borderless display panel with a narrow border, that is, in the first direction X, the non-display area on the left and right sides of the display area AA is very small, or even does not exist. For example, the borderless display panel is used as an example in the drawings of the present application.

[0049] The display area AA includes a first sub-display area A1 and a second sub-display area A2 adjacent to each other in a first direction X. Figure 1 The first sub-display area A1 is the display area on the left, and the second sub-display area A2 is the display area on the right. The display panel includes a first edge C1 extending along the second direction Y, and the two first edges C1 are opposite to each other in the first direction X. For easy distinction, Figure 1 Among them, C11 is the first edge of the first sub display area A1, and C12 is the first edge of the second sub display area A2.

[0050] The width of the display panel in the first direction X is D, the first center line L1 extends along the second direction Y, the distance between the first center line L1 and the first edge C1 is d1, d1 = D / 4. It can be understood that the display panel is divided into left and right half screens in the first direction, and the first center line L1 is the center line of the half screen. For easy distinction, Figure 1 Wherein L11 is the center line of the first sub display area A1, and the distance between L11 and C11 is equal to D / 4; L12 is the center line of the second sub display area A2, and the distance between L12 and C12 is equal to D / 4.

[0051] Herein, the first direction X intersects with the second direction Y. For example, the first direction X is a row direction, and the second direction Y is a column direction.

[0052] It should be noted that the first center line is located in the display area, and the first center line is parallel or approximately parallel to the first edge. The first center line does not represent the actual alignment of the display panel, and can be understood as the position center line of the virtually defined display panel, that is, the first center line is used to indicate the position. The two or more parameters defined in this article as "equal", "equal to", and "=" are not absolutely equal, and a certain error is allowed. It should be noted that the equal distances mentioned in this disclosure refer to distance values ​​being equal within the allowable error range (±5%).

[0053] The gate driving circuit 10 of the display panel is located in the display area AA, and at least one gate driving circuit 10 is disposed on both sides of the first center line L1 in the first direction X.

[0054] Exemplarily, at least one gate driving circuit is disposed between the first center line L11 of the first sub display area A1 and the first center line L12 of the second sub display area A2.

[0055] As an example, in the first sub-display area A1, the first gate driving circuit 11 and the second gate driving circuit 12 are respectively disposed on both sides of the first center line L11 of the first sub-display area A1. In the second sub-display area A2, the first gate driving circuit 11 and the second gate driving circuit 12 are also respectively disposed on both sides of the first center line L12 of the second sub-display area A2.

[0056] The display panel provided in the embodiment of the present application breaks the conventional design thinking and no longer limits the gate driving circuit to the edge display area. Instead, the gate driving circuit is dispersed on both sides of the first center line. In this way, even if the number of gate driving circuits is large, there is enough display area to accommodate them, thereby achieving a narrow frame or even no frame. In addition, compared with limiting the gate driving circuit to the edge display area, dispersing the gate driving circuit on both sides of the first center line can shorten the distance between at least part of the gate driving circuit and the center of the display area, thereby shortening the distance for the gate driving circuit to charge to the center of the display area, thereby improving signal delay and voltage drop, and improving display uniformity.

[0057] In some embodiments, Figure 1 As shown, the distance between the second center line L2 and the first edge C1 of the display panel in the first direction X is d2, d2=D / 2. At least one gate driving circuit 10 is disposed between the first center line L1 and the second center line L2.

[0058] The second center line L2 is the boundary line between the first sub-display area A1 and the second sub-display area A2, and the widths of the first sub-display area A1 and the second sub-display area A2 are equal in the first direction X. It can be understood that the distance between the second center line L2 and the first edge C11 of the first sub-display area A1 is d2, and the distance between the second center line L2 and the first edge C12 of the second sub-display area A2 is also d2. This is equivalent to dividing the display panel into two half-screens in the first direction, and gate driving circuits are arranged on both sides of the first center line of each half-screen.

[0059] Exemplarily, the gate driving circuit in each half screen may be arranged close to its first center line.

[0060] For example, Figure 1 In the embodiment, two gate driving circuits in the first sub display area A1 are arranged close to the first center line L11 thereof, and two gate driving circuits in the second sub display area A2 are arranged close to the first center line L12 thereof.

[0061] in addition, Figure 1 It is illustrated that a second gate drive circuit 12 is arranged between the second center line L2 and the first center line L1. It can be understood that a second gate drive circuit 12 is arranged between the second center line L2 and the first center line L11 in the first sub-display area A1, and another second gate drive circuit 12 is arranged between the second center line L2 and the first center line L12 in the second sub-display area A2. Figure 1 The dashed line with an arrow in the middle represents the transmission path of the signal output by the second gate driving circuit 12 . It can be seen that the transmission distance of the signal output by the second gate driving circuit 12 is only about one quarter of the width D of the display panel.

[0062] It is understandable that, for any first gate driving circuit 11 or any second gate driving circuit 12, the transmission distance of its output signal is only about one-fourth of the width D of the display panel, which can more effectively shorten the charging distance of the gate driving circuit, thereby improving signal delay and voltage drop, and improving display uniformity.

[0063] The technical concept of the present application can also be explained by the positional relationship between the gate driving circuit and the pixel.

[0064] In some embodiments, Figure 2 As shown, the display panel 100 includes N pixel circuit columns 201 arranged in a first direction X, where N is an integer, and the pixel circuit column 201 includes a plurality of pixel circuits 20 arranged in the first direction X. At least one gate driving circuit 10 is disposed on both sides of the N / 4th pixel circuit column 201 (1 / 4) in the first direction X, where N / 4 is an integer.

[0065] In other words, the display panel includes N pixel columns arranged in a first direction, N is an integer, and the pixel column includes a plurality of pixel circuits arranged in the first direction. At least one gate driving circuit is disposed on both sides of the N / 4th pixel column in the first direction, wherein N / 4 is an integer.

[0066] like Figure 2 As shown, the pixel circuit columns are marked from left to right, and the N / 4th pixel circuit column 201 (1 / 4) and the 3N / 4th pixel circuit column 201 (3 / 4) are marked respectively. It can be understood that the 3N / 4th pixel circuit column 201 (3 / 4) from left to right is the N / 4th pixel circuit column 201 from right to left.

[0067] The N / 4th pixel circuit column 201 may include the N / 4th pixel circuit column 201 from left to right, and the N / 4th pixel circuit column 201 from right to left.

[0068] Exemplarily, the N / 4th pixel circuit column 201 from left to right is provided with at least one gate driving circuit 10 on both sides in the first direction X, and the N / 4th pixel circuit column 201 from right to left is provided with at least one gate driving circuit 10 on both sides in the first direction X.

[0069] For example, N=240, from left to right, at least one gate driving circuit is provided on both sides of the 60th pixel circuit column in the first direction, and from left to right, at least one gate driving circuit is provided on both sides of the 180th pixel circuit column in the first direction. In other words, N=240, from right to left, at least one gate driving circuit is provided on both sides of the 60th pixel circuit column in the first direction, and from right to left, at least one gate driving circuit is provided on both sides of the 180th pixel circuit column in the first direction.

[0070] The embodiment of the present application improves the positional relationship between the gate driving circuit and the pixel circuit column, and no longer limits the gate driving circuit to the edge display area. Instead, the gate driving circuit is dispersed on both sides of the N / 4th pixel circuit column. In this way, even if the number of gate driving circuits is large, there is enough display area to accommodate them, thereby achieving borderless display. In addition, compared with limiting the gate driving circuit to the edge display area, dispersing the gate driving circuit on both sides of the N / 4th pixel circuit column can shorten the distance between at least part of the gate driving circuit and the center of the display area, thereby shortening the distance for the gate driving circuit to charge to the center of the display area, thereby improving signal delay and voltage drop, and improving display uniformity.

[0071] In some embodiments, Figure 2 As shown, along the first direction X, at least one gate driving circuit 10 is included between the N / 4th pixel circuit column 201 (1 / 4) and the N / 2th pixel circuit column 201 (1 / 2), wherein N / 2 is an integer.

[0072] In other words, along the first direction X, at least one gate driving circuit 10 is included between the N / 4th pixel column and the N / 2th pixel column, wherein N / 2 is an integer.

[0073] The N / 2th pixel circuit column can be understood as the pixel circuit column located at the center of the entire display area. The N / 4th pixel circuit column in the left display area can be understood as the pixel circuit column located at the center of the left display area, and the N / 4th pixel circuit column in the right display area can be understood as the pixel circuit column located at the center of the right display area.

[0074] For example, Figure 2 In the left display area, two gate driving circuits are respectively arranged on both sides of the pixel circuit column 201 (1 / 4), and two gate driving circuits are respectively arranged on both sides of the pixel circuit column 201 (3 / 4) in the right display area. For example, a second gate driving circuit 12 is arranged between the pixel circuit column 201 (1 / 4) and the pixel circuit column 201 (1 / 2), and a second gate driving circuit 12 is arranged between the pixel circuit column 201 (3 / 4) and the pixel circuit column 201 (1 / 2). Figure 2The dashed line with an arrow in the middle represents the transmission path of the signal output by the second gate driving circuit 12 . It can be seen that the transmission distance of the signal output by the second gate driving circuit 12 is only about one quarter of the width D of the display panel.

[0075] Similarly, for any first gate driving circuit 11 or any second gate driving circuit 12, the transmission distance of its output signal is only about one-fourth of the display panel width D, which can more effectively shorten the charging distance of the gate driving circuit, thereby improving signal delay and voltage drop, and improving display uniformity.

[0076] It is understandable that the signal output by the gate driving circuit is transmitted to the pixel circuit, and the signal output by the gate driving circuit is used to control the transistor in the pixel circuit to be turned on or off.

[0077] The gate driving circuit may include a plurality of cascaded shift registers. In the same gate driving circuit, the plurality of shift registers are arranged along the second direction.

[0078] In some embodiments, Figure 3 As shown, the display panel includes a partition area Q, the first center line L1 is located in the partition area Q, at least one gate driving circuit 10 is disposed on both sides of the partition area Q in the first direction X, and the width of the partition area Q in the first direction X is less than or equal to 625 um.

[0079] Exemplarily, the partition in the first sub-display area A1 is the first partition Q1, the center line L11 is located in the first partition Q1, and at least one gate driving circuit 10 is disposed on each of the left and right sides of the first partition Q1. The partition in the second sub-display area A2 is the second partition Q2, the center line L11 is located in the second partition Q2, and at least one gate driving circuit 10 is disposed on each of the left and right sides of the second partition Q2.

[0080] In the embodiment of the present application, the separation zone separates the gate driving circuits on the left and right sides thereof, that is, the gate driving circuits may not be arranged closely together, which can reduce signal interference between different gate driving circuits.

[0081] In some embodiments, Figure 4 As shown, the display panel includes N pixel circuit columns 201 arranged in a first direction X, and the pixel circuit column 201 includes a plurality of pixel circuits 20 arranged in a second direction Y; the N / 4th pixel circuit column 201 (1 / 4) is located in the partition area Q1.

[0082] Figure 4 The 3N / 4th pixel circuit column 201 (3 / 4) from left to right in FIG. 1 is the N / 4th pixel circuit column from right to left. Figure 4The middle partition area Q may also include a first partition area Q1 and a second partition area Q2 , the pixel circuit column 201 ( 1 / 4 ) is located in the first partition area Q1 , and the pixel circuit column 201 ( 3 / 4 ) is located in the second partition area Q2 .

[0083] In the embodiment of the present application, the partition area separates the gate driving circuits on the left and right sides thereof, and a pixel circuit is arranged in the partition area, thereby avoiding wasting space.

[0084] In some embodiments, Figures 5 to 7 As shown in any of the accompanying drawings, the pixel circuit 20 of the display panel includes an amplitude modulation sub-circuit 21 and a pulse width modulation sub-circuit 22, and the gate driving circuit includes a first gate driving circuit 11 and a second gate driving circuit 12. The gate signal output by the first gate driving circuit 11 is used to control the first data signal PAM_data to be written into the amplitude modulation sub-circuit 21, and the gate signal output by the second gate driving circuit 12 is used to control the second data signal PWM_data to be written into the pulse width modulation sub-circuit 22.

[0085] In order to meet the driving requirements of high-resolution display panels, such as micro LED (Micro Light Emitting Diode) or organic light emitting diode (Organic Light Emitting Diode) display panels, a pixel circuit combining pulse amplitude modulation (Pulse Amplitude Modulation, PAM) and pulse width modulation (Pulse Width Modulation, PWM) is used to control the driving current intensity and the duration of the driving current to control the light-emitting state of the light-emitting element.

[0086] The amplitude modulation subcircuit 21 is connected to the pulse width modulation subcircuit 22. The pixel circuit 20 generates a driving current under the control of the amplitude modulation subcircuit 21 and the pulse width modulation subcircuit 22. The amplitude modulation subcircuit 21 can be used to control the amplitude of the driving current, and the pulse width modulation subcircuit 22 can be used to adjust the pulse width of the voltage applied to the first electrode of the light emitting element 30.

[0087] The pulse width modulation subcircuit 22 adjusts the pulse width of the voltage applied to the first electrode of the light emitting element 30, that is, the pulse width modulation subcircuit 22 adjusts the actual emission period of the driving current applied to the light emitting element 30, and at the same time, the driving current applied to the light emitting element is maintained at a constant level to adjust the grayscale or brightness displayed by the light emitting element, rather than adjusting the grayscale or brightness displayed by the light emitting element only by adjusting the magnitude of the driving current applied to the light emitting element. Therefore, the amplitude modulation subcircuit 21 can provide the driving current to the light emitting element so that the light emitting element is driven with the best luminous efficiency, and adjust the grayscale or brightness displayed by the light emitting element by adjusting the light emission duty ratio of the light emitting element (that is, the emission period of the light emitting element) through the pulse width modulation subcircuit 22.

[0088] In the drawings of the present application, PAM_S2 represents the gate signal output by the first gate driving circuit 11, PWM_S2 represents the gate signal output by the second gate driving circuit 12, PAM_data represents the first data signal, and PWM_data represents the second data signal.

[0089] It should be noted that Figures 5 to 7 The circuit structure shown is only exemplary and is not intended to limit the present application. Regardless of the specific structures of the amplitude modulation subcircuit and the pulse width modulation subcircuit in the pixel circuit, both of them usually need to write data signals. Therefore, the design concept of the gate drive circuit in the present application can also be applied to Figures 5 to 7 Pixel circuits with other structural forms than the circuit structure shown.

[0090] In some embodiments, Figure 8 As shown, in the first direction X, the first gate driving circuit 11 is located on a side of the first center line L1 close to the second center line L2, and the second gate driving circuit 12 is located on a side of the first center line L1 away from the second center line L2.

[0091] Or, if Figure 1 As shown, in the first direction X, the first gate driving circuit 11 is located on a side of the first center line L1 away from the second center line L2, and the second gate driving circuit 12 is located on a side of the first center line L1 close to the second center line L2.

[0092] For example, Figure 1 or Figure 8 As shown, a first gate driving circuit 11 and a second gate driving circuit 12 are provided on both sides of the second center line L2, and the two first gate driving circuits 11 on both sides of the second center line L2 are symmetrical about the second center line L2, and the two second gate driving circuits 12 on both sides of the second center line L2 are symmetrical about the second center line L2. In this way, the signal distribution output by the first gate driving circuit and the second gate driving circuit can be relatively uniform, thereby improving display uniformity.

[0093] like Figure 8 As shown, in the first direction X, the distance between the first gate driving circuit 11 and the first center line L1 is marked as d3, and the distance between the second gate driving circuit 12 and the first center line L1 is marked as d4. It should be noted that, Figure 8 The d3 and d4 are only used to illustrate the distance between the gate driving circuit and the first center line, and are not used to limit the size of d3 and d4.

[0094] In some embodiments, d3=d4.

[0095] For example, the signals output by the first gate driving circuit and the second gate driving circuit are the same. When d3=d4, the first gate driving circuit and the second gate driving circuit can be distributed relatively evenly. For the entire display area, the signal delay and voltage drop output by the first gate driving circuit and the second gate driving circuit will be relatively uniform, thereby improving display uniformity.

[0096] In other embodiments, d3≠d4.

[0097] The driving requirements of the amplitude modulation sub-circuit and the pulse width modulation sub-circuit may be different, so the signals output by the first gate driving circuit and the second gate driving circuit may be different. When d3≠d4, the relative distribution positions of the first gate driving circuit and the second gate driving circuit can be flexibly adjusted to flexibly match the different driving requirements of the amplitude modulation sub-circuit and the pulse width modulation sub-circuit.

[0098] As an example, d3<d4.

[0099] The closer the gate drive circuit is to the first center line, the closer the flow path of the gate drive circuit output signal is to one quarter of the width of the display panel, and the lower the signal delay and voltage drop of the gate drive circuit output signal will be. The amplitude modulation subcircuit has a relatively large impact on the luminous brightness, and the gate signal output by the first gate drive circuit is used to control the writing of the data signal of the amplitude modulation subcircuit. Therefore, the signal of the first gate drive circuit has a relatively large impact on the luminous brightness. In the case of d3<d4, the first gate drive circuit is arranged closer to the first center line, so that the signal delay and voltage drop of the first gate drive circuit will be relatively low, thereby improving display uniformity.

[0100] It is understandable that, in other examples, if the signal delay and voltage drop of the second gate driving circuit are required to be relatively low, the second gate driving circuit may be arranged to be closer to the first center line.

[0101] The first gate drive circuit and the second gate drive circuit each include an input terminal and an output terminal. The input terminal of the gate drive circuit can be used to access at least one of the following clock signals (CK, CKB), a trigger signal (STV), a fixed voltage signal (VGH and / or VGL), and a reset signal (Reset). The output terminal of the gate drive circuit is used to output a gate signal, which is used to control the pixel circuit. The output terminal of the gate drive circuit is electrically connected to the pixel circuit. For example, an output terminal of the gate drive circuit is electrically connected to a plurality of pixel circuits located in the same row.

[0102] It can be understood that when the first gate driving circuit is provided on both sides of the second center line, the closer the output end of the first gate driving circuit is to the first center line, the closer the transmission path of the signal output by the first gate driving circuit is to one quarter of the width of the display panel, and the same is true for the second gate driving circuit.

[0103] In some embodiments, in the first direction, of the input and output of the first gate driving circuit, the input of the first gate driving circuit is closer to the first center line, and of the input and output of the second gate driving circuit, the input of the second gate driving circuit is closer to the first center line. In this way, the path of the signal transmitted by the output of the first gate driving circuit is closer to one quarter of the width of the display panel.

[0104] In some embodiments, Fig. 9 As shown, the first gate driving circuit 11 is connected to multiple first signal lines 41. In the first direction X, the number of first signal lines 41 distributed on the side of the first gate driving circuit 11 close to the first center line L1 is n1, and the number of first signal lines 41 distributed on the side of the first gate driving circuit 11 away from the first center line L1 is n2, and n1<n2.

[0105] The second gate driving circuit 12 is connected to multiple second signal lines 42. In the first direction X, the number of second signal lines 42 distributed on the side of the second gate driving circuit 12 close to the first center line L1 is n3, and the number of second signal lines 42 distributed on the side of the second gate driving circuit 12 away from the first center line L1 is n4, and n3<n4.

[0106] The first signal line 41 and the second signal line 42 extend along the second direction Y. At least some of the signal lines connected to the gate driving circuit are connected to the driving chip, and the signal output by the driving chip is transmitted to the gate driving circuit to control the gate driving circuit.

[0107] Fig. 9In the figure, the signal line of the first gate driving circuit 11 close to the first center line L1 is marked as signal line 411, and the signal line of the first gate driving circuit 11 away from the first center line L1 is marked as signal lines 412 and 413. For example, the signal line 411 can be used for a fixed voltage signal or other signals, and the signal lines 412 and 413 can be used for transmitting two clock signals or other signals with misaligned timing.

[0108] Fig. 9 In the figure, the signal line of the second gate driving circuit 12 close to the first center line L1 is marked as signal line 421, and the signal line of the second gate driving circuit 12 away from the first center line L1 is marked as signal lines 422 and 423. Exemplarily, the signal line 421 can be used for a fixed voltage signal or other signal, and the signal lines 422 and 423 can be used for transmitting two clock signals or other signals with misaligned timing.

[0109] It should be noted that Fig. 9 The number of signal lines shown is merely exemplary and is not intended to limit the present application.

[0110] In the embodiment of the present application, the number of first signal lines distributed on the side of the first gate drive circuit close to the first center line is relatively small, so a smaller space can be designed between the first gate drive circuit and the first center line, that is, the first gate drive circuit can be arranged closer to the first center line, thereby reducing the delay and voltage drop of the output signal of the first gate drive circuit. Similarly, the number of second signal lines distributed on the side of the second gate drive circuit close to the first center line is relatively small, so a smaller space can be designed between the second gate drive circuit and the first center line, that is, the second gate drive circuit can be arranged closer to the first center line, thereby reducing the delay and voltage drop of the output signal of the second gate drive circuit.

[0111] The pixel circuit may include a data writing module, a gate reset module, an anode reset module, etc. The data writing module is used to write data signals, and the degree of writing of the data signals directly affects the brightness, that is, compared with other functional modules, the data writing module has a greater impact on the brightness. Therefore, the signal of the gate driving circuit that controls the data writing module has a greater impact on the brightness.

[0112] To this end, in some embodiments, Fig.10The gate driving circuit 10 includes a first type of gate driving circuit 10a and other types of gate driving circuits 10d. The gate signal output by the first type of gate driving circuit 10a is used to control the data signal to be written into the pixel circuit. In the first direction X, the distance between the first type of gate driving circuit 10a and the first center line L1 is smaller than the distance between the other types of gate driving circuits 10d and the first center line L1. In this way, the first type of gate driving circuit is closer to the first center line, so that the delay and voltage drop of the output signal of the first type of gate driving circuit are relatively low, so as to improve the display uniformity.

[0113] For example, for the first type of gate driving circuit 10a and the other type of gate driving circuit 10d located on the same side of the first center line L1, the first type of gate driving circuit 10a is located between the first center line L1 and the other type of gate driving circuit 10d.

[0114] Exemplarily, the first type of gate driving circuit 10a includes the first gate driving circuit 11 and the second gate driving circuit 12 described above. At least one other type of gate driving circuit 10d may be distributed on the side of the first gate driving circuit 11 away from the first center line L1, and at least one other type of gate driving circuit 10d may also be distributed on the side of the second gate driving circuit 12 away from the first center line L1. At least two other types of gate driving circuits 10d on the same side of the second center line L2 are used to control different functional modules in the pixel circuit. For example, one other type of gate driving circuit 10d is used to control the reset signal to be written into the pixel circuit, one other type of gate driving circuit 10d is used to control the light emission control signal to be written into the pixel circuit, and one other type of gate driving circuit 10d is used to provide a sweep signal (SWEEP), etc.

[0115] In some embodiments, Fig.11 As shown, the gate driving circuit 10 includes a first type of gate driving circuit 10a, a second type of gate driving circuit 10b and a third type of gate driving circuit 10c. The gate signal output by the first type of gate driving circuit 10a is used to control the data signal to be written into the pixel circuit, the gate signal output by the second type of gate driving circuit 10b is used to control the reset signal to be written into the pixel circuit, and the third type of gate driving circuit 10c is used to output a sweep signal and / or a light emitting control signal. In the first direction X, the third type of gate driving circuit 10c is spaced between the first type of gate driving circuit 10a and the second type of gate driving circuit 10b.

[0116] For example, please refer to Fig.11 ,as well as Figures 5 to 7Any one of the gate drive circuits 10a of the first type includes PAM_S2 and PWM_S2, the gate signal output by the gate drive circuit 10b of the second type includes PAM_S1 and PWM_S1, and the gate signal output by the gate drive circuit 10c of the third type includes PAM_EM, PWM_EM, and SWEEP. PAM_REF1, PAM_REF2, PWM_REF1, and PWM_REF2 represent reset signals.

[0117] For example, please refer to Fig.11 , in the first direction X, the display area AA is divided into four sub-areas, namely the first sub-area A11, the second sub-area A12, the third sub-area A22, and the fourth sub-area A21. The first sub-area A11 and the second sub-area A12 are separated by the center line L11, the third sub-area A22 and the fourth sub-area A21 are separated by the center line L12, and the second sub-area A12 and the third sub-area A22 are separated by the second center line L2. For each sub-area, the first type of gate driving circuit 10a, the second type of gate driving circuit 10b and the third type of gate driving circuit 10c can be arranged therein, and the distribution rule in each sub-area is that the third type of gate driving circuit 10c is located between the first type of gate driving circuit 10a and the second type of gate driving circuit 10b.

[0118] As introduced above, the closer the gate drive circuit is to the first center line, the smaller the circulation distance of its output signal can be. The writing of the data signal directly affects the size of the driving current, and its influence on the brightness is the greatest. The light-emitting control signal and the frequency sweep signal affect the light-emitting duration of the light-emitting element, and their influence on the brightness is second, and the reset signal has the least influence on the brightness. In the embodiment of the present application, the first type of gate drive circuit that has the greatest influence on the brightness is set closest to the first center line, the second type of gate drive circuit that has the least influence on the brightness is set farthest from the first center line, and the third type of gate drive circuit is set between the two. In this way, the importance of the influence of various types of gate drive circuits on the brightness can be matched, which is more conducive to optimizing the display uniformity.

[0119] In some embodiments, please refer to Fig.11 and Figure 5, the pixel circuit 20 includes an amplitude modulation subcircuit 21 and a pulse width modulation subcircuit 22, and the second type of gate drive circuit 10b includes a third gate drive circuit 13 and a fourth gate drive circuit 14. The gate signal output by the third gate drive circuit 13 is PAM_S1, and the gate signal output by the fourth gate drive circuit 14 is PWM_S1. The gate signal output by the third gate drive circuit 13 is used to control the reset signal PAM_REF1 to be written into the amplitude modulation subcircuit 21, and the gate signal output by the fourth gate drive circuit 14 is used to control the reset signal PWM_REF1 to be written into the pulse width modulation subcircuit 22; in the first direction X, the third gate drive circuit 13 and the fourth gate drive circuit 14 are respectively located on both sides of the first center line L1.

[0120] For example, Fig.11 As shown, for the display area on the same side of the second center line L2, the third gate driving circuit 13 is located on the side of the first center line L1 close to the second center line L2, and the fourth gate driving circuit 14 is located on the side of the first center line L1 away from the second center line L2. In other examples, the third gate driving circuit 13 may be located on the side of the first center line L1 away from the second center line L2, and the fourth gate driving circuit 14 may be located on the side of the first center line L1 close to the second center line L2.

[0121] For example, Figure 5 As shown, the writing of reset signal PAM_REF2 can be controlled by gate signal PAM_S2 or PAM_S1, and the writing of reset signal PWM_REF2 can be controlled by gate signal PWM_S2 or PWM_S1. As described above, gate signal PAM_S2 is provided by the first gate driving circuit, and gate signal PWM_S2 is provided by the second gate driving circuit.

[0122] In the embodiment of the present application, for the display area on the same side of the second center line L2, the third gate driving circuit 13 and the fourth gate driving circuit 14, which have the least impact on the brightness, are respectively located on both sides of the first center line L1. In this way, there is a certain amount of space on both sides of the first center line L1 to place other gate driving circuits that have a relatively large impact on the brightness. In this way, the overall layout can be optimized.

[0123] In some embodiments, please refer to Fig.11 and Figure 5The pixel circuit 20 includes an amplitude modulation sub-circuit 21 and a pulse width modulation sub-circuit 22. The third type of gate driving circuit 10c includes a fifth gate driving circuit 15, a sixth gate driving circuit 16 and a seventh gate driving circuit 17. The fifth gate driving circuit 15 is used to output a first light-emitting control signal PAM_EM, the sixth gate driving circuit 16 is used to output a second light-emitting control signal PWM_EM, and the seventh gate driving circuit 17 is used to output a sweep signal SWEEP. The fifth gate driving circuit 15 is electrically connected to the amplitude modulation sub-circuit 21, and the sixth gate driving circuit 16 and the seventh gate driving circuit 17 are electrically connected to the pulse width modulation sub-circuit 22. In the first direction X, the fifth gate driving circuit 15 and the sixth gate driving circuit 16 are adjacent to each other.

[0124] The gate signals output by the fifth gate driving circuit 15 and the sixth gate driving circuit 16 are both used to control the luminous time. The two are arranged adjacent to each other so that their signal delay and voltage drop tend to be consistent, thereby avoiding large differences in the control of the luminous time between the two.

[0125] Exemplarily, a group of the fifth gate driving circuit 15 and the sixth gate driving circuit 16 are respectively arranged on both sides of the second center line L2, and the fifth gate driving circuit 15 and the sixth gate driving circuit 16 are adjacent to each other on either side of the second center line L2.

[0126] In some embodiments, please refer to Fig.11 In the first direction X, the fifth gate driving circuit 15 and the sixth gate driving circuit 16 are located on one side of the first center line L1, and the seventh gate driving circuit 17 is located on the other side of the first center line L1.

[0127] Exemplarily, the fifth gate drive circuit 15 and the sixth gate drive circuit 16 are located on the side of the first center line L1 close to the second center line L2, and the seventh gate drive circuit 17 is located on the side of the first center line L1 away from the second center line L2. Of course, in other examples, it is also possible that: the fifth gate drive circuit 15 and the sixth gate drive circuit 16 are located on the side of the first center line L1 away from the second center line L2, and the seventh gate drive circuit 17 is located on the side of the first center line L1 close to the second center line L2.

[0128] The fifth gate driving circuit 15, the sixth gate driving circuit 16 and the seventh gate driving circuit 17 have a similar effect on brightness. If the three are located on the same side of the first center line, one of them must be farther away from the first center line, and the farther away from the first center line, the greater the signal delay and voltage drop. In the embodiment of the present application, the three are distributed on both sides of the first center line, so that the distances between the three and the first center line tend to be consistent, thereby making the signal delay and voltage drop of the three also tend to be consistent, so as to optimize display uniformity.

[0129] In some embodiments, Fig.12 As shown, the display panel 100 includes two sub-display areas arranged in a first direction X, and each sub-display area includes a first center line L1. The two sub-display areas are a first sub-display area A1 and a second sub-display area A2, the first center line of the first sub-display area A1 is L11, and the first center line of the second sub-display area A2 is L12.

[0130] The gate driving circuit includes a target gate driving circuit 101. The same sub-display area includes n target gate driving circuits 101 outputting the same gate signal. The n target gate driving circuits 101 in the sub-display area are evenly distributed in the first direction X, and n≥2.

[0131] Fig.12 In the figure, each sub-display area includes two target gate driving circuits 101. For the first sub-display area A1, it includes a one-third line L31 and a two-thirds line L32. The distance between the one-third line L31 and the two-thirds line L32 is d31, the distance between the one-third line L31 and the edge C11 is d31, and the distance between the two-thirds line L32 and the second center line L2 is d31. d31 is one-third of the display panel width D. One of the target gate driving circuits 101 can be set on the one-third line L31, and the other target gate driving circuit 101 can be set on the two-thirds line L32.

[0132] Similarly, for the second sub-display area A2, it includes a one-third line L41 and a two-thirds line L42, the distance between the one-third line L41 and the two-thirds line L42 is d31, the distance between the one-third line L41 and the edge C12 is d31, and the distance between the two-thirds line L42 and the second center line L2 is d31, which is one-third of the display panel width D. One of the target gate driving circuits 101 can be set at the one-third line L41, and the other target gate driving circuit 101 can be set at the two-thirds line L42.

[0133] The more gate driving circuits that output the same gate signal, the stronger the driving capability is. Moreover, the n target gate driving circuits 101 are evenly distributed, so that the delay and voltage drop of the output signal of the target gate driving circuit 101 can be minimized.

[0134] The more gate driving circuits that output the same gate signal, the stronger the driving capability is, and the more space is occupied. For example, in the case of taking both driving capability and layout design into consideration, n may be no greater than 4.

[0135] In some embodiments, the n target gate driving circuits 101 are all used to output the sweep signal SWEEP; or, the n target gate driving circuits 101 are all used to output the first light emitting control signal PAM_EM for controlling the amplitude modulation subcircuit in the pixel circuit.

[0136] That is to say, the target gate driving circuit 101 may be the seventh gate driving circuit 17 mentioned above, or the target gate driving circuit 101 may be the fifth gate driving circuit 15 mentioned above.

[0137] Compared with other gate driving circuits, the seventh gate driving circuit 17 and the fifth gate driving circuit 15 have relatively large parasitic capacitance, which will affect their driving capabilities. Therefore, setting multiple seventh gate driving circuits 17 or multiple fifth gate driving circuits 15 in the sub-display area can balance the driving capabilities of each gate driving circuit.

[0138] In some embodiments, the n target gate drive circuits 101 include n first gate drive circuits 11, and the gate signals PAM_S2 output by the n first gate drive circuits 11 are used to control the first data signal PAM_data to be written into the amplitude modulation sub-circuit 21; and / or, the n target gate drive circuits 101 include n second gate drive circuits 12, and the gate signals PWM_S2 output by the n second gate drive circuits 12 are used to control the second data signal PWM_data to be written into the pulse width modulation sub-circuit.

[0139] As introduced above, the writing of data signals has a great influence on the brightness. Therefore, setting multiple first gate driving circuits and / or multiple second gate driving circuits in the sub-display area can enhance the driving capability of the first gate driving circuit and / or the second gate driving circuit, and can achieve more effective control over the writing of data signals.

[0140] As an example, Fig.13 As shown, each sub-display area includes two first gate driving circuits 11 and two second gate driving circuits 12, and are arranged in the order of second gate driving circuit 12, first gate driving circuit 11, first center line L1, first gate driving circuit 11, and second gate driving circuit 12.

[0141] As another example, Fig.14 As shown, each sub-display area includes two first gate driving circuits 11 and two second gate driving circuits 12, and are arranged in the order of first gate driving circuit 11, second gate driving circuit 12, first center line L1, first gate driving circuit 11, and second gate driving circuit 12.

[0142] As another example, Fig.15As shown, each sub-display area includes two first gate driving circuits 11 and two second gate driving circuits 12, and are arranged in the order of first gate driving circuit 11, second gate driving circuit 12, first center line L1, second gate driving circuit 12, and first gate driving circuit 11.

[0143] As another example, Fig.16 As shown, each sub-display area includes two first gate driving circuits 11 and two second gate driving circuits 12, and are arranged in the order of second gate driving circuit 12, first gate driving circuit 11, first center line L1, second gate driving circuit 12, and first gate driving circuit 11.

[0144] The above are merely some examples and are not intended to limit the present application. The arrangement order of the plurality of first gate driving circuits and the plurality of second gate driving circuits may also be set in other ways, which are not listed one by one here.

[0145] In some embodiments, Fig.11 As shown, the display panel 100 includes two sub-display areas arranged in a first direction X, and each sub-display area includes a first center line L1. The two sub-display areas are a first sub-display area A1 and a second sub-display area A2, the first center line of the first sub-display area A1 is L11, and the first center line of the second sub-display area A2 is L12.

[0146] Along the first direction X, the two sub-display areas each include m gate driving circuits 10, the m gate driving circuits 10 are respectively K1-th gate driving circuit to Km-th gate driving circuit, the gate signal output by the Kj-th gate driving circuit in the first sub-display area and the Kj-th gate driving circuit in the second sub-display area is the same, m≥2, Kj is any one of K1 to Km;

[0147] In the first direction X, the K1th gate driving circuit to the Kmth gate driving circuit in the first sub-display area are arranged close to the second center line L2 in sequence, and the K1th gate driving circuit to the Kmth gate driving circuit in the second sub-display area are arranged away from the second center line L2 in sequence. The second center line L2 is the dividing line between the two sub-display areas.

[0148] Fig.11 In the figure, m is 7, indicating that the fourth gate driving circuit 14 is the K1th gate driving circuit, and the third gate driving circuit 13 is the Kmth gate driving circuit.

[0149] It is understandable that in the embodiment of the present application, the arrangement order of the gate driving circuits of the two sub-display areas is symmetrical, so that the transmission paths of the output signals of the gate driving circuits of the two sub-display areas are also symmetrical, which is more conducive to optimizing display uniformity.

[0150] Of course, the gate driving circuits may also be arranged in other orders.

[0151] As an example, in the same sub-display area, in the first direction, the third gate drive circuit 13 (output signal PAM_S1), the seventh gate drive circuit 17 (output signal SWEEP), the second gate drive circuit 12 (output signal PWM_S2), the first center line L1, the first gate drive circuit 11 (output signal PAM_S2), the sixth gate drive circuit 16 (output signal PWM_EM), the fifth gate drive circuit 15 (output signal PAM_EM), and the fourth gate drive circuit 14 (output signal PWM_S1) are arranged in order.

[0152] As another example, in the same sub-display area, in the first direction, the fourth gate drive circuit 14 (output signal PWM_S1), the second gate drive circuit 12 (output signal PWM_S2), the first center line L1, the first gate drive circuit 11 (output signal PAM_S2), the seventh gate drive circuit 17 (output signal SWEEP), the sixth gate drive circuit 16 (output signal PWM_EM), the fifth gate drive circuit 15 (output signal PAM_EM), and the third gate drive circuit 13 (output signal PAM_S1) are arranged in order.

[0153] As another example, in the same sub-display area, in the first direction, the fourth gate drive circuit 14 (output signal PWM_S1), the sixth gate drive circuit 16 (output signal PWM_EM), the fifth gate drive circuit 15 (output signal PAM_EM), the second gate drive circuit 12 (output signal PWM_S2), the first center line L1, the first gate drive circuit 11 (output signal PAM_S2), the seventh gate drive circuit 17 (output signal SWEEP), and the third gate drive circuit 13 (output signal PAM_S1) are arranged in order.

[0154] Only part of the arrangement is shown above, and the arrangement sequence of each gate driving circuit is not listed here one by one.

[0155] In some embodiments, Fig.11 As shown, the display panel 100 includes two sub-display areas arranged in a first direction X, and each sub-display area includes a first center line L1. The two sub-display areas are a first sub-display area A1 and a second sub-display area A2, the first center line of the first sub-display area A1 is L11, and the first center line of the second sub-display area A2 is L12.

[0156] The sub-display area includes a plurality of gate driving circuits 10 . In the first direction X, the plurality of gate driving circuits 10 in the same sub-display area are arranged at unequal intervals.

[0157] The circuit architectures of gate drive circuits used to provide different gate signals will be different, so the layout area occupied by gate drive circuits with different functions, or the number of signal lines required to be connected will be different. When the gate drive circuits are arranged at unequal intervals, it is easier to achieve a reasonable design for the layout of each gate drive circuit.

[0158] As an example, any two adjacent gate drive circuits 10 form a circuit group, the spacing between the two gate drive circuits 10 in at least one circuit group in the first direction X is d11, and the spacing between the two gate drive circuits 10 in at least another circuit group in the first direction X is d12, and d11≠d12.

[0159] Specifically, the spacing between each gate driving circuit can be set according to actual needs, and this application does not limit this.

[0160] As another example, any two adjacent gate driving circuits form a circuit group, and the pixel circuit columns ( Fig.17 The number of pixel circuit columns distributed between two gate driving circuits in at least another circuit group is m2, and m1≠m2.

[0161] In the case where multiple gate drive circuits 10 in the same sub-display area are arranged at unequal intervals, the spaces between the gate drive circuits are different. For larger spacings, the space between the gate drive circuits is larger, and more pixel circuit columns can be set in the space, so that each space can be reasonably utilized. For smaller spacings, the space between the gate drive circuits is smaller, and a small number of pixel circuit columns can be set in the space. If more pixel circuit columns are set in a small space, the pixel circuit columns will be too crowded, which will cause the signal to be easily crosstalked or interfered; or the pixel circuit size has to be reduced, resulting in reduced performance of the pixel circuit, and the embodiments of the present application can avoid the above situation.

[0162] In some embodiments, Figure 2 or Figure 4 As shown, the display area includes a pixel circuit 20, and the orthographic projection of the pixel circuit 20 on the plane where the display panel is located does not overlap with the orthographic projection of the gate driving circuit 10 on the plane where the display panel is located.

[0163] In the embodiment of the present application, the pixel circuits are no longer arranged in adjacent rows, but space is left between the rows of pixel circuits, so that there is space in the display area for placing the lower gate drive circuit, and the gate drive circuit can be set in the display area to achieve a borderless display.

[0164] In some embodiments, the sizes of the pixel circuits 20 in different areas are the same. For example, the size of the pixel circuits in the entire display area is reduced as a whole. After the size of the pixel circuits is reduced, there is a certain space between the columns of pixel circuits, and the gate driving circuit is arranged in the gap between the columns of pixel circuits.

[0165] If the size of the pixel circuit in only some areas is reduced, the driving capabilities of the pixel circuits in different areas will be different, resulting in poor display uniformity. In the embodiment of the present application, the size of the pixel circuit in the entire display area is reduced as a whole, and the sizes of the pixel circuits after reduction are still the same, so the driving capabilities of the pixel circuits in each area are still consistent, which will not affect the display uniformity.

[0166] The present application also provides a display device, including the display panel provided by the present application. Fig.18 , Fig.18 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.18 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Fig.18 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0167] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, It is characterized in that including a display area; A first center line, the width of the display panel in the first direction is D, the first center line extends along the second direction, the distance between the first center line and the first edge of the display panel in the first direction is d1, d1=D / 4, at least one gate driving circuit is disposed on both sides of the first center line in the first direction; the first direction intersects with the second direction; The gate driving circuit is located in the display area.

2. The display panel according to claim 1, It is characterized in that The distance between the second center line of the display panel and the first edge of the display panel in the first direction is d2, d2=D / 2, and at least one gate driving circuit is arranged between the first center line and the second center line.

3. The display panel according to claim 1, It is characterized in that The display panel includes N pixel circuit columns arranged in the first direction, and the pixel circuit columns include a plurality of pixel circuits arranged in the second direction; At least one gate driving circuit is disposed on both sides of the N / 4th pixel circuit column in the first direction, wherein N / 4 is an integer.

4. The display panel according to claim 3, It is characterized in that Along the first direction, at least one gate driving circuit is included between the N / 4th pixel circuit column and the N / 2th pixel circuit column, wherein N / 2 is an integer.

5. The display panel according to claim 1, It is characterized in that The display panel includes a separation area, the first center line is located in the separation area, at least one gate driving circuit is disposed on both sides of the separation area in the first direction, and a width of the separation area in the first direction is less than or equal to 625 um.

6. The display panel according to claim 5, It is characterized in that The display panel includes N pixel circuit columns arranged in the first direction, and the pixel circuit columns include a plurality of pixel circuits arranged in the second direction; The N / 4th pixel circuit row is located in the separation area.

7. The display panel according to claim 2, It is characterized in that The pixel circuit of the display panel includes an amplitude modulation subcircuit and a pulse width modulation subcircuit, and the gate drive circuit includes a first gate drive circuit and a second gate drive circuit. The gate signal output by the first gate drive circuit is used to control the first data signal to be written into the amplitude modulation subcircuit, and the gate signal output by the second gate drive circuit is used to control the second data signal to be written into the pulse width modulation subcircuit.

8. The display panel according to claim 7, It is characterized in that In the first direction, the first gate driving circuit is located on a side of the first center line close to the second center line, and the second gate driving circuit is located on a side of the first center line far from the second center line; Alternatively, in the first direction, the first gate driving circuit is located on a side of the first center line away from the second center line, and the second gate driving circuit is located on a side of the first center line close to the second center line.

9. The display panel according to claim 8, It is characterized in that In the first direction, the distance between the first gate driving circuit and the first center line is d3, and the distance between the second gate driving circuit and the first center line is d4, where d3=d4.

10. The display panel according to claim 8, It is characterized in that In the first direction, the distance between the first gate driving circuit and the first center line is d3, and the distance between the second gate driving circuit and the first center line is d4, where d3≠d4.

11. The display panel according to claim 10, It is characterized in that d3<d4.

12. The display panel according to claim 8, It is characterized in that In the first direction, among the input and output ends of the first gate drive circuit, the input end of the first gate drive circuit is closer to the first center line, and among the input and output ends of the second gate drive circuit, the input end of the second gate drive circuit is closer to the first center line.

13. The display panel according to claim 8, It is characterized in that The first gate driving circuit is connected to a plurality of first signal lines. In the first direction, the number of the first signal lines distributed on the side of the first gate driving circuit close to the first center line is n1, and the number of the first signal lines distributed on the side of the first gate driving circuit far from the first center line is n2, where n1<n2; The second gate driving circuit is connected to multiple second signal lines. In the first direction, the number of the second signal lines distributed on the side of the second gate driving circuit close to the first center line is n3, and the number of the second signal lines distributed on the side of the second gate driving circuit away from the first center line is n4, and n3<n4.

14. The display panel according to claim 1, It is characterized in that The gate driving circuit includes a first type of gate driving circuit and other types of gate driving circuits, and the gate signal output by the first type of gate driving circuit is used to control the data signal to be written into the pixel circuit; In the first direction, the distance between the first type of gate driving circuit and the first center line is smaller than the distance between the other types of gate driving circuits and the first center line.

15. The display panel according to claim 1, It is characterized in that The gate driving circuit includes a first type of gate driving circuit, a second type of gate driving circuit and a third type of gate driving circuit, wherein the gate signal output by the first type of gate driving circuit is used to control the data signal to be written into the pixel circuit, the gate signal output by the second type of gate driving circuit is used to control the reset signal to be written into the pixel circuit, and the third type of gate driving circuit is used to output a frequency sweeping signal and / or a light emitting control signal; In the first direction, the third type of gate driving circuit is located between the first type of gate driving circuit and the second type of gate driving circuit.

16. The display panel according to claim 15, It is characterized in that The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit, the second type of gate driving circuit includes a third gate driving circuit and a fourth gate driving circuit, the gate signal output by the third gate driving circuit is used to control the reset signal to be written into the amplitude modulation subcircuit, and the gate signal output by the fourth gate driving circuit is used to control the reset signal to be written into the pulse width modulation subcircuit; In the first direction, the third gate driving circuit and the fourth gate driving circuit are respectively located on two sides of the first center line.

17. The display panel according to claim 16, It is characterized in that The pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit, the third type of gate driving circuit includes a fifth gate driving circuit, a sixth gate driving circuit and a seventh gate driving circuit, the fifth gate driving circuit is used to output a first light-emitting control signal, the sixth gate driving circuit is used to output a second light-emitting control signal, the seventh gate driving circuit is used to output a frequency sweep signal, the fifth gate driving circuit is electrically connected to the amplitude modulation subcircuit, and the sixth gate driving circuit and the seventh gate driving circuit are electrically connected to the pulse width modulation subcircuit; In the first direction, the fifth gate driving circuit and the sixth gate driving circuit are adjacent to each other.

18. The display panel according to claim 17, It is characterized in that In the first direction, the fifth gate driving circuit and the sixth gate driving circuit are located on one side of the first center line, and the seventh gate driving circuit is located on the other side of the first center line.

19. The display panel according to claim 1, It is characterized in that The display panel includes two sub-display areas arranged in a first direction, and the sub-display areas include the first center line; The same sub-display area includes n target gate driving circuits that output the same gate signal, and the n target gate driving circuits in the sub-display area are evenly distributed in the first direction, and n≥2.

20. The display panel according to claim 19, It is characterized in that The n target gate drive circuits are all used to output a frequency sweep signal; Alternatively, the n target gate driving circuits are all used to output a first light emitting control signal for controlling an amplitude modulation subcircuit in a pixel circuit.

21. The display panel according to claim 19, It is characterized in that The n target gate driving circuits include n first gate driving circuits, and the gate signals output by the n first gate driving circuits are used to control the first data signal to be written into the amplitude modulation sub-circuit; And / or, the n target gate driving circuits include n second gate driving circuits, and the gate signals output by the n second gate driving circuits are used to control the second data signal to be written into the pulse width modulation sub-circuit.

22. The display panel according to claim 1, It is characterized in that The display panel includes two sub-display areas arranged in a first direction, and the sub-display areas include the first center line; Along the first direction, the two sub-display areas each include m gate driving circuits, the m gate driving circuits are respectively K1-th gate driving circuit to Km-th gate driving circuit, the gate signal output by the Kj-th gate driving circuit in the first sub-display area and the Kj-th gate driving circuit in the second sub-display area is the same, m≥2, Kj is any one of K1 to Km; In the first direction, the K1th gate driving circuit to the Kmth gate driving circuit in the first sub-display area are arranged close to the second center line in sequence, and the K1th gate driving circuit to the Kmth gate driving circuit in the second sub-display area are arranged away from the second center line in sequence, and the second center line is the dividing line between the two sub-display areas.

23. The display panel according to claim 1, It is characterized in that The display panel includes two sub-display areas arranged in a first direction, and the sub-display areas include the first center line; The sub-display area includes a plurality of gate driving circuits. In the first direction, the plurality of gate driving circuits in the same sub-display area are arranged at unequal intervals.

24. The display panel according to claim 23, It is characterized in that Any two adjacent gate drive circuits form a circuit group, the distance between the two gate drive circuits in at least one circuit group in the first direction is d11, and the distance between the two gate drive circuits in at least another circuit group in the first direction is d12, d11≠d12.

25. The display panel according to claim 23, It is characterized in that Any two adjacent gate drive circuits form a circuit group, the number of pixel circuit columns distributed between the two gate drive circuits in at least one circuit group is m1, and the number of pixel circuit columns distributed between the two gate drive circuits in at least another circuit group is m2, m1≠m2.

26. The display panel according to claim 1, It is characterized in that The display area includes a pixel circuit, and an orthographic projection of the pixel circuit on the plane where the display panel is located and an orthographic projection of the gate driving circuit on the plane where the display panel is located do not overlap.

27. The display panel according to claim 26, It is characterized in that The sizes of the pixel circuits in different areas are the same.

28. A display device, It is characterized in that Comprising the display panel as claimed in any one of claims 1-27.

Images