Passive feed-forward noise shaping SAR ADC structure and quantification method thereof

Abstract

The invention discloses a passive feed-forward noise shaping SAR ADC structure and a quantification method thereof. The structure comprises a second-order noise shaping circuit based on a charge pump, a sampling switch circuit, a DAC capacitor array, a six-input comparator and a logic control circuit. The method comprises the following steps: sampling an input analog signal to an upper pole plate of a DAC capacitor array; carrying out inter-board capacitor voltage switching processing according to the control signal, and outputting a successive approximation voltage signal; obtaining quantization residual voltage in inter-board capacitor voltage switching processing, performing second-order noise shaping filtering processing, and outputting a first-order integral voltage signal and a second-order integral voltage signal; comparing the successive approximation voltage signal, the first-order integral voltage signal and the second-order integral voltage signal to obtain a digital code; and carrying out inter-board capacitor voltage switching according to the digital code to obtain a quantization result. According to the embodiment of the invention, the power consumption of the SAR ADC structure can be reduced, and the quantization precision of the SAR ADC structure can be improved. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a passive feedforward noise shaping SAR ADC structure and a quantization method thereof. Background Art

[0002] The successive approximation register analog-to-digital converter (SAR ADC) mainly converts the continuous analog signal in nature into a digital signal that can be processed by the circuit system. However, its accuracy is difficult to reach more than 10 bits. Even if it can reach more than 10 bits, the energy efficiency will become very poor. In order to improve the accuracy, researchers proposed a noise shaping SAR ADC structure based on sigma-delta modulation. Therefore, the noise shaping SAR ADC (NS-SAR ADC) has the advantages of low power consumption and high precision. NS-SAR ADC is mainly divided into a basic SAR ADC module and a noise shaping module. From the position of noise feedback, the noise shaping structure can be divided into two types: feedforward and feedback; from whether there is an amplifier structure in the noise shaping module, it can be divided into active noise shaping and passive noise shaping. Related technology In order to improve the quantization accuracy and noise shaping capability, a group of integral capacitors are introduced. However, the large-sized input pair tube will not only increase the power consumption of the comparator, but also bring larger parasitic capacitance, which will not only introduce nonlinearity to reduce the ADC accuracy, but also reduce the speed of the comparator. Therefore, the noise suppression effect of the existing passive noise shaping module is not ideal.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a passive feedforward noise shaping SAR ADC structure and a quantization method thereof, which can reduce the power consumption of the SAR ADC structure and improve the quantization accuracy of the SAR ADC structure.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application provides a passive feedforward noise shaping SAR ADC structure, which includes a second-order noise shaping circuit based on a charge pump, a sampling switch circuit, a DAC capacitor array, a six-input comparator and a logic control circuit, wherein the output end of the sampling switch circuit is connected to the first input end of the DAC capacitor array, the first output end of the DAC capacitor array is connected to the first input end of the second-order noise shaping circuit based on the charge pump, the second output end of the DAC capacitor array is connected to the first input end of the six-input comparator, the output end of the second-order noise shaping circuit based on the charge pump is connected to the second input end of the six-input comparator, the output end of the six-input comparator is connected to the input end of the logic control circuit, the first output end of the logic control circuit is connected to the second input end of the DAC capacitor array, the second output end of the logic control circuit is connected to the second input end of the second-order noise shaping circuit based on the charge pump, and the third output end of the logic control circuit is connected to the third input end of the six-input comparator, wherein:

[0006] The sampling switch circuit is used to sample the input analog signal to the upper plate of the DAC capacitor array according to the sampling control signal;

[0007] The DAC capacitor array is used to perform inter-plate capacitor voltage switching processing according to the sampling control signal and output a successive approximation voltage signal;

[0008] The second-order noise shaping circuit based on the charge pump is used to perform second-order noise shaping filtering on the residual voltage of the upper plate of the DAC capacitor array, and output a first-order integrated voltage signal and a second-order integrated voltage signal;

[0009] The six-input comparator is used to compare and process the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a digital code;

[0010] The logic control circuit is used to control the working states of the DAC capacitor array, the charge pump-based second-order noise shaping circuit and the six-input comparator according to the digital code.

[0011] In some embodiments, the charge pump-based second-order noise shaping circuit includes a first charge pump, a first-order integrating capacitor, a second charge pump, a first noise sampling switch, a second noise sampling switch, a third noise sampling switch, a first second-order integrating switch, a second second-order integrating switch, a third second-order integrating switch, a first charge pump switch, a first-order integrating capacitor switch, a clearing switch, and a first-order integrating switch, wherein a first end of the first noise sampling switch is connected to the sampling switch circuit and the DAC capacitor array, a second end of the first noise sampling switch, a second end of the clearing switch, and a first end of the second noise sampling switch are connected to a first input end of the first charge pump, a first input end of the first charge pump is connected to a second output end of the first charge pump through the first charge pump switch, and a first output end of the first charge pump is connected to a first input end of the first charge pump through the first charge pump switch. The first input terminal of the second charge pump is connected to the second output terminal of the first charge pump through the third noise sampling switch, the second end of the second noise sampling switch, the first end of the first-order integration switch, the first end of the first second-order integration switch and the second input terminal of the first charge pump are connected, the second end of the first-order integration switch and the first end of the first-order integration capacitor are connected to the six-input comparator, the second end of the first second-order integration switch and the first end of the second second-order integration switch are connected to the six-input comparator, the second end of the second second-order integration switch is connected to the second input terminal of the second charge pump, the first input terminal of the second charge pump is connected to the second output terminal of the second charge pump through the first-order integration capacitor switch, and the first output terminal of the second charge pump is connected to the second output terminal of the second charge pump through the third second-order integration switch.

[0012] In some embodiments, the first charge pump and the second charge pump are both double charge pumps.

[0013] In some embodiments, the relationship between the capacitance value of the first charge pump, the first-order sampling capacitance value and the capacitance value constituting the second charge pump is specifically as follows:

[0014] 2C RES1 =2C RES2 =C INT1 =2C INT2a =2C INT2b =1 / 4C

[0015] In the above formula, C RES1 , C RES2 represents the capacitance value of the first charge pump, C INT1 Represents the first-order sampling capacitor value, C INT2a , C INT2b represents the capacitance value of the second charge pump, and C represents the capacitance value of the DAC capacitor array.

[0016] In some embodiments, the transfer function of the passive feedforward noise shaping SAR ADC structure is specifically as follows:

[0017] D out =V in +(1-0.8z -1 ) -2 Q

[0018] In the above formula, D out Represents the quantization result output, V in represents the analog signal, z -1 represents the delay of one cycle in the z-domain, and Q represents the non-ideal factor in the system.

[0019] To achieve the above object, another aspect of the embodiment of the present application provides a quantization method for a passive feedforward noise shaping SAR ADC structure, the method comprising the following steps:

[0020] The input analog signal is sampled to the upper plate of the DAC capacitor array according to the sampling control signal;

[0021] Perform inter-plate capacitor voltage switching processing according to the control signal and output a successive approximation voltage signal;

[0022] Acquire the quantized residual voltage in the inter-plate capacitor voltage switching process and perform a second-order noise shaping filter process, and output a first-order integrated voltage signal and a second-order integrated voltage signal;

[0023] Comparing and processing the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a digital code;

[0024] The inter-plate capacitor voltage is switched according to the digital code to obtain a quantized result.

[0025] In some embodiments, sampling the input analog signal to the upper plate of the DAC capacitor array according to the sampling control signal includes:

[0026] The analog signal is collected to the upper plate of the DAC capacitor array by closing the sampling switch circuit, and the upper plate of the DAC capacitor array is connected to the first positive input terminal of the six-input comparator;

[0027] Connecting a first-order integrating capacitor to the second positive input terminal of the six-input comparator, and collecting the voltage at the upper terminal of the first-order integrating capacitor to the six-input comparator;

[0028] The second charge pump is connected to the third positive input terminal of the six-input comparator, and the upper terminal voltage of the second charge pump is collected to the six-input comparator to complete the signal sampling work.

[0029] In some embodiments, the step of obtaining the quantized residual voltage in the inter-plate capacitor voltage switching process and performing a second-order noise shaping filter process to output a first-order integrated voltage signal and a second-order integrated voltage signal includes:

[0030] Acquiring a quantized residual voltage in the inter-plate capacitor voltage switching process;

[0031] Performing noise sampling processing on the quantized residual voltage to obtain a noise sampling signal;

[0032] Performing first-order noise integration and filtering processing on the noise sampling signal in sequence to obtain the first-order integrated voltage signal;

[0033] The noise sampling signal is sequentially subjected to second-order noise integration and filtering processing to obtain the second-order integrated voltage signal.

[0034] In some embodiments, the comparing and processing the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a digital code includes:

[0035] The six-input comparator compares the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a comparison result;

[0036] Based on the comparison result, switching the lower plate voltage of the DAC capacitor array is performed through a logic control circuit;

[0037] After switching, the six-input comparator compares and quantizes the voltage on the DAC capacitor array, the first-order integrating capacitor and the second charge pump to obtain a digital code.

[0038] In some embodiments, the first control clock signal, the second control clock signal, the third control clock signal, the fourth control clock signal and the fifth control clock signal are also included, wherein the first control clock signal is the control clock of the six-input comparator, the second control clock signal is the sampling clock of the DAC capacitor array, the third control clock signal is the control clock of the first charge pump, the fourth control clock signal is the control clock of the first-order integration capacitor, and the fifth control clock signal is the control clock of the second charge pump, wherein:

[0039] When the second control clock signal is at a low level, the DAC capacitor array is in a sampling phase, and when the second control clock signal is at a high level, the DAC capacitor array sampling ends;

[0040] When the first control clock signal is at a high level, the six-input comparator enters a comparison phase;

[0041] When the third control clock signal is at a high level, the first charge pump is turned on by the DAC capacitor array, and when the third control clock signal is at a low level, the first charge pump completes a double boost operation;

[0042] When the fourth control clock signal is at a high level, the first charge pump is turned on by the first-order integration capacitor to complete a first-order integration noise shaping operation;

[0043] When the fifth control clock signal is at a high level, the first charge pump and the second charge pump are turned on to achieve charge sharing. When the fifth control clock signal is at a low level, the second charge pump completes a double boost operation and a second-order integral noise shaping operation.

[0044] The embodiments of the present application include at least the following beneficial effects: The present application provides a passive feedforward noise shaping SAR ADC structure and a quantization method thereof. The scheme introduces a second-order noise shaping circuit based on a charge pump, and based on the charge pump boost principle in the noise sampling capacitor and the second-order integrating capacitor, compensates for the signal loss in the shaping process, reduces the output power consumption, and thereby reduces the width-to-length ratio between the input pairs of tubes of the multi-input comparator, while enhancing the noise suppression effect and improving the quantization accuracy of the passive feedforward noise shaping SAR ADC structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Schematic diagram of a passive feedforward noise shaping SAR ADC structure provided in an embodiment of the present application;

[0046] Figure 2 It is a schematic flow chart of the steps of a quantization method of a passive feedforward noise shaping SAR ADC structure provided in an embodiment of the present application;

[0047] Figure 3 is a schematic diagram of an existing feedforward noise shaping SAR ADC structure provided in an embodiment of the present application;

[0048] Figure 4 is a schematic diagram of a conventional first-order passive noise shaping SAR ADC structure provided in an embodiment of the present application;

[0049] Figure 5 is a schematic diagram of an existing classic second-order passive noise shaping SAR ADC structure provided in an embodiment of the present application;

[0050] Figure 6 1 is a schematic diagram of the structure of a second-order passive feedforward NS-SAR ADC based on a charge pump provided in an embodiment of the present application;

[0051] Figure 7Schematic diagram of signal flow of a second-order passive feedforward noise shaping SAR ADC provided in an embodiment of the present application;

[0052] Figure 8 This is a schematic diagram of the quantization timing of a second-order passive feedforward noise shaping SAR ADC provided in an embodiment of the present application;

[0053] Fig. 9 is a schematic diagram of a fast Fourier transform curve of a transient ADC output of a transistor-level simulation provided in an embodiment of the present application;

[0054] Fig.10 is a schematic diagram of a basic SAR ADC noise shaping structure based on 11-bit provided in an embodiment of the present application;

[0055] Fig.11 Schematic diagram of a 9-bit basic SAR ADC noise shaping structure provided in an embodiment of the present application.

[0056] Figure numerals: 1. sampling switch circuit; 2. DAC capacitor array; 3. six-input comparator; 4. logic control circuit; 5. second-order noise shaping circuit based on charge pump; 511. first charge pump; 512. first-order integrating capacitor; 513. second charge pump. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0058] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0059] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0061] Before describing the embodiments of the present application in detail, some nouns and terms involved in the embodiments of the present application are first described. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0062] The successive approximation register analog-to-digital converter (SAR ADC) mainly converts continuous analog signals in nature into digital signals that can be processed by circuit systems. Due to the unique quantization method and circuit structure of the successive approximation register, it has always had great advantages and potential in energy efficiency, and the internal digital structure can continue to benefit from the shrinking of CMOS process. However, its accuracy is difficult to reach more than 10 bits, and even if it can reach more than 10 bits, the energy efficiency will become very poor. In order to improve the accuracy, researchers proposed a noise shaping SAR ADC structure based on sigma-delta modulation. Therefore, the noise shaping SAR ADC (NS-SAR ADC) is naturally low Power consumption and high precision advantages. Such as Figure 3 As shown in the figure, in the feedforward NS-SAR ADC structure first proposed, the active integral filter based on the amplifier structure constructs a clear noise transfer function (NTF), which brings a more obvious low-frequency suppression effect to the design of the NTF, thereby improving the performance of noise shaping and ADC accuracy. However, the amplifier circuit increases the complexity of the entire system design and the additional power consumption. At the same time, the amplifier is more sensitive to process changes, and the change of gain will also reduce the stability of the circuit.

[0063] NS-SAR ADC is mainly divided into basic SAR ADC module and noise shaping module. In the whole NS-SAR ADC system, the power consumption of noise shaping module accounts for a large proportion, and the impact on accuracy is also relatively large. Therefore, the design of noise shaping module becomes the design bottleneck of noise shaping SAR ADC. At present, designers have proposed various noise shaping structures: from the position of noise feedback, noise shaping structure can be divided into feedforward and feedback types; from whether there is an amplifier structure in the noise shaping module, it can be divided into active noise shaping and passive noise shaping.

[0064] So if Figure 4In order to improve quantization accuracy and reduce power consumption, the classic passive feedforward noise shaping SAR ADC has gradually attracted attention. This structure only requires capacitors with a certain ratio and a few switches. However, due to this structure, only one zero of 0.75 can be constructed in the noise transfer function, and at the same time there is a pole of 0.75, resulting in the best shaping effect of this structure being only 12dB.

[0065] like Figure 5 As shown in Figure 2, in order to improve the noise shaping capability, the second-order passive feedforward NS-SAR ADC Figure 4 A set of integral capacitors C is added to the structure int2 , and the comparator is changed to six inputs. This structure constructs two zeros at 0.75 in the noise transfer function, realizes second-order noise shaping, and achieves -24dB noise suppression at DC. However, this NTF requires the width-to-length ratio between the three pairs of input pairs of the comparator to meet the following requirements: 1:4:16. Large-sized input pairs will not only increase the power consumption of the comparator, but also bring about greater parasitic capacitance, which will not only introduce nonlinearity and reduce ADC accuracy, but also reduce the speed of the comparator. This is also an important bottleneck that limits passive noise shaping.

[0066] Therefore, there are some deficiencies in the related art, such as poor noise suppression effect of the passive noise shaping module and excessively large width-to-length ratio between input pairs of tubes of the multi-input comparator.

[0067] In view of this, a passive feedforward noise shaping SAR ADC structure is provided in an embodiment of the present application. Through the charge pump boost principle in the noise shaping module, the noise sampling capacitor and the second-order integrating capacitor, the signal loss in the shaping process is compensated, thereby reducing the width-to-length ratio between the input pairs of tubes of the multi-input comparator, and enhancing the noise suppression effect.

[0068] Reference Figure 1 , Figure 1 A schematic diagram of a passive feedforward noise shaping SAR ADC structure provided by an embodiment of the present invention, referring to Figure 1The structure includes a second-order noise shaping circuit 5 based on a charge pump, a sampling switch circuit 1, a DAC capacitor array 2, a six-input comparator 3 and a logic control circuit 4, wherein the output end of the sampling switch circuit is connected to the first input end of the DAC capacitor array, the first output end of the DAC capacitor array is connected to the first input end of the second-order noise shaping circuit based on the charge pump, the second output end of the DAC capacitor array is connected to the first input end of the six-input comparator, the output end of the first-order noise shaping circuit based on the charge pump is connected to the second input end of the six-input comparator, the output end of the second-order noise shaping circuit based on the charge pump is connected to the third input end of the six-input comparator, the output end of the six-input comparator is connected to the input end of the logic control circuit, the first output end of the logic control circuit is connected to the second input end of the DAC capacitor array, the second output end of the logic control circuit is connected to the second input end of the second-order noise shaping circuit based on the charge pump, and the third output end of the logic control circuit is connected to the third input end of the six-input comparator, wherein:

[0069] The sampling switch circuit is used to sample the input analog signal to the upper plate of the DAC capacitor array according to the sampling control signal;

[0070] The DAC capacitor array is used to perform inter-plate capacitor voltage switching processing according to the sampling control signal and output a successive approximation voltage signal;

[0071] The second-order noise shaping circuit based on the charge pump is used to perform second-order noise shaping filtering on the residual voltage of the upper plate of the DAC capacitor array, and output a first-order integrated voltage signal and a second-order integrated voltage signal;

[0072] The second-order noise shaping circuit based on the charge pump includes a first charge pump 511, a first-order integrating capacitor 512, a second charge pump 513, a first noise sampling switch Φ NS11 , the second noise sampling switch Φ NS12 、The third noise sampling switch Φ NS13 、First and second order integral switch Φ NS31 , the second second-order integral switch Φ NS32 、Third second-order integral switch Φ NS33 , the first charge pump switch Φ NS1b , first-order integrating capacitor switch Φ NS2b , reset switch Φ RST and first-order integrating switch Φ NS2, wherein the first end of the first noise sampling switch is connected to the sampling switch circuit and the DAC capacitor array, the second end of the first noise sampling switch, the second end of the zeroing switch, the first end of the second noise sampling switch and the first input end of the first charge pump are connected, the first input end of the first charge pump is connected to the second output end of the first charge pump through the first charge pump switch, the first output end of the first charge pump is connected to the second output end of the first charge pump through the third noise sampling switch, the second end of the second noise sampling switch, the first end of the first-order integration switch, the first end of the first second-order integration switch and the second input end of the first charge pump are connected, the second end of the first second-order integration switch, the first end of the first-order integration capacitor and the six-input comparator are connected, the second end of the first second-order integration switch and the first end of the second second-order integration switch are connected to the six-input comparator, the second end of the second second-order integration switch is connected to the second input end of the second charge pump, the first input end of the second charge pump is connected to the second output end of the second charge pump through the first-order integration capacitor switch, and the first output end of the second charge pump is connected to the second output end of the second charge pump through the third second-order integration switch.

[0073] It should be further explained that both the first charge pump and the second charge pump are double charge pumps.

[0074] The six-input comparator is used for comparing the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a digital code;

[0075] The logic control circuit is used for controlling the working states of the DAC capacitor array, the second-order noise shaping circuit based on the charge pump and the six-input comparator according to the digital code.

[0076] In this embodiment, the DAC capacitor array switches the lower plate switch of the capacitor, changes the upper plate voltage of the capacitor array, and then makes the upper plate output a successive approximation voltage. The second-order noise shaping structure based on the charge pump is used for the second-order noise shaping filtering of the residual voltage of the DAC upper plate. The filtered output includes a first-order integral voltage and a second-order integral voltage. The successive approximation voltage, the first-order integral voltage and the second-order integral voltage of the DAC capacitor array are further compared together through a six-input comparator to output a digital code. The logic control circuit is used to control the working state of the DAC capacitor array, the second-order noise shaping module and the comparator module according to the comparator result.

[0077] In summary, if Figure 6 As shown, Figure 6The proposed second-order dual charge pump passive feedforward NS-SAR ADC structure is demonstrated. For ease of description, only the single-ended structure is demonstrated here. The actual circuit design is based on the fully differential structure of the 10-bit SAR ADC. The embodiment of the present invention redesigns the structure of the sampling capacitor and the second-order shaping capacitor in the noise shaping module based on the traditional second-order passive feedforward noise shaping SAR ADC. Among them, the introduction of the double charge pump into the noise sampling capacitor and the second-order noise shaping capacitor can reduce the relative gain ratio of the input end of the traditional comparator from 1:5:25 to 1:2.5:6.25, greatly reducing the power consumption of the comparator. At the same time, the size of the capacitance value in the structure is adjusted, and the size relationship between the capacitance value of the first charge pump, the first-order sampling capacitance value and the capacitance value constituting the second charge pump is specifically shown as follows:

[0078] 2C RES1 =2C RES2 =C INT1 =2C INT2a =2C INT2b =1 / 4C

[0079] In the above formula, C RES1 , C RES2 represents the capacitance value of the first charge pump, C INT1 Represents the first-order sampling capacitor value, C INT2a , C INT2b represents the capacitance value of the second charge pump, and C represents the capacitance value of the DAC capacitor array.

[0080] The first charge pump is a sampling noise capacitor, the first-order integrating capacitor is a first-order noise shaping capacitor, and the second charge pump is a second-order noise shaping capacitor.

[0081] like Figure 7 As shown in Figure 1, the internal signal flow diagram of the designed second-order passive feedforward noise shaping SAR ADC during the quantization process is shown. The zero point of the transfer function is determined by the ratio of the capacitors. RES1 =2C RES2 =C INT1 =2C INT2a =2C INT2b =1 / 4C, it can be deduced that the signal transfer system function is:

[0082] D out =V in +(1-0.8z -1 ) -2 Q

[0083] In the above formula, D out Represents the quantization result output, V in represents the analog signal, z -1represents the delay of one cycle in the z-domain, and Q represents the non-ideal factor in the system.

[0084] Q represents the non-ideal factors in the system, including comparator offset, noise, etc. The noise transfer function NFT = (1-0.8z -1 ) -2 This structure pushes the zero point in the noise transfer function NTF to 0.8, enhancing the effect of noise shaping and thus improving the quantization accuracy of the ADC.

[0085] See also Figure 2 The embodiment of the present application further provides a quantization method of a passive feedforward noise shaping SAR ADC structure, which can realize the above-mentioned passive feedforward noise shaping SAR ADC structure, and the method includes:

[0086] S100, sampling the input analog signal to the upper plate of the DAC capacitor array according to the sampling control signal;

[0087] It should be noted that, in some embodiments, step S100 may include: S110, collecting the analog signal to the upper plate of the DAC capacitor array by closing the sampling switch circuit, and connecting the upper plate of the DAC capacitor array to the first positive input terminal of the six-input comparator; S120, connecting the first-order integrating capacitor to the second positive input terminal of the six-input comparator, and collecting the upper end voltage of the first-order integrating capacitor to the six-input comparator; S130, connecting the second charge pump to the third positive input terminal of the six-input comparator, and collecting the upper end voltage of the second charge pump to the six-input comparator to complete the signal sampling work.

[0088] S200, performing inter-plate capacitor voltage switching processing according to the control signal, and outputting a successive approximation voltage signal;

[0089] S300, obtaining the quantized residual voltage in the inter-plate capacitor voltage switching process and performing a second-order noise shaping filter process, and outputting a first-order integrated voltage signal and a second-order integrated voltage signal;

[0090] It should be noted that, in some embodiments, step S300 may include: S310, obtaining the quantized residual voltage in the inter-plate capacitor voltage switching process; S320, performing noise sampling processing on the quantized residual voltage to obtain a noise sampling signal; S330, performing first-order noise integration and filtering processing on the noise sampling signal in sequence to obtain a first-order integrated voltage signal; S340, performing second-order noise integration and filtering processing on the noise sampling signal in sequence to obtain a second-order integrated voltage signal.

[0091] S400, comparing and processing the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a digital code;

[0092] It should be noted that, in some embodiments, step S400 may include: S410, comparing and processing the successive approximation voltage signal, the first-order integral voltage signal and the second-order integral voltage signal through a six-input comparator to obtain a comparison result; S420, switching the lower plate voltage of the DAC capacitor array through a logic control circuit based on the comparison result; S430, after switching, comparing and quantizing the voltage on the DAC capacitor array, the first-order integral capacitor and the second charge pump through a six-input comparator to obtain a digital code.

[0093] S500, switching the inter-plate capacitance voltage according to the digital code to obtain a quantized result;

[0094] In this embodiment, during the sampling phase, the switch circuit is closed and the analog signal V in+ The voltage V on the first-order noise shaping capacitor is collected through the switch circuit and connected to the positive electrode of the six-input comparator with a relative gain of 1. CINT1+ and the voltage V on the second-order noise shaping capacitor CINT2+ The capacitor array is connected to the ports with positive relative gain of 2.5 and 6.25 respectively. in+ of sampling.

[0095] After sampling, the six-input comparator directly compares the voltages at the positive and negative terminals, and the comparison results are input to the logic control circuit, where the voltage of the lower plate of the DAC capacitor array is switched through logic control, thereby changing the voltage of the upper plate of the capacitor array. After that, the comparator continues to compare and quantize the voltages on the DAC capacitor array, the first-order integrating capacitor, and the second charge pump, and finally quantizes the input analog signal into a 10-bit digital number.

[0096] After the quantization is completed, the DAC is controlled by logic control to perform voltage inversion again, and then C RES Sampling it, then C RES Using the charge pump principle to boost voltage, C INT1 and C INT2 The charge is shared in turn, and finally C INT2 The charge pump principle is also used to boost the voltage. Finally, the noise shaping module completes the integration of the last quantization error and prepares for the next quantization.

[0097] In the module, the sampling switch circuit is mainly composed of a bootstrap circuit, the comparator adopts a traditional six-input strongARM Latch comparator, and the capacitors in the DAC capacitor array and the noise shaping module are all composed of unit capacitors. In the present invention, a 4μm×4μm MIM capacitor is used based on the SMIC 0.18μm CMOS process, and the capacitance value is 15.5fF.

[0098] In addition, the embodiment of the present invention further includes a first control clock signal, a second control clock signal, a third control clock signal, a fourth control clock signal and a fifth control clock signal, wherein the first control clock signal is a control clock of the six-input comparator, the second control clock signal is a sampling clock of the DAC capacitor array, the third control clock signal is a control clock of the first charge pump, the fourth control clock signal is a control clock of the first-order integration capacitor, and the fifth control clock signal is a control clock of the second charge pump, wherein:

[0099] When the second control clock signal is at a low level, the DAC capacitor array is in a sampling phase, and when the second control clock signal is at a high level, the DAC capacitor array sampling ends;

[0100] When the first control clock signal is at a high level, the six-input comparator enters a comparison phase;

[0101] When the third control clock signal is at a high level, the first charge pump is turned on by the DAC capacitor array, and when the third control clock signal is at a low level, the first charge pump completes a double boost operation;

[0102] When the fourth control clock signal is at a high level, the first charge pump and the first-order integration capacitor are turned on to complete the first-order integration noise shaping operation;

[0103] When the fifth control clock signal is at a high level, the first charge pump and the second charge pump are turned on to realize charge sharing. When the fifth control clock signal is at a low level, the second charge pump completes a double boost operation and a second-order integral noise shaping operation.

[0104] Specifically, Figure 8 As shown, during the entire ADC operation, it is mainly controlled by five clocks, namely the first control clock signal CLK, the second control clock signal CLK S , the third control clock signal Φ NS1 , the fourth control clock signal Φ NS2 and the fifth control clock signal Φ NS3 Among them, CLK is the control clock of the comparator, CLK S is the sampling clock of the ADC, and the frequency of this clock is also equal to the sampling frequency and data output frequency of the entire ADC. NS1 , Φ NS2 and Φ NS3 They are sampling noise capacitor C RES , first-order noise shaping capacitor C INT1 and the second-order noise shaping capacitor C INT2 The control clock of NS1b Φ NS1 The opposite of Φ NS3b Φ NS3The opposite of Φ RST It is a zeroing switch. When the circuit is started, it is at a high level to clear the charge of the noise sampling capacitor, and then it remains at a low level.

[0105] 1) When CLK S When CLK is low, the ADC is in the sampling phase. At this time, the switch circuit is closed and the upper plates of all DAC capacitors sample the input signal. S When it is high, sampling ends, and the six-input comparator directly compares the voltage on the DAC and the first-order voltage and second-order voltage of the noise shaping module.

[0106] 2) When CLK is high, the six-input comparator makes a comparison. If the positive end is greater than the negative end, the output result is 1; if the positive end is less than the negative end, the output result is 0. At the same time, the DAC performs voltage conversion according to the comparator result and SAR logic. It is quantized in sequence until the tenth bit of data is quantized. Then, according to the quantization result, the voltage of the DAC is changed again to obtain the residual voltage V RES .

[0107] 3)Φ NS1 is high level, C RES The DAC capacitor is turned on to complete the sampling of the residual voltage, and then Φ NS1 is low level, Φ NS1b When the bit is high, the charge pump starts to perform a 2x boost operation.

[0108] 4)Φ NS2 is high, making the sampling capacitor C RES With the first-order integrating capacitor C INT1 Turn on to complete the first-order integral noise shaping.

[0109] 5)Φ NS3 is high, making the sampling capacitor C RES With the second-order integrating capacitor C INT2 conduction, complete charge sharing, and then Φ NS3 Drop to low level, Φ NS3b When the voltage is high, the charge pump starts to perform a 2x boost operation and finally completes the second-order integral noise shaping.

[0110] 6) In the Nth quantization cycle, the residual integrated voltage of the N-1 cycle participates in the quantization process of the entire noise shaping SAR ADC through charge sharing of the first-order and second-order integration capacitors.

[0111] In summary, the embodiment of the present invention outputs a successive approximation voltage through a DAC capacitor array; a second-order passive noise shaping module based on a charge pump utilizes charge sharing to perform noise sampling on the quantization residual voltage of the DAC capacitor array, and then performs first-order noise integration and second-order noise integration in sequence, and finally achieves filtering of the quantization noise and outputs a first-order noise integration voltage and a second-order noise integration voltage; the successive approximation voltage, the first-order integration voltage and the second-order integration voltage of the DAC capacitor array are compared together through a six-input comparator, and a digital code is output; according to the digital code, the voltage of the DAC capacitor array is switched through a logic module to complete a primary quantization work of the passive second-order noise shaping SAR ADC structure.

[0112] Finally, it should be noted that the noise shaping SAR ADC structure of the present invention is designed based on the SMIC 0.18μm CMOS process. Its supply voltage is 1.2V and the sampling frequency is 2MHz. When the oversampling rate is 8 and the input signal is a 93.75kHz, -0.06dBFS sinusoidal signal, Fig. 9 The 4096-point fast Fourier transform (FFT) curve of the transient ADC output of the transistor-level simulation is shown. The effective number of bits (ENOB) of the noise-shaping SAR ADC is 14.12 bits, the spurious-free dynamic range (SFDR) is 97.16dB, and the power consumption is about 56.8μW. According to the FoM definition, the Walden FoM of the second-order passive feedforward NS-SAR ADC can be calculated to be 3.19fJ / conv, and the corresponding Schreier FoM is 180.18dB.

[0113] In addition to the methods mentioned in this embodiment, the following transformations can also be made: For a basic SAR ADC with an 11-bit structure, the entire noise shaping SAR ADC structure is as follows: Fig.10 As shown, the main need is to increase the SAR ADC to 11 bits, and still keep the capacitance value in the noise shaping structure to meet the relationship: 2C RES1 =2C RES2 =C INT1 =2C INT2a =2C INT2b =1 / 4C, where C is the total capacitance of the DAC. For a 9-bit basic SAR ADC, the entire noise shaping SAR ADC structure is as follows: Fig.11 As shown, the main need is to reduce the SAR ADC to 9 bits, and still keep the capacitance value in the noise shaping structure to meet the relationship: 2C RES1 =2C RES2 =C INT1 =2C INT2a =2C ENT2b=1 / 4C, where C is the total capacitance of the DAC. At the same time, for basic SAR ADCs of other precisions, such as higher precision 12-bit, 13-bit, 14-bit, etc. and lower precision 8-bit, 7-bit SAR ADC, etc., in short, the noise shaping structure can be applied to basic SAR ADCs of arbitrary precision.

[0114] The embodiments of the present invention have the following improvements over the prior art:

[0115] 1) Due to the sampling capacitor C RES and the second-order integrating capacitor C INT2 The charge pump technology with a 2x gain is used everywhere. In the embodiment of the present invention, the relative gain of the passive integrator is provided by two groups of charge pumps and a multi-input comparator: the relative gain provided by the charge pump on the sampling capacitor compensates for the signal loss, and the second group of charge pumps is applied to the second-order integration capacitor C INT2 The relative gain provided above compensates for the integral loss, reducing the width-to-length ratio of the three pairs of input tubes of the comparator to 1:2.5:6.25, avoiding the use of large-size input tubes and reducing the power consumption of the comparator.

[0116] 2) Due to the use of 2x charge pump technology, the capacitance value of the noise shaping module can be adjusted so that the second-order zero point of the NTF is pushed to 0.8, thereby obtaining a more significant low-frequency noise suppression effect.

[0117] 3) Due to the use of charge pump technology in the noise shaping module, the designed second-order NS-SAR ADC architecture only adds 0.75C times the capacitance of the basic SAR ADC, where C is the capacitance value of the DAC capacitor array in the SAR ADC. Smaller capacitance saves ADC power consumption and area.

[0118] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0119] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A passive feedforward noise shaping SAR ADC structure, characterized in that: The structure includes a second-order noise shaping circuit based on a charge pump, a sampling switch circuit, a DAC capacitor array, a six-input comparator and a logic control circuit, wherein the output end of the sampling switch circuit is connected to the first input end of the DAC capacitor array, the first output end of the DAC capacitor array is connected to the first input end of the second-order noise shaping circuit based on the charge pump, the second output end of the DAC capacitor array is connected to the first input end of the six-input comparator, the output end of the second-order noise shaping circuit based on the charge pump is connected to the second input end of the six-input comparator, the output end of the six-input comparator is connected to the input end of the logic control circuit, the first output end of the logic control circuit is connected to the second input end of the DAC capacitor array, the second output end of the logic control circuit is connected to the second input end of the second-order noise shaping circuit based on the charge pump, and the third output end of the logic control circuit is connected to the third input end of the six-input comparator, wherein: The sampling switch circuit is used to sample the input analog signal to the upper plate of the DAC capacitor array according to the sampling control signal; The DAC capacitor array is used to perform inter-plate capacitor voltage switching processing according to the sampling control signal and output a successive approximation voltage signal; The second-order noise shaping circuit based on the charge pump is used to perform second-order noise shaping filtering on the residual voltage of the upper plate of the DAC capacitor array, and output a first-order integrated voltage signal and a second-order integrated voltage signal; The six-input comparator is used to compare and process the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a digital code; The logic control circuit is used to control the working states of the DAC capacitor array, the charge pump-based second-order noise shaping circuit and the six-input comparator according to the digital code.

2. The structure according to claim 1, characterized in that: The second-order noise shaping circuit based on the charge pump comprises a first charge pump, a first-order integrating capacitor, a second charge pump, a first noise sampling switch, a second noise sampling switch, a third noise sampling switch, a first second-order integrating switch, a second second-order integrating switch, a third second-order integrating switch, a first charge pump switch, a first-order integrating capacitor switch, a clearing switch and a first-order integrating switch, wherein a first end of the first noise sampling switch is connected to the sampling switch circuit and the DAC capacitor array, a second end of the first noise sampling switch, a second end of the clearing switch, a first end of the second noise sampling switch and a first input end of the first charge pump are connected, a first input end of the first charge pump is connected to a second output end of the first charge pump through the first charge pump switch, and a first output end of the first charge pump is connected to a second output end of the first charge pump through the first charge pump switch. The three noise sampling switches are connected to the second output terminal of the first charge pump, the second terminal of the second noise sampling switch, the first terminal of the first-order integration switch, the first terminal of the first second-order integration switch and the second input terminal of the first charge pump are connected, the second terminal of the first-order integration switch and the first terminal of the first-order integration capacitor are connected to the six-input comparator, the second terminal of the first second-order integration switch and the first terminal of the second second-order integration switch are connected to the six-input comparator, the second terminal of the second second-order integration switch is connected to the second input terminal of the second charge pump, the first input terminal of the second charge pump is connected to the second output terminal of the second charge pump through the first-order integration capacitor switch, and the first output terminal of the second charge pump is connected to the second output terminal of the second charge pump through the third second-order integration switch.

3. The structure according to claim 2, characterized in that: The first charge pump and the second charge pump are both double charge pumps.

4. The structure according to claim 2, characterized in that: The relationship between the capacitance value of the first charge pump, the first-order sampling capacitance value and the capacitance value constituting the second charge pump is specifically as follows: 2C RES1 =2C RES2 =C INT1 =2C INT2a =2C INT2b =1 / 4C In the above formula, C RES1 , C RES2 represents the capacitance value of the first charge pump, C INT1 Represents the first-order sampling capacitor value, C INT2a , C INT2b represents the capacitance value of the second charge pump, and C represents the capacitance value of the DAC capacitor array.

5. The structure according to claim 1, characterized in that: The transfer function of the passive feedforward noise shaping SAR ADC structure is specifically as follows: D out =V in +(1-0.8z -1 ) -2 Q In the above formula, D out Represents the quantization result output, V in represents the analog signal, z -1 represents the delay of one cycle in the z-domain, and Q represents the non-ideal factor in the system.

6. A quantization method for a passive feedforward noise shaping SAR ADC structure, characterized in that: The method comprises the following steps: The input analog signal is sampled to the upper plate of the DAC capacitor array according to the sampling control signal; Perform inter-plate capacitor voltage switching processing according to the control signal and output a successive approximation voltage signal; Acquire the quantized residual voltage in the inter-plate capacitor voltage switching process and perform a second-order noise shaping filter process, and output a first-order integrated voltage signal and a second-order integrated voltage signal; Comparing and processing the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a digital code; The inter-plate capacitor voltage is switched according to the digital code to obtain a quantized result.

7. The method according to claim 6, characterized in that The method of sampling the input analog signal to the upper plate of the DAC capacitor array according to the sampling control signal includes: The analog signal is collected to the upper plate of the DAC capacitor array by closing the sampling switch circuit, and the upper plate of the DAC capacitor array is connected to the first positive input terminal of the six-input comparator; Connecting a first-order integrating capacitor to the second positive input terminal of the six-input comparator, and collecting the voltage at the upper terminal of the first-order integrating capacitor to the six-input comparator; The second charge pump is connected to the third positive input terminal of the six-input comparator, and the upper terminal voltage of the second charge pump is collected to the six-input comparator to complete the signal sampling work.

8. The method according to claim 6, characterized in that The step of obtaining the quantized residual voltage in the inter-plate capacitor voltage switching process and performing a second-order noise shaping filter process to output a first-order integrated voltage signal and a second-order integrated voltage signal includes: Acquiring a quantized residual voltage in the inter-plate capacitor voltage switching process; Performing noise sampling processing on the quantized residual voltage to obtain a noise sampling signal; Performing first-order noise integration and filtering processing on the noise sampling signal in sequence to obtain the first-order integrated voltage signal; The noise sampling signal is sequentially subjected to second-order noise integration and filtering processing to obtain the second-order integrated voltage signal.

9. The method according to claim 7, characterized in that: The step of comparing and processing the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a digital code comprises: The six-input comparator compares the successive approximation voltage signal, the first-order integrated voltage signal and the second-order integrated voltage signal to obtain a comparison result; Based on the comparison result, switching the lower plate voltage of the DAC capacitor array is performed through a logic control circuit; After switching, the six-input comparator compares and quantizes the voltage on the DAC capacitor array, the first-order integrating capacitor and the second charge pump to obtain a digital code.

10. The method according to claim 9, characterized in that It also includes a first control clock signal, a second control clock signal, a third control clock signal, a fourth control clock signal and a fifth control clock signal, wherein the first control clock signal is the control clock of the six-input comparator, the second control clock signal is the sampling clock of the DAC capacitor array, the third control clock signal is the control clock of the first charge pump, the fourth control clock signal is the control clock of the first-order integration capacitor, and the fifth control clock signal is the control clock of the second charge pump, wherein: When the second control clock signal is at a low level, the DAC capacitor array is in a sampling phase, and when the second control clock signal is at a high level, the DAC capacitor array sampling ends; When the first control clock signal is at a high level, the six-input comparator enters a comparison phase; When the third control clock signal is at a high level, the first charge pump is turned on by the DAC capacitor array, and when the third control clock signal is at a low level, the first charge pump completes a double boost operation; When the fourth control clock signal is at a high level, the first charge pump is turned on by the first-order integration capacitor to complete a first-order integration noise shaping operation; When the fifth control clock signal is at a high level, the first charge pump and the second charge pump are turned on to achieve charge sharing. When the fifth control clock signal is at a low level, the second charge pump completes a double boost operation and a second-order integral noise shaping operation.

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