Spread spectrum induced polarization controllable transmitting and weak signal receiving method and system

Abstract

The invention relates to the technical field of electrical prospecting, in particular to a spread spectrum induced polarization controllable transmitting and weak signal receiving method and system. The system comprises a transmitter and a receiver, the transmitter comprises a master control module, a waveform generation module and an isolation driving module, the waveform generation module is based on an FPGA, high-quality clock supply is ensured through clock management, a specific frequency signal synchronous or asynchronous with standard time is flexibly generated by using a soft core processor and a synchronous frequency division sub-module, and the signal is transmitted to the isolation driving module. Dead time processing is added to optimize inverter control; the isolation driving module ensures that the signal safely drives the IGBT inverter; the receivers are deployed in acquisition stations, each station is provided with at least three receivers, the middle receiver integrates current and voltage measurement, and the receivers on the two sides concentrate on voltage measurement. According to the technical scheme, the reliability and diversity of signal sending and the effectiveness of signal receiving can be improved.

Description

Technical Field

[0001] The invention relates to the technical field of electrical prospecting, and in particular to a spread spectrum induced polarization controllable emission and weak signal receiving method and system. Background Art

[0002] In the field of geophysical exploration, electrical exploration technology is an important exploration method. It transmits electric currents of specific frequencies into the ground and measures the response of the underground medium to these currents to infer the physical properties of underground structures and rocks. Traditional electrical exploration equipment generally faces problems such as poor signal synchronization, insufficient control signal accuracy, and low signal reception efficiency under complex geological conditions. These problems limit the accuracy of exploration data and the efficiency of exploration operations.

[0003] Existing spread spectrum IP exploration systems usually include a transmitter and a receiver. The transmitter is responsible for generating and sending electrical signals of a specific frequency, while the receiver is responsible for capturing these signals and converting them into geological structure information. However, there are the following technical challenges in practical applications: 1. In complex geological environments, signal synchronization is critical to ensuring data accuracy. In traditional systems, signal synchronization generally relies on simple clock signals, which is difficult to achieve high-precision synchronization in multi-channel systems.

[0004] 2. Existing waveform control signal generation methods usually rely on hardware circuits. These circuits fix the types and parameters of waveforms during design and cannot adapt to the needs of different geological conditions and exploration targets, which affects the diversity and accuracy of exploration data.

[0005] 3. Ordinary transmitters usually have problems with low output voltage and small transmission current, which limits the penetration ability and coverage of exploration signals, especially in deep or complex geological conditions.

[0006] 4. In long-distance or large-area exploration, how to efficiently use receivers for data collection is a technical challenge. Summary of the invention

[0007] The purpose of the present invention is to provide a method and system for spread spectrum induced polarization controllable transmission and weak signal reception, which can improve the reliability and diversity of signal transmission and the effectiveness of signal reception.

[0008] To achieve the above objectives, in a first aspect, the embodiments of the present disclosure provide a spread spectrum electromagnetic controllable transmission and weak signal receiving system, comprising a transmitter and a receiver; the transmitter comprises a main control module, a waveform generating module, and an isolation driving module; The waveform generation module generates a waveform control signal based on the FPGA using the instructions of the main control module; The FPGA includes a clock management submodule, which is used to further manage the clock input by the external clock synthesis chip, output a high-quality clock, and directly connect to the FPGA global clock network; it also includes a soft-core processor submodule and a synchronous frequency division and waveform generation submodule, the synchronous frequency division and waveform generation submodule is used to generate a frequency division signal of a specific frequency that is synchronized or asynchronous with the standard time synchronization signal under the control of the soft-core processor submodule; it also includes a dead time submodule, which is used to add dead time to the two control signals of the inverter; An isolation driving module, used for converting the waveform control signal generated by the waveform generating module into a signal suitable for driving the IGBT inverter; The receiver is connected to the collection station, and each collection station is connected to at least 3 receivers. The middle receiver includes a current measurement channel and a voltage measurement channel, and the receivers on both sides include a voltage measurement channel. At least 3 receivers are used to achieve observation of the entire survey line by rolling, or the entire survey line can be observed at one time by increasing the number of receivers.

[0009] Beneficial effects of the basic solution: Using FPGA (field programmable gate array) for waveform generation and outputting high-quality clocks through the clock management submodule ensures the accuracy and stability of the waveform control signal, enabling the system to generate complex and precise waveforms to meet the detection needs under different geological conditions and improve the accuracy of detection data.

[0010] Under the control of the soft-core processor submodule, the synchronous frequency division and waveform generation submodule can generate a specific frequency division signal that is synchronized or asynchronous with the standard time synchronization signal, so that the system can adjust the transmission frequency and timing according to different detection tasks, optimize the detection effect, and reduce the dependence on external time synchronization equipment.

[0011] The dead time submodule effectively avoids cross conduction between the two control signals of the inverter, thereby reducing the damage risk of the IGBT (insulated gate bipolar transistor) inverter and improving the reliability and safety of the system.

[0012] The isolated drive module converts the waveform control signal generated by the FPGA into a signal suitable for driving the IGBT inverter, ensuring the effective transmission of the signal and the stable operation of the inverter, enabling the system to output high-power electromagnetic signals and enhancing the detection depth and resolution of underground electrical structures.

[0013] Each acquisition station is connected to at least three receivers. The middle receiver includes current measurement channels and voltage measurement channels, which can measure the power supply current and the potential difference of the measuring electrode, and measure the transmission current and underground electric field response at the same time. The receivers on both sides focus on voltage measurement, which can measure the power supply current and the potential difference of the measuring electrode at the same time, enhancing the data acquisition capability of the system and providing a richer information basis for subsequent data processing and interpretation. At the same time, the system can also flexibly adjust the number and position of receivers according to actual needs. By rolling observation or increasing the number of receivers, the system can achieve effective observation of the entire survey line, improving detection efficiency and coverage.

[0014] As an implementable preferred solution, the waveform generation module also includes a GPS submodule, a frequency synthesis submodule, and an isolation level conversion interface; The GPS submodule is used to provide a high-precision clock source for the FPGA internal system and output a standard time synchronization signal; the frequency synthesis submodule is mainly used to synthesize clock signals to meet the needs of 2n frequency waveforms suitable for fast Fourier transform; the isolation level conversion interface is used to achieve electrical isolation and level conversion with the MCU system.

[0015] As an implementable preferred solution, the FPGA internal system clock source comes from the output of the GPS submodule TIMEPULSE2, with a frequency range of 0.25Hz-10MH; the frequency clock enters the FPGA, and in order to increase the operating speed of the internal logic and improve the synchronization accuracy, and further improve the reliability of the clock, the clock management submodule is used to multiply it twice as the system clock.

[0016] As an implementable preferred solution, the isolation drive module is also used to feed back the drive status to the detection and protection module, and to perform electrical isolation between the weak current of the control circuit and the strong current of the power supply circuit; it also includes a detection and protection module, which is used to collect detection parameters and feed back the detection parameters to the main control module for analysis and processing, and generate a protection control signal based on the analysis results.

[0017] As an implementable preferred solution, it also includes a communication module for realizing data communication between modules inside the transmitter system and for realizing communication between the transmitter and external devices, and the communication mode includes serial communication or Zigbee wireless communication; In the process of sending and receiving data in the communication module, the status of each FIFO is determined by reading the status information. When receiving data, the EMPTY / DATA_PRESENT flag of the receiving unit FIFO should be checked to see if there is data in the buffer. If it is not empty, it means there is data and it is read; when sending data, EMPTY / DATA_PRESENT determines whether it is ready to send data. If it is empty, the sending unit will not enter the sending or reading state; before sending, check whether the FULL flag of the sending unit FIFO is full. If it is full, wait for data to be sent, and write to the buffer if it is not full.

[0018] As an implementable preferred solution, it also includes an input module and a display module; the input module is used to receive the user's operating instructions, and the input module transmits the user's instructions to the main control module, which, after processing, coordinates other modules to perform corresponding operations to achieve human-computer interaction; the display module provides a user interface for displaying the operation information and status information of the transmitter, which is convenient for user monitoring and operation.

[0019] As an implementable preferred solution, the dead time submodule uses a counter to count high-frequency clock pulses, and performs a logical exclusive OR operation on the waveform signal and the signal 1 delayed by one clock cycle through a D flip-flop to generate a time counting unit trigger signal trig. The time counting unit outputs a signal 3, which is inverted to obtain a signal 4. The signal 4 is logically ANDed with the waveform signal delayed by one clock cycle and its inverted signal to obtain signals 5 and 6 with dead time added. Signals 5 and 6 are latched through the D flip-flop to output waveform control signals Q1 and Q2.

[0020] As an implementable preferred solution, the collection station is responsible for receiving data from the receiver, performing synchronous collection, storage and preliminary processing; the receiver and the collection station perform data transmission and communication via wired or wireless means; According to the number of measuring points on each survey line, all measuring electrodes are arranged on the entire survey line at one time. For the power supply electrode spacing inside the survey line, high resolution of shallow targets is guaranteed through multiple coverage. For the power supply outside the survey line, the power supply electrode spacing is increased exponentially.

[0021] As an implementable preferred solution, the collection station includes a server module, a collection module and a processing module; The server module includes a communication submodule, a command parsing submodule, a shared memory submodule, a process management submodule, a logical connection submodule, a parameter setting submodule, an information query submodule, an acquisition operation submodule and a file operation submodule; the communication submodule is used to provide reliable data transmission function; the command parsing submodule is used to receive various commands sent by the control center and call other submodules to execute the command; the shared memory management submodule is responsible for the creation of shared memory and semaphore parameters; the process management submodule is used to create and destroy each subprocess in response to the "start acquisition" and "stop acquisition" commands; the logical connection submodule is used for the connection and disconnection between the acquisition station and the receiving control center; the parameter setting submodule is used to convert the received parameters into register values ​​and write them into the corresponding IO ports; the information query submodule is used to update and return the acquisition status, statistical values ​​and induced polarization calculation result data; the acquisition operation submodule is used for the logical control functions of different acquisitions; the file operation submodule is used for file list return, file deletion, file download and file upload functions.

[0022] The acquisition module is used for synchronous data acquisition and storage; The processing module is used for superposition denoising and real-time Fourier transform of the acquisition signal, and extracts the amplitude and phase of the corresponding frequency point, then calculates the dispersion rate using the amplitude of each frequency point, and uses the phase to calculate the relative phase of two adjacent frequency points.

[0023] In a second aspect, the embodiments of the present disclosure also provide a spread spectrum induced polarization controllable transmission and weak signal receiving method, which utilizes the above-mentioned spread spectrum induced polarization controllable transmission and weak signal receiving system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the transmitter structure based on MCU+FPGA.

[0025] Figure 2 This is a schematic diagram of the design principle of the synchronous waveform control signal generation circuit.

[0026] Figure 3 This is a schematic diagram of the internal circuit structure of FPGA.

[0027] Figure 4 Design framework diagram for PicoBlaze interface.

[0028] Figure 5 This is a flowchart of the PicoBlaze software.

[0029] Figure 6 Construct a schematic for the dead time generation unit circuit.

[0030] Figure 7 Generate a timing diagram for the dead time.

[0031] Figure 8 This is the state transition diagram of the time counting unit.

[0032] Fig. 9 Schematic diagram of the two-dimensional spread spectrum induced polarization observation device.

[0033] Fig.10 Schematic diagram of two-dimensional spread spectrum IP observation using distributed spread spectrum IP receiver.

[0034] Fig.11 This is a schematic diagram of the server program framework.

[0035] Fig.12 This is a flow chart of the acquisition module.

[0036] Fig.13 A schematic diagram of the processing module flow.

[0037] Fig.14 This is a schematic diagram of the DCM reset structure using SRL16E.

[0038] Fig.15 FIG. 4 is a schematic diagram of the structure of the DCM reset circuit in this embodiment.

[0039] Fig.16 This is a schematic diagram of the principle of synchronous frequency division and waveform generation.

[0040] Fig.17 This is a schematic diagram of the counter clear signal circuit structure.

[0041] Fig.18 This is the timing diagram of the counter clear signal circuit.

[0042] Fig.19 It is a schematic diagram of the synchronous and asynchronous control circuit structure.

[0043] Fig. 20 Design a schematic for the communication module.

[0044] Fig.21 This is a schematic diagram of the SPI receiving unit circuit construction.

[0045] Fig. 22 It is a simplified state transition diagram of the sending unit.

[0046] Fig.23 This is the UART macro module structure diagram. DETAILED DESCRIPTION

[0047] In order to make the technical solution and advantages of the present application clearer, the technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings. It will be understood that the specific embodiments described herein are only partial embodiments of the present invention, which are only used to explain the present application, rather than to limit the present application. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered isolated, and they can be combined with each other to achieve better technical effects. The same reference numerals appearing in the drawings of the following embodiments represent the same features or components, which can be applied to different embodiments.

[0048] In addition, unless otherwise defined, the technical terms or scientific terms used in the description of the present invention should have the common meanings understood by those skilled in the art in the art to which the present invention belongs.

[0049] The present invention is further described in detail below in conjunction with the accompanying drawings: Embodiment 1 A spread spectrum electromagnetic controllable transmission and weak signal receiving system, including a transmitter and a receiver, referring to Figure 1 The transmitter includes a main control module, a waveform generation module, an isolation drive module, a detection and protection module, a communication module, a display module, and an input module; the receiver is based on a two-dimensional spectrum induced polarization observation device of a distributed 4-channel spread spectrum induced polarization acquisition station. The two-dimensional spectrum induced polarization observation device is based on the multiple coverage and rolling measurement ideas of seismic exploration, which is conducive to high-precision imaging of geoelectric information.

[0050] The main control module, in this embodiment, uses MCU as the main control module, as the control core of the entire transmitter system, for coordinating the work of each module, processing the instructions input by the user, and controlling the waveform, frequency, dead time, synchronization and asynchronous, single and bipolar parameters; for sending the control command to the FPGA synchronization waveform control signal generation module, generating the required waveform signal, and receiving the returned GPS time and status information; for reading the UTC time (an international standard time based on the atomic clock, which provides a unified time reference worldwide) and GPS status information, and analyzing and processing the information output by the detection and protection module, and processing and generating protection measures.

[0051] The waveform generation module includes a synchronous waveform control signal generation circuit to generate the required waveform control signal in real time. Using the logic resources and programmable characteristics of the FPGA, the waveform control signal is generated according to the instructions (control parameters) of the main control module, including waveform selection, frequency selection, dead time selection, etc., and the GPS serial code information is interpreted to send the UTC time and GPS status information to the MCU, and the IGBT (Insulated Gate Bipolar Transistor) inverter is driven through the isolation drive module.

[0052] Reference Figure 2 The synchronous waveform control signal generating circuit includes FPGA (Field-Programmable Gate Array), GPS submodule, frequency synthesis submodule, debugging interface, isolation level conversion interface with MCU, power submodule, and power detection submodule.

[0053] The GPS submodule is used to provide a high-precision clock source for the FPGA internal system, outputting 1PPS (1PulsePerSecond, a standard time synchronization signal that outputs a pulse signal every second) to synchronize the timing signal and GPS serial code information for high-precision synchronization.

[0054] The frequency synthesis submodule is mainly used to meet the needs of 2n frequency waveform suitable for fast Fourier transform, and synthesizes a clock signal with low jitter, high accuracy, and suitable for 2n frequency division.

[0055] The debugging interface adopts RS232 standard and is used to configure the GPS module and debug the internal control program of FPGA.

[0056] The isolated level conversion interface is used to achieve electrical isolation and level conversion with the MCU system, which is beneficial to the safe operation of the FPGA circuit and facilitates the ground line design during PCB board manufacturing.

[0057] The power submodule provides power for the FPGA circuit and other additional circuits, including 3.3V, 2.5V, and 1.2V power supplies.

[0058] The power detection submodule is used to detect the 3.3V power supply to avoid signal confusion when the 3.3V power supply fails. It is a protection measure for the inverter.

[0059] The main part of the synchronous waveform control signal generation circuit is implemented by programming inside the FPGA. Figure 3 ,FPGA ​​includes a clock management submodule (DCM), a synchronous frequency division and waveform generation submodule, a soft-core processor submodule, a communication submodule, a dead time submodule, and a waveform output submodule.

[0060] The clock management submodule is used to further manage the clock input by the external clock synthesis chip to generate a low-jitter, stable clock, which is used as the working clock of other modules to improve system performance.

[0061] The clock management submodule outputs high-quality clocks and is directly connected to the global clock network of the FPGA. It can solve various common clock problems such as multiple clock domains, clock jitter or offset, etc. It is of great significance in FPGA, especially in high clock frequency and high performance applications. It includes digital frequency synthesizer (DFS), delay locked loop (DLL), status logic flag (statuslogic), and phase shifter (phaseshifter). The main functions include eliminating clock offset, clock phase adjustment and frequency synthesis. In addition, it can also ensure the output of a clean clock with a duty cycle of 50%, convert clock signal IO standards, etc.

[0062] The internal system clock source of the FPGA is output from the GPS submodule TIMEPULSE2. The frequency can be configured in the frequency range of 0.25Hz-10MHz. In one embodiment, since the GPS module uses a 48MHz temperature compensated crystal oscillator, in order to avoid clock jitter caused by non-integer frequency division during frequency division, the output is configured to 8MHz. In order to obtain an accurate 2n frequency division value, the circuit uses an external user-configurable clock chip ICS525, and the synthesized frequency is 33554432Hz (2 to the 25th power) by configuring the pin value. The frequency clock enters the FPGA. In order to increase the operating speed of the internal logic and improve the synchronization accuracy, and further improve the reliability of the clock, the clock management submodule is used to perform 2 times of frequency multiplication as the system clock, that is, 67108864Hz. The reason for only performing two times of frequency multiplication is that too high a frequency will increase the power consumption of the system on the one hand, and on the other hand, it will put forward greater requirements on the timing. Too high a frequency cannot meet the timing constraints during synchronous frequency division, resulting in chaotic output logic. In the ISE development environment, you can generate a clock management submodule by generating an IP core, and configure the clock management submodule properties through the interface clock configuration wizard.

[0063] The synchronous frequency division and waveform generation submodule includes a ROM, a frequency division unit and a synchronization unit. It is used to generate a frequency division signal of a specific frequency that is synchronized or asynchronous with 1PPS (1 PulsePerSecond, a standard time synchronization signal that outputs a pulse signal every second) under the control of the soft-core processor submodule, and read the waveform data in the ROM to generate a waveform signal.

[0064] The soft-core processor submodule uses the PicoBlaze 8-bit microprocessor soft core as the control core to coordinate and control the work of other modules, including monitoring the status of the communication module, receiving and analyzing commands from the MCU, extracting time information from the GPS serial code, sending time information to the MCU, setting waveform, frequency, and dead time registers, controlling synchronization and asynchronous, and waveform control signal output, etc.

[0065] In this embodiment, the PicoBlaze microprocessor needs to receive data from the single-chip microcomputer and GPS module, output waveform selection, frequency division parameters, dead time parameters, control parameters, etc., and its own input port and output port are only 8 bits each, which cannot meet the requirements and requires port expansion.

[0066] In this embodiment, PicoBlaze requires 3 input ports and 5 output ports, so the input design uses a multiplexer, PORT_ID uses binary encoding, and the output design uses one-hot encoding. Figure 4 , using a 3-to-1 three-way selection switch, PORT_ID[1:0] is used as the selection signal to select the data received from the SPI debug serial port unit, the GPS serial port unit, and the FIFO status information. At the same time, PORT_ID[1:0] decoding and READ_STROBE are used to generate the read enable signal of the FIFO data buffer to read out the FIFO data. In the figure, registers are appropriately added before and after the selection switch because PORT_ID is valid for two clock cycles. Adding registers can meet the timing requirements at a higher system clock and improve system performance. The output includes transmission data, frequency division factor memory selection address, dead time memory selection address, waveform selection parameters, and control output parameters. PORT_ID[5:1] unique hot encoding is used to determine each output port, and the enable signal is generated with the WRITE_STROBE combination logic to write FIFO data, read corresponding address data, or store corresponding parameters. This encoding method reduces the address decoding logic and reduces resource overhead.

[0067] During the data transmission and reception process of the communication module, the status information of the corresponding FIFO is checked first to ensure the effective transmission and reception of data. The FIFO data buffer is designed with three status flags: ①EMPTY / DATA_PRESENT, used to mark whether there is data in the buffer; ②HALF_FULL, marking that the buffer data has half the depth; ③FULL, marking that the buffer is full. When receiving data, the EMPTY / DATA_PRESENT flag of the receiving unit FIFO should be checked to see if there is data in the buffer. If it is not empty, it means that there is data and it is read. When sending data, EMPTY / DATA_PRESENT determines whether the data is ready to be sent. If it is empty, the sending unit will not enter the sending or reading state; in order to avoid the FIFO buffer being full, the FULL flag of the sending unit FIFO should be checked before sending. If it is full, wait for data to be sent, and write to the buffer if it is not full. This information is determined by reading the status information to determine the status of each FIFO. The definition of each status bit of the status information is shown in Table 1.

[0068] Table 1

[0069] A total of 8 status bits are defined, omitting the half-full flag sent. Each bit can be modified. The FIFO status judgment part in the PicoBlaze program corresponds to the definition of the status bit and should be modified accordingly.

[0070] Reference Figure 5 , after the FPGA is powered on and configured, PicoBlaze starts running. During idle time, PicoBlaze repeatedly checks the GPS_PRESENT and RF_EMPTY flags in the status information. If there is data, it will enter the GPS data receiving and processing program or the SPI data receiving and processing program accordingly. Since the data of the two communication interfaces need to be read and processed, the data transmission rate and FIFO depth should be properly designed to meet the actual processing requirements. If it is GPS data, analyze whether the received data is RMC information. The data file starts with "$GPRMC". If it is RMC information, continue to receive and store time information and GPS status information. If it is SPI data, receive the setting command and parameters, and then make corresponding settings and output control commands. In synchronous mode, the set synchronization time is processed and stored, and the GPS time information is read every second for comparison. If they are the same, the synchronization control information is output.

[0071] The communication submodule, as the communication interface of the soft-core processor submodule, realizes the communication inside and outside the FPGA, including the communication with the MCU during operation, the communication with the GPS module, and the communication with the PC during debugging. PicoBlaze uses a custom SPI communication mode to communicate with the MCU, an asynchronous serial port to communicate with the GPS module, and an asynchronous serial port to communicate with the PC during debugging.

[0072] The dead time submodule is used to add dead time to the two control signals of the inverter to avoid the shutdown time of the inverter unit and ensure the safe and reliable operation of the inverter. Figure 6 In this embodiment, a time counting unit (preferably a counter) is used to count high-frequency clock pulses, the timing is relatively accurate, and the dead time has a large optional range, which is conducive to setting the dead time that meets the requirements and minimizes waveform distortion.

[0073] Reference Figure 7 The waveform signal is logically XORed with signal 1 which is delayed by one clock cycle through the D flip-flop to generate the time counting unit trigger signal trig. The time counting unit outputs signal 3, which is inverted to obtain signal 4. Signal 4 is logically ANDed with the waveform signal delayed by one clock cycle and its inverted signal, respectively, to obtain signals 5 and 6 with added dead time. To avoid glitches, the D flip-flop latches outputs Q1 and Q2, i.e., the waveform control signals, and outputs them to the IGBT drive circuit.

[0074] Reference Figure 8 , the time counting unit generates dead time, and changes the length of the dead time according to the preset time value. In this embodiment, a state machine is used for design, and the trig signal triggers the state machine to run. The trig signal is generated by the logical exclusive OR of the waveform signal and its signal 1 delayed by one clock cycle. There will be no competition risk, and the state machine works synchronously under the same clock, so there will be no false triggering. Once the time counting unit starts working, the output is independent of the input signal, which belongs to the Moore type state machine.

[0075] The waveform output submodule is used to select the waveform control signal required for outputting unipolar or bipolar, whether to add dead time, etc. The waveform output submodule can generate waveforms such as DC, square wave, dual-frequency wave, pseudo-random wave, spread spectrum wave, bipolar square wave with non-1:1 duty cycle, etc.

[0076] In this embodiment, the waveform control signal is not completely generated by reading ROM. Direct current is output directly, and square wave is output after being divided by a clock signal. Different methods of adding dead time to some waveforms, such as pseudo-random waves and spread spectrum waves used for frequency domain electromagnetism, are directly added to the two-way waveform control signal, while unipolar waves or bipolar square waves with a duty cycle not of 1:1 need to consider the use of a dummy load, and it is necessary to output a dummy load control signal. Dead time may be added or not added according to the design of the dummy load circuit. Polarity control can also be set for unipolar waves, and inversion can be performed for bipolar square waves with a bipolarity not of 1:1.

[0077] The isolation drive module is used to convert the waveform control signal generated by the waveform generation module into a signal suitable for driving the IGBT inverter, and at the same time feed back the drive status to the detection and protection module, and electrically isolate the weak current of the control circuit and the strong current of the power supply circuit to ensure safety.

[0078] The detection and protection module includes a detection submodule and a protection submodule; the detection submodule is used to collect detection parameters, including but not limited to battery voltage, power supply voltage and current, and temperature; the protection submodule is used to generate a protection control signal according to the detection parameters to ensure the reliable and safe operation of the inverter.

[0079] The detection parameters collected by the detection protection module are fed back to the main control module for analysis and processing, and a protection control signal is generated according to the analysis results.

[0080] The communication module is used to realize data communication between modules within the transmitter system, and also to realize communication between the transmitter and external devices (such as GPS module, computer, etc.). The communication methods include serial communication or Zigbee wireless communication. Serial communication can be used to transmit the saved setting parameters and working voltage and current to the computer. Zigbee wireless communication can be used to form a wireless local area network with the receiver array and the main control computer to realize remote control and information exchange.

[0081] The display module provides a user interface for displaying the operation information and status information of the transmitter, which is convenient for users to monitor and operate. The display module obtains system status and parameter information from the main control module and presents this information to the user.

[0082] The input module is used to receive the user's operation instructions and realize human-computer interaction. The user inputs the control parameters, such as waveform, frequency, etc., through the keyboard. The input module transmits the user's instructions to the main control module, which processes them and coordinates other modules to perform corresponding operations.

[0083] Reference Fig. 9 In the implementation of the present disclosure, the weak signal receiver is different from the traditional induced polarization two-dimensional acquisition based on a multi-channel dipole device, and measurement electrodes and power supply electrodes are arranged on the measuring line. The receiver has 4 acquisition channels, including current measurement channels and voltage measurement channels, and is mainly used in spread spectrum induced polarization. The receiver is the front-end equipment of the acquisition station, which is in direct contact with the object under test and is responsible for the preliminary acquisition of data. The acquisition station is the back-end processing center of the receiver, responsible for receiving data from the receiver, performing synchronous acquisition, storage and preliminary processing, and communicating with the receiving control center. Data transmission and communication are carried out between the receiver and the acquisition station through wired or wireless means.

[0084] According to the number of measuring points on each measuring line, all measuring electrodes are arranged on the entire measuring line at one time. For example, the length of a measuring line is 1200 meters, and the point spacing is 20 meters. The total number of measuring points is 60. 61 measuring electrodes and 60 parallel measuring channels can be arranged at one time, and then power is supplied from the middle of the measuring line. Each time power is supplied, 60 parallel measuring channels are measured simultaneously.

[0085] Reference Fig. 9 , first power on A0B0, then power on A1B1, and then power on A2B2. For the supply electrode spacing inside the survey line, high resolution for shallow targets is ensured by multiple coverages, and the distance increased each time is twice the point spacing. In this embodiment, the supply electrode spacing is increased by 40 meters each time. For the power supply outside the survey line, the pole distance increase scheme is adopted to increase the supply electrode spacing exponentially to improve the imaging accuracy of deep targets, and the supply electrode spacing can also be encrypted to improve the resolution of deep targets.

[0086] When the power supply is external to the survey line, the detection depth is increased by gradually increasing the distance between the power supply electrodes. Since the shallow targets have been powered by the internal power supply of the survey line to ensure high-precision detection, the influence of shallow inhomogeneities on the detection of deep targets can be prevented, greatly improving the imaging accuracy of deep targets.

[0087] The collection station is connected to at least 3 receivers, refer to Fig.10 The receiver in the middle includes 3 voltage measurement channels and 1 current measurement channel, which can measure the power supply current and the potential difference of the measuring electrode at the same time. The receivers on both sides include 4 voltage measurement channels, which can measure the potential difference of multiple measuring points. The whole measuring line can be observed at one time by increasing the number of receivers, or the whole measuring line can be observed by rolling with a small number of receivers.

[0088] The collection station includes a server module, a collection module and a processing module.

[0089] The server module is used for communication between the acquisition station and the receiving control center (including PC), command parsing, shared memory creation, semaphore creation, and subprocess management. Its module framework is as follows Fig.11 As shown, it includes a communication submodule, a command parsing submodule, a shared memory submodule, a process management submodule, a logic connection submodule, a parameter setting submodule, an information query submodule, a collection operation submodule and a file operation submodule. Among them, the communication submodule is composed of the TCP / IP communication submodule, which mainly provides reliable data transmission function for the upper layer; the command parsing submodule mainly completes various commands sent by the PC and calls other submodules to execute the command; the shared memory management submodule is responsible for the creation of parameters such as shared memory and semaphores, and provides data access areas and synchronization variables for other processes; the process management submodule is responsible for the creation and destruction of each subprocess. This submodule is generally called by the acquisition operation to respond to the "start acquisition" and "stop acquisition" commands; the logical connection submodule is mainly responsible for the connection and disconnection between the acquisition station and the PC; the parameter setting submodule mainly realizes the conversion of the received parameters into register values ​​and writes them to the corresponding IO port; the information query submodule is mainly responsible for the update and return of data such as acquisition status, statistical values ​​and induced polarization calculation results; the acquisition operation submodule is mainly responsible for the logical control functions of different acquisitions; the file operation submodule mainly completes the file list return, file deletion, file download and file upload functions.

[0090] The acquisition module is used for synchronous data acquisition and storage, refer to Fig.12, the execution steps after the module is started are: ① initialize the parameters related to the acquisition first; ② obtain the shared memory and signal set created by the server module; ③ open the I / O port of the data reading channel and clear the I / O port buffer; ④ calculate the data length to be collected according to the set parameters; ⑤ read a section of data from each channel from the I / O port, and store it in the storage card in the form of a file, and update the acquisition information in the shared memory at the same time; ⑥ determine whether the data length read from the I / O port reaches the data length required to be collected. If so, end and exit the process, otherwise jump to step ⑤.

[0091] The processing module is mainly responsible for superposition and noise removal of the collected signals and real-time Fourier transform, and extracts the amplitude and phase of the corresponding frequency points, then uses the amplitude of each frequency point to calculate the dispersion rate, and uses the phase to calculate the relative phase of two adjacent frequency points. After the IP acquisition is started, the calculation program will remain in the IP calculation state until the server process terminates the process. After each signal cycle is collected, the calculation program will perform an IP calculation. After the calculation is completed, the program automatically counts all the results of the previous calculations and calculates the corresponding expected value and error.

[0092] The processing module is used to calculate IP results and error statistics, refer to Fig.13 After startup, it is initialized first, and the shared memory and semaphore set created by the server process are obtained. Then the data file created by the acquisition process is opened, the data is read according to the parameters in the shared memory and the corresponding calculation is performed. Finally, the calculation results are updated to the shared memory for query by the server process.

[0093] The FPGA system is connected to the main control module through a level conversion circuit, and communicates with the main control module using an SPI communication interface. PicoBlaze receives waveform control parameters through the SPI interface, analyzes and processes the control parameters, and generates waveform selection, frequency selection, dead time selection and other control signals. At the same time, it receives serial code information from the GPS module, obtains GPS lock status and time information, and sends it to the main control module through SPI. The waveform selection memory module determines the RAM addressing high address and determines the output waveform; the frequency division factor memory determines the RAM address counter clock, and the RAM address counter generates the RAM addressing low address and determines the frequency of the output waveform; the dead time selection memory determines the dead time size; the dead time generation module adds dead time to the generated waveform control signal; the waveform output selection module determines whether to output the waveform control signal with dead time added or directly output a unipolar waveform control signal. Under the control of PicoBlaze, the synchronous control module decides whether to use GPS synchronous output or asynchronous mode. The generated waveform control signal drives the IGBT under the synthesis of the external waveform control logic gate circuit.

[0094] Embodiment 2 In some prior arts, the clock management submodule adds a reset unit (circuit) when using an external feedback source, see Fig.14 , an SRL16 shift register with an initial value of 000F is used to generate a reset signal. This is because the reliable reset of DCM requires the reset signal to last at least 3 input clock cycles. In practice, although the internal feedback source is used, the IO buffer has not yet taken effect during the power-on configuration process, and the existence of the external clock synthesis chip causes the clock to be unstable at the beginning, resulting in the phenomenon that the DCM cannot be locked after power-on. Although the above method can increase the probability of locking, it still cannot be locked because it ends after 16 pulses and the clock may not have stabilized.

[0095] There are other technical solutions that use a single-chip microcomputer as an external reset signal source to monitor the DCM lock status in real time. The DCM provides status logic LOCKED and STATUS to indicate the working status of the DCM. LOCKED is used to indicate whether CLKFB and CLKIN are in phase. STATUS has 8 bits, of which only STATUS[2:0] is defined to indicate the working status of DLL and PS. STATUS[2] indicates whether the output CLKFX of DFS is suspended; STATUS[1] is used to indicate whether CLKIN is suspended; STATUS[0] is used to indicate whether the phase shifter has reached the limit value, which is only valid in the enhanced Spartan-3A series. In order to reliably indicate the DCM status, it is best to monitor LOCKED and STATUS[1] at the same time.

[0096] This embodiment provides a reliable reset circuit that does not require the participation of a single chip microcomputer. Fig.15 As shown, the clock management submodule (DCM) is prevented from being in a locked state when the FPGA is powered on and configured and the clock is stopped before the clock output is allowed. Specifically, a counter is used to count the clock, which is equivalent to skipping the previous unstable clock cycle. After reaching a certain count value, an enable signal for the shift register is generated. The shift register is composed of 4 cascaded flip-flops with enable and asynchronous setting. The initial value of the flip-flop is configured to 1, and the first flip-flop input is connected to a low level. In this way, a high-level reset signal that lasts for 4 clock cycles can be generated to ensure that the DCM is effectively reset and locked under a stable clock. The clock input can be turned off by controlling CLK_OFF to be high. At this time, CLK_OFF will asynchronously clear the counter and asynchronously set the flip-flop. When the clock is restored, a valid reset signal can still be generated, thereby ensuring that the DCM can always be in a reliable locked state.

[0097] Embodiment 3 There are two main ways to generate waveform signals in the synchronous frequency division and waveform generation module: one is to use a finite state machine, and the other is to read a waveform memory. When using a finite state machine to design each waveform, it must be designed separately. It is very convenient when there are fewer waveform encoding states, but it will be very troublesome when there are more states. For example, a pseudo-random wave, an n-frequency wave waveform encoding has 2n states, and an eleven-frequency wave has 2048 states. In addition, when the waveform is expanded, a new state machine must be designed for each additional waveform, which is not convenient for waveform expansion. The method of using a waveform memory is relatively convenient. It only needs to use software programming to sample the waveform and write the waveform data into the memory to easily realize waveform expansion. Of course, this method is also insufficient for waveforms with more states, and more storage space is required to store waveform data without errors.

[0098] The disclosed embodiment is based on the advantage of integrating RAM blocks inside FPGA to meet the needs of a large amount of on-chip storage space, and uses internal Block RAM to generate ROM space to store waveform data to simplify the peripheral hardware circuit design. The difficulty in outputting the desired waveform control signal by reading the waveform data is how to achieve synchronous reading of the waveform data.

[0099] The addressing of waveform data is to select the waveform by high bit and the waveform sampling point data by low bit. It only needs to meet the synchronization of ROM low bit address, that is, address counting clock and 1-PPS. The output waveform control signal is synchronized with 1-PPS. Fig.16 The design can realize the generation of ROM address counting clock and synchronous or asynchronous control with 1-PPS.

[0100] The counter clear signal used for synchronous frequency division enables the D flip-flop with input '1' to generate the ROM enable signal, so that the ROM starts reading according to the address when the address counting clock is valid, thereby completing the synchronization of the waveform control signal and 1-PPS.

[0101] When synchronizing a low-frequency signal to a high-frequency signal, a high-frequency signal can be used as a clock source to trigger and latch the low-frequency signal. This is feasible for a high-frequency clock, but it cannot synchronize a lower-frequency signal. In order to align the divided frequency signal with the leading edge of 1PPS, refer to Fig.17 , so that the frequency division unit counter starts counting at the rising edge of 1PPS and sets the high level to achieve synchronous output of the frequency division signal and the rising edge of 1PPS.

[0102] Reference Fig.19, the rst_ct signal is output by the PicoBlaze core and is used to enable the generation of a counter clear signal. After receiving the synchronization output time parameter, this technical solution waits for the arrival of the time, outputs the control signal rst_ct in the previous second, and completes synchronization when the next PPS front arrives. rst_ct enables the D flip-flop with asynchronous clearing. When the set time arrives, rst_ct is set to 1, q_temp1 outputs a high level, which is latched by the next SEC, q_temp2 becomes a high level, and is latched by the rising edge of the system clock after SEC, ct_clr becomes a high level, and the previous two D flip-flops are asynchronously cleared, q_temp1 and q_temp2 both become low levels, and in the next system clock ct_clr becomes a low level again, completing the clearing of the counter.

[0103] The SEC refers to the signal after PPS passes through two-stage triggers. Since PPS is an asynchronous signal relative to the system clock, directly using PPS as the clock of FDC in the figure may cause the output q_temp2 to fail to meet the establishment time of the subsequent FD, and the output of FDCE may also not meet the establishment time of the PPS clock domain, which will cause metastable states. Therefore, PPS is converted into a SEC synchronized with the system clock through two-stage triggers, thereby improving the reliability of system synchronization.

[0104] In addition to the fact that the internal devices and transmission lines of the FPGA will cause a certain delay between the output frequency division signal and the PPS front edge, the system clock will also cause a delay of no more than 4 system clock cycles. For the system clock of 67.108864M in this system, the delay caused by this solution does not exceed 100ns, which meets the requirements.

[0105] Reference Fig.18 , using a two-way switch, select 1PPS or simulated 1PPS signal as the synchronous SEC clock source, and add an asynchronous mode to the synchronous mode to meet the power supply situation that does not require synchronization.

[0106] Both SPPS and MODE are generated by PicoBlaze. SPPS simulates PPS. MODE is used to select which of the two is used as the synchronous clock source, that is, synchronous and asynchronous modes. For PPS, the design generates a delay of no more than two system cycles. The control signal is always output after the serial code information of PPS, so the combinational logic circuit will not have a competitive risk. Even if a glitch occurs, the two-stage trigger behind it will be filtered out and will not cause false synchronization triggering.

[0107] Currently, most FPGAs provide RAM blocks to meet the needs of designs that require a large amount of on-chip storage space. This technical solution uses Block RAMs to generate ROM for waveform data storage. Block RAMs are real dual-port storage blocks that can be configured as single-port or dual-port in use. The IP Core generator can configure Block RAM as RAM or ROM, and does not distinguish between data and check bits. Both can be used as data bits. The ratio of bit width to space size is very flexible, supporting a bit width of 1-256 bits, and the storage depth depends on the selected chip. For dual-port memory, the two ports can be configured with different bit width and depth ratios, but the total storage space size depends on port A. In one embodiment, port A is set to a bit width of 1 bit and a depth of 131072. When the bit width of port B is set to 2, the depth is 65536.

[0108] The main waveforms currently used in electrical prospecting are dual-frequency waves, pseudo-random waves, bipolar square waves with a duty cycle other than 1:1, and spread spectrum waves. The generation of bipolar square waves with a duty cycle other than 1:1 requires two different signal controls, such as a power supply direction control signal and a power supply control signal. Therefore, waveforms such as bipolar square waves with a duty cycle other than 1:1 require a bit width of 2 when stored. For waveforms with alternating forward and reverse power supply, only the waveform data is required, and the two control signals of the inverter are obtained by inverting them.

[0109] In order to meet the above two needs and save storage space at the same time, a solution for storing waveform data is adopted, in which two single-port ROMs are generated, the bit width of ROM1 is set to 2, and the bit width of ROM2 is set to 1.

[0110] Embodiment 4 The technical feature that distinguishes this embodiment from the above embodiments is that, in order to facilitate debugging in the transmitter system, the serial port and SPI communication during debugging are designed to be combined, and the conversion between normal operation and debugging mode is achieved by controlling the jumper.

[0111] Reference Fig. 20, a communication module, including a debugging serial port receiving unit, an SPI receiving unit, an SPI sending unit, and a debugging serial port sending unit. The entire waveform control signal generation is completed under the control of PicoBlaze, and the serial port is used for debugging, and the SPI is used for normal operation. The two communication modes share the same data buffer to save storage units. It is only necessary to design the sending / receiving units of the SPI and serial ports respectively. The receiving unit generates data output and a write enable signal, and the sending unit generates data input and a read enable signal. Which communication mode is selected is determined by selecting which group of receiving / transmitting units, that is, which working mode is selected. In this embodiment, the jumper Work / Debug is used for selection. In order to prevent the units of the two communication modes from working at the same time, Work / Debug is used as the enable signal of each receiving and transmitting unit at the same time. When one communication mode is selected, the unit of the other communication mode is not working, thereby saving the dynamic power consumption of the unit.

[0112] In the embodiments of the present disclosure, the SPI interface is designed according to an 8-bit data length. Fig.21 In this embodiment, the receiving unit needs to complete the conversion from serial data to parallel data, which is realized by register shifting. In this embodiment, the chip select signal CS is inverted as the enable signal, and the SCLK clock line is used as the clock source to read the data on the MOSI data line. In order to avoid the impact of the peak pulse of the SCLK clock on the reception, the system clock is used to latch the SCLK and then used as the shift clock to receive the data, and the MOSI data line is also latched.

[0113] The sending unit converts parallel data into serial data output and is designed using a state machine. The SPI sending unit is designed as a slave mode. Data transmission is always initiated by the microcontroller. The output of the state machine is related to the input and belongs to the Mealy state machine. Fig. 22 The figure shows a simplified state transition diagram of the sending unit. Some states have multiple sub-state transitions. Data transmission is specified to be valid on the falling edge of the SCLK clock, so the next bit of data is output on the rising edge, and the bit data is held and the clock is counted on the falling edge. When the count value is 8 bits, it means that one byte of valid data is output, a read enable signal is generated, and the FIFO data is read. Like the write enable signal of the receiving unit, the read enable signal can only last for one clock cycle. The state machine works under the system clock, and there is one clock cycle between two sub-states.

[0114] In this embodiment, the read enable signal is placed after the data transmission is completed rather than at the beginning of each data reading, so as to avoid the FIFO data being read due to the loss of the SCLK clock or less than 8 when the data is sent. Under normal circumstances, the SCLK clock will not be lost, but because it is a slave mode, the data may not be ready when the single-chip microcomputer initiates the data reading, and the data is written into the FIFO after several clocks. The state machine enters the sending state when the FIFO is not empty. At this time, it is less than 8 clocks to read the complete data, so data loss occurs. If the data in the FIFO is directly time information, it is impossible to determine whether the first data read is correct, so a file header or response data must be defined. After receiving the read command, the file header or response data is placed in front of the data to be sent. If the single-chip microcomputer reads the correct data, it means that the time information is ready and can be read. If it is incorrect, it is re-read until the correct response data is read and then the time information is read.

[0115] PicoBlaze uses UART communication to communicate with the GPS module and the PC. Xilinx provides UART receive and transmit macros, each of which contains a 16-byte FIFO. Fig.23 , the transmission baud rate can be configured by simply adding an additional baud rate reference timing signal generation unit.

[0116] The baud rate configuration of UART is realized by configuring the reference timing signal of the ex_16_x_baud port of the macro module. This signal is used as the internal clock enable signal of the transceiver unit, which is 16 times the baud rate. Since it is used as a clock enable signal, it must be synchronized with the clock on the one hand, and the high level can only last for one clock cycle on the other hand, so configuring the baud rate is actually dividing the system clock to obtain a signal of 16*baud rate. A counter can be used for frequency division design, and the division factor is: system clock / baud rate / 16, and the allowable error is within 1%.

[0117] During debugging, communication with the PC requires a receiving unit and a sending unit, while communication with the GPS module only requires a receiving unit. In this embodiment, the UART receiving macro module is directly used to communicate with the GPS module, and the receiving and sending units in the UART macro are used to communicate with the PC, and the FIFO is shared with the SPI receiving and sending units respectively. The baud rate of the FPGA to communicate with the GPS module is designed to be 115200Hz (the frequency division factor is 18), and the baud rate of the FPGA to communicate with the PC is designed to be 9600Hz (the frequency division factor is 218). A total of two receiving units and one receiving unit are required, and the baud rate settings do not affect each other and are independent of each other.

[0118] The disclosed embodiment also provides a spread spectrum induced polarization controllable transmission and weak signal receiving method, which utilizes the above-mentioned spread spectrum induced polarization controllable transmission and weak signal receiving system.

[0119] The embodiment of the present disclosure also provides a storage medium, in which a computer program is stored. When the computer program is executed by a processor, all steps of the above-mentioned method of spread spectrum induced polarization controllable transmission and weak signal reception based on big data can be implemented.

[0120] Those skilled in the art can understand that the implementation of all or part of the process in a spread spectrum electromagnetic controllable emission and weak signal reception method can be completed by instructing related hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the process of each embodiment of a spread spectrum electromagnetic controllable emission and weak signal reception method. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0121] The above contents are only embodiments of the present invention. The common sense such as the known specific structures and characteristics in the scheme is not described in detail here. The ordinary technicians in the relevant field know all the common technical knowledge in the technical field to which the invention belongs before the application date or the priority date, can obtain all the existing technologies in the field, and have the ability to apply the conventional experimental means before that date. The ordinary technicians in the relevant field can improve and implement this scheme in combination with their own abilities under the enlightenment given by this application. Some typical known structures or known methods should not become obstacles for the ordinary technicians in the relevant field to implement this application. It should be pointed out that for the technicians in this field, without departing from the structure of the present invention, several deformations and improvements can be made, which should also be regarded as the protection scope of the present invention, which will not affect the effect of the implementation of the present invention and the practicality of the patent. The protection scope required by this application shall be based on the content of its claims, and the specific implementation methods and other records in the specification can be used to explain the content of the claims.

Claims

1. A spread spectrum electromagnetic controllable transmission and weak signal receiving system, characterized in that: It includes a transmitter and a receiver; the transmitter includes a main control module, a waveform generation module, and an isolation drive module; The waveform generation module generates a waveform control signal based on the FPGA using the instructions of the main control module; The FPGA includes a clock management submodule, which is used to further manage the clock input by the external clock synthesis chip, output a high-quality clock, and directly connect to the FPGA global clock network; it also includes a soft-core processor submodule and a synchronous frequency division and waveform generation submodule, the synchronous frequency division and waveform generation submodule is used to generate a frequency division signal of a specific frequency that is synchronized or asynchronous with the standard time synchronization signal under the control of the soft-core processor submodule; it also includes a dead time submodule, which is used to add dead time to the two control signals of the inverter; An isolation driving module, used for converting the waveform control signal generated by the waveform generating module into a signal suitable for driving the IGBT inverter; The receiver is connected to the collection station, and each collection station is connected to at least 3 receivers. The middle receiver includes a current measurement channel and a voltage measurement channel, and the receivers on both sides include a voltage measurement channel. At least 3 receivers are used to achieve observation of the entire survey line by rolling, or the entire survey line can be observed at one time by increasing the number of receivers.

2. A spread spectrum induced polarization controllable transmission and weak signal receiving system according to claim 1, characterized in that: The waveform generation module also includes a GPS submodule, a frequency synthesis submodule, and an isolation level conversion interface; The GPS submodule is used to provide a high-precision clock source for the FPGA internal system and output a standard time synchronization signal; the frequency synthesis submodule is mainly used to synthesize clock signals to meet the needs of 2n frequency waveforms suitable for fast Fourier transform; the isolation level conversion interface is used to achieve electrical isolation and level conversion with the MCU system.

3. A spread spectrum induced polarization controllable transmission and weak signal receiving system according to claim 2, characterized in that: The internal system clock source of FPGA comes from the output of GPS submodule TIMEPULSE2, with a frequency range of 0.25Hz-10MH; the frequency clock enters FPGA, and in order to increase the running speed of internal logic and improve synchronization accuracy, and further improve the reliability of the clock, the clock management submodule is used to multiply it twice as the system clock.

4. A spread spectrum induced polarization controllable transmission and weak signal receiving system according to claim 1, characterized in that: The isolation drive module is also used to feed back the drive status to the detection and protection module, and to perform electrical isolation between the weak current of the control circuit and the strong current of the power supply circuit; it also includes a detection and protection module, which is used to collect detection parameters and feed back the detection parameters to the main control module for analysis and processing, and generate a protection control signal based on the analysis results.

5. A spread spectrum induced polarization controllable transmission and weak signal receiving system according to claim 1, characterized in that: It also includes a communication module, which is used to realize data communication between modules inside the transmitter system, and is also used to realize communication between the transmitter and external devices, and the communication method includes serial communication or Zigbee wireless communication; In the process of sending and receiving data in the communication module, the status of each FIFO is determined by reading the status information. When receiving data, the EMPTY / DATA_PRESENT flag of the receiving unit FIFO should be checked to see if there is data in the buffer. If it is not empty, it means there is data and it is read; when sending data, EMPTY / DATA_PRESENT determines whether it is ready to send data. If it is empty, the sending unit will not enter the sending or reading state; before sending, check whether the FULL flag of the sending unit FIFO is full. If it is full, wait for data to be sent, and write to the buffer if it is not full.

6. A spread spectrum induced polarization controllable transmission and weak signal receiving system according to claim 1, characterized in that: It also includes an input module and a display module; the input module is used to receive the user's operating instructions, and the input module transmits the user's instructions to the main control module. After being processed by the main control module, the main control module coordinates other modules to perform corresponding operations to achieve human-computer interaction; the display module provides a user interface for displaying the operation information and status information of the transmitter, which is convenient for user monitoring and operation.

7. A spread spectrum induced polarization controllable transmission and weak signal receiving system according to claim 1 or 5, characterized in that: The dead time submodule uses a counter to count high-frequency clock pulses. The waveform signal is logically XORed with signal 1 which is delayed by one clock cycle through a D flip-flop to generate a time counting unit trigger signal trig. The time counting unit outputs signal 3, which is inverted to obtain signal 4. Signal 4 is logically ANDed with the waveform signal delayed by one clock cycle and its inverted signal to obtain signals 5 and 6 with dead time added. Signals 5 and 6 are latched by the D flip-flop to output waveform control signals Q1 and Q2.

8. The spread spectrum induced polarization controllable transmission and weak signal receiving system according to claim 1, characterized in that: The collection station is responsible for receiving data from the receiver, and performing synchronous collection, storage and preliminary processing; the receiver and the collection station transmit and communicate data via wired or wireless means; According to the number of measuring points on each survey line, all measuring electrodes are arranged on the entire survey line at one time. For the power supply electrode spacing inside the survey line, high resolution of shallow targets is guaranteed through multiple coverage. For the power supply outside the survey line, the power supply electrode spacing is increased exponentially.

9. A spread spectrum induced polarization controllable transmission and weak signal receiving system according to claim 1 or 8, characterized in that: The collection station includes a server module, a collection module and a processing module; The server module includes a communication submodule, a command parsing submodule, a shared memory submodule, a process management submodule, a logic connection submodule, a parameter setting submodule, an information query submodule, a collection operation submodule and a file operation submodule; the communication submodule is used to provide a reliable data transmission function; the command parsing submodule is used to receive various commands sent by the control center and call other submodules to execute the command; The shared memory management submodule is responsible for the creation of shared memory and semaphore parameters; The process management submodule is used to create and destroy each subprocess in response to the "start collection" and "stop collection" commands; The logic connection submodule is used for connection and disconnection between the acquisition station and the receiving control center; The parameter setting submodule is used to convert the received parameters into register values ​​and write them into the corresponding IO ports; the information query submodule is used to update and return the data of the acquisition status, statistical values ​​and IP calculation results; the acquisition operation submodule is used for the logic control function of asynchronous acquisition; the file operation submodule is used for the file list return, file deletion, file download and file upload functions; The acquisition module is used for synchronous data acquisition and storage; The processing module is used for superposition denoising and real-time Fourier transform of the acquisition signal, and extracts the amplitude and phase of the corresponding frequency point, then calculates the dispersion rate using the amplitude of each frequency point, and uses the phase to calculate the relative phase of two adjacent frequency points.

10. A method for spread spectrum electromagnetic controllable transmission and weak signal reception, characterized in that: A spread spectrum induced polarization controllable transmission and weak signal receiving system as described in claims 1-9 is used.

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