Mask device, display device and packaging method thereof

Abstract

The invention discloses a mask device, a display device and a packaging method of the display device. The mask device comprises a mask plate main body, the mask plate main body comprises an edge area located at the edge position of the mask plate main body and a middle area located at the middle position of the mask plate main body; the middle area comprises a plurality of hollow areas and salient point layers which are fixedly arranged in the direction perpendicular to the plane where the mask plate main body is located; at least two packaging alignment marks are designed in the edge area, and the packaging alignment marks and the wafer alignment marks are correspondingly arranged; the arrangement mode of the hollowed-out areas is the same as that of the chips, the size of the hollowed-out areas is larger than that of the glass cover plate, and the multiple hollowed-out areas form a net-shaped hollowed-out opening; when the mask device is attached to the wafer substrate, the edge area and the salient point layer make contact with the surface of the wafer substrate, and a gap exists between the net face of the net-shaped hollowed-out opening and the surface of the wafer substrate. According to the mask device, the deviation position of the glass cover plate can be limited, and the mask device is uniform in stress and not prone to deformation.

Description

Technical Field

[0001] The present invention relates to the technical field of display devices, and in particular to a mask device, a display device and a packaging method thereof. Background Art

[0002] In order to protect the display area of ​​silicon-based organic light-emitting diodes (OLEDs) from external damage and prevent water and oxygen in the environment from corroding OLED devices, it is necessary to encapsulate the OLED devices with a glass cover. Currently, the most mainstream glass cover encapsulation of silicon-based OLED microdisplay devices is to apply optical liquid glue (OCR, Optical Clear Resin) on the silicon substrate by pneumatic glue coating, then attach the glass cover, and then cure the OCR glue by ultraviolet irradiation or heating to complete the glass cover encapsulation of the silicon-based OLED.

[0003] However, this packaging process using OCR glue has the following defects: liquid OCR glue can easily cause the glass cover to shift. Although current patch equipment generally has visual alignment and high-precision bonding mechanisms to ensure the accuracy of the glass cover mounting position, there is a layer of fluid liquid glue between the glass cover and the underlying silicon substrate. During the extension and flow of the glue, the glass cover will shift by 20-100um, affecting the yield. Currently, with the increase in the screen-to-body ratio of silicon-based OLED microdisplay devices, the size of the glass cover has increased, and the distance between the edge of the cover and the wafer cutting path has been significantly reduced. Therefore, the offset of the glass cover will increase the risk of the cutting process, and will also affect the installation of subsequent optical modules. Summary of the invention

[0004] The present invention provides a mask device, a display device and a packaging method thereof, which can limit the offset position of a glass cover plate, eliminate the negative impact of the offset of the glass cover plate on subsequent wafer cutting and optical module installation, and the mask device is evenly stressed as a whole and does not deform after long-term use.

[0005] In a first aspect, an embodiment of the present invention provides a mask device for packaging a display device, wherein the display device includes a wafer substrate and a packaging component; the wafer substrate includes a plurality of chips, a light-emitting element layer, and a wafer alignment mark; the packaging component includes a glass cover layer, and the glass cover layer includes a glass cover;

[0006] The mask device comprises: a mask plate main body;

[0007] The mask plate body includes an edge area located at the edge position of the mask plate body and a middle area located at the middle position of the mask plate body; the middle area includes a plurality of hollow areas and bump layers fixedly arranged in a direction perpendicular to the plane where the mask plate body is located; the edge area is designed with at least two package alignment marks, and the package alignment marks and the wafer alignment marks are arranged correspondingly;

[0008] The arrangement of the hollow areas is the same as that of the chips, and the size of the hollow areas is larger than that of the glass cover plate, and a plurality of the hollow areas form a mesh of hollow openings;

[0009] When the mask device and the wafer substrate are attached, the edge region and the bump layer are in contact with the surface of the wafer substrate, and a gap exists between the mesh surface of the mesh-shaped hollow opening and the surface of the wafer substrate.

[0010] Optionally, the bump layer includes at least two bumps;

[0011] The convex point is arranged at the center of the mesh intersection of the mesh-shaped hollow opening.

[0012] Optionally, the cross-section of the protrusion along a direction parallel to the plane where the mask plate body is located is circular.

[0013] Optionally, the number of the protrusions is the same as the number of mesh intersections of the mesh-shaped hollow openings.

[0014] Optionally, the package alignment mark includes a circular hole.

[0015] Optionally, the material of the mask plate body includes iron-nickel alloy and stainless steel.

[0016] Optionally, the projection of the hollow area on the plane where the mask plate body is located is a rectangle, and the difference between the width of the hollow area and the width of the glass cover plate is in the range of 50-100 μm; the difference between the length of the hollow area and the length of the glass cover plate is in the range of 50-100 μm.

[0017] In a second aspect, an embodiment of the present invention further provides a display device, which is packaged using the mask device as described in the first aspect, and the display device includes:

[0018] Silicon-based semiconductor circuit substrate;

[0019] A light emitting element layer located on one side of the silicon-based semiconductor circuit substrate;

[0020] A thin film encapsulation layer located on a side of the light emitting element layer away from the silicon-based semiconductor circuit substrate;

[0021] An optical adhesive layer located on a side of the thin film encapsulation layer away from the light emitting element layer;

[0022] A glass cover layer located on a side of the optical adhesive layer away from the thin film encapsulation layer;

[0023] Wherein, the display device comprises a wafer substrate and a packaging component, the wafer substrate comprises the silicon-based semiconductor circuit substrate, the light-emitting element layer and the thin-film packaging layer, and the packaging component comprises the optical adhesive layer and the glass cover layer.

[0024] Optionally, the wafer substrate further includes: a color filter layer;

[0025] The color filter layer is located between the thin film encapsulation layer and the optical adhesive layer.

[0026] In a third aspect, an embodiment of the present invention further provides a method for packaging a display device, which is used to package the display device as described in the second aspect. The method for packaging the display device includes:

[0027] Coating liquid optical adhesive on the wafer substrate to form an optical adhesive layer;

[0028] Aligning the mask device with the wafer substrate and attaching them together;

[0029] Mounting glass cover plates one by one on the hollow areas of the mask device to form a glass cover plate layer;

[0030] The optical adhesive layer is cured by using a high-pressure degassing process and an ultraviolet irradiation curing process;

[0031] The mask device is removed, and the wafer substrate is cut to form the display device.

[0032] The embodiment of the present invention provides a mask device, a display device and a packaging method thereof, wherein the mask device comprises: a mask plate body; the mask plate body comprises an edge region located at the edge position of the mask plate body and a middle region located at the middle position of the mask plate body; the middle region comprises a plurality of hollow regions and a bump layer fixedly arranged in a direction perpendicular to the plane where the mask plate body is located; the edge region is designed with at least two package alignment marks, and the package alignment marks and the wafer alignment marks are arranged correspondingly; the arrangement mode of the hollow regions is the same as the arrangement mode of the chips, and the size of the hollow regions is larger than the size of the glass cover plate, and the plurality of hollow regions constitute a mesh hollow opening; when the mask device and the wafer substrate are bonded, the edge region and the bump layer are in contact with the surface of the wafer substrate, and there is a gap between the mesh surface of the mesh hollow opening and the surface of the wafer substrate. The corresponding arrangement of the package alignment marks and the wafer alignment marks in the mask device of the present invention can ensure the bonding accuracy, the arrangement mode of the hollow regions is the same as the arrangement mode of the chips, and the size of the hollow regions is larger than the size of the glass cover plate, which can limit the offset position of the glass cover plate. Providing a bump layer in the non-hollow area can avoid scratching the display area of ​​the wafer substrate. When the mask device and the wafer substrate are bonded, the edge area and the bump layer are in contact with the surface of the wafer substrate, and there is a gap between the mesh surface of the mesh-shaped hollow opening and the surface of the wafer substrate, which can make the mask device evenly stressed as a whole and will not deform after long-term use.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A cross-sectional view of a display device provided by an embodiment of the present invention;

[0036] Figure 2 A cross-sectional view of another display device provided by an embodiment of the present invention;

[0037] Figure 3 A top view of a display device provided by an embodiment of the present invention;

[0038] Figure 4 A top view of a mask device provided by an embodiment of the present invention;

[0039] Figure 5A cross-sectional view of a mask device provided by an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of laminating a mask device and a wafer substrate provided by an embodiment of the present invention;

[0041] Figure 7 A flow chart of a method for packaging a display device provided by an embodiment of the present invention;

[0042] Figure 8 A schematic diagram of a glass cover plate provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] Figure 1 A cross-sectional view of a display device provided by an embodiment of the present invention, referring to Figure 1, the display device comprises: a silicon-based semiconductor circuit substrate 110. A light-emitting element layer 120 located on one side of the silicon-based semiconductor circuit substrate 110. A thin film encapsulation layer 130 located on a side of the light-emitting element layer 120 away from the silicon-based semiconductor circuit substrate 110. An optical adhesive layer 140 located on a side of the thin film encapsulation layer 130 away from the light-emitting element layer 120. A glass cover layer 150 located on a side of the optical adhesive layer 140 away from the thin film encapsulation layer 130. The display device 100 comprises a wafer substrate A and a packaging component B, the wafer substrate A comprises a silicon-based semiconductor circuit substrate 110, a light-emitting element layer 120 and a thin film encapsulation layer 130, and the packaging component B comprises an optical adhesive layer 140 and a glass cover layer 150. The glass cover layer 150 comprises a glass cover.

[0046] Figure 2 A cross-sectional view of another display device provided by an embodiment of the present invention. Optionally, based on the above embodiment, refer to Figure 2 The wafer substrate A further includes a color filter layer 160 . The color filter layer 160 is located between the thin film encapsulation layer 130 and the optical adhesive layer 140 .

[0047] Figure 3 A top view of a display device provided in an embodiment of the present invention may be a top view of any display device provided in the above embodiments. Figure 3 The display device 100 also includes a plurality of chips A1 and a wafer alignment mark A2.

[0048] Figure 4 A top view of a mask device provided by an embodiment of the present invention, Figure 5 1 is a cross-sectional view of a mask device provided in an embodiment of the present invention, and the mask device is used to encapsulate the display device 100 provided in the above embodiment. Figure 4 The mask device 200 includes: a mask body 210. The mask body 210 includes an edge region 211 located at an edge of the mask body 210 and a middle region 212 located at a middle of the mask body 210. Figure 4-5 The middle region 212 includes a plurality of hollow regions 2121 and a bump layer 2122 fixedly arranged in a direction perpendicular to the plane where the mask body 210 is located. Figure 4-5 The edge area 211 is designed with at least two package alignment marks 2111 .

[0049] Figure 6 A schematic diagram of laminating a mask device and a wafer substrate provided by an embodiment of the present invention, specifically a schematic diagram of laminating a mask device 200 provided by the above embodiment and a wafer substrate A. Figure 6 In the embodiment of the present invention, the package alignment mark 2111 and the wafer alignment mark A2 are set correspondingly.

[0050] refer to Figure 3-6 In the embodiment of the present invention, the arrangement of the hollow area 2121 is the same as that of the chip A1, and multiple hollow areas 2121 form a mesh of hollow openings. When the mask device 200 and the wafer substrate A are attached, the edge area 211 and the bump layer 2122 are in contact with the surface of the wafer substrate A, and there is a gap between the mesh surface of the mesh of the hollow opening and the surface of the wafer substrate A. In the embodiment of the present invention, the size of the hollow area 2121 is larger than the size of the glass cover.

[0051] It can be understood that the height of the edge area 211 in the direction perpendicular to the wafer substrate A is greater than the height of the hollow area 2121, and the sum of the heights of the hollow area 2121 and the bump layer 2122 in the direction perpendicular to the wafer substrate A is equal to the height of the edge area 211, so that when the mask device 200 and the wafer substrate A are bonded, the edge area 211 and the bump layer 2122 are in contact with the surface of the wafer substrate A, and there is a gap between the mesh surface of the mesh hollow opening and the surface of the wafer substrate A.

[0052] The corresponding arrangement of the package alignment mark 2111 and the wafer alignment mark A2 in the mask device 200 of the present invention can ensure the bonding accuracy. The arrangement of the hollow area 2121 is the same as that of the chip A1, and the size of the hollow area 2121 is larger than the size of the glass cover plate, which can limit the offset position of the glass cover plate. The bump layer 2122 is arranged in the non-hollow area to avoid scratching the display area of ​​the wafer substrate A. When the mask device 200 and the wafer substrate A are bonded, the edge area 211 and the bump layer 2122 are in contact with the surface of the wafer substrate A, and there is a gap between the mesh surface of the mesh hollow opening and the surface of the wafer substrate A, which can make the mask device 200 uniformly stressed as a whole and will not deform after long-term use.

[0053] Optionally, based on the above embodiment, continue to refer to Figure 4 The bump layer 2122 includes at least two bumps 21221. The bumps 21221 are arranged at the center of the mesh intersection of the mesh-shaped hollow openings.

[0054] In the embodiment of the present invention, the protrusions 21221 are arranged at the centers of the intersections of the mesh surfaces of the mesh-shaped hollow openings, so as to avoid scratching the display area of ​​the wafer substrate A.

[0055] Optionally, based on the above embodiment, the shape of the cross section of the protrusion 21221 along the direction parallel to the plane where the mask body 210 is located is circular.

[0056] Optionally, based on the above embodiment, continue to refer to Figure 4 The number of protrusions 21221 is the same as the number of intersections of the mesh surface of the mesh hollow openings.

[0057] In the embodiment of the present invention, the number of the protrusions 21221 is the same as the number of the mesh intersections of the mesh hollow openings, so that the mask device 200 is evenly stressed as a whole and does not deform after long-term use.

[0058] Optionally, based on the above embodiment, the package alignment mark 2111 includes a circular hole.

[0059] Optionally, based on the above embodiment, the material of the mask plate body 210 includes iron-nickel alloy and stainless steel.

[0060] Specifically, the iron-nickel alloy may be Invar36, and the stainless steel may be SUS420, which are suitable for high-precision processing and have a low expansion coefficient, ensuring dimensional accuracy in various production environments without deformation.

[0061] Optionally, based on the above embodiment, continue to refer to Figure 4 The projection of the hollow area 2121 on the plane where the mask body 210 is located is a rectangle. In the embodiment of the present invention, the difference between the width of the hollow area 2121 and the width of the glass cover is in the range of 50-100 μm. The difference between the length of the hollow area 2121 and the length of the glass cover is in the range of 50-100 μm.

[0062] In the embodiment of the present invention, the size of the hollow area 2121 is larger than the size of the glass cover plate, which can limit the offset position of the glass cover plate and strictly limit the offset amplitude of the glass cover plate after mounting while avoiding collision of the glass cover plate.

[0063] The corresponding arrangement of the package alignment mark 2111 and the wafer alignment mark A2 in the mask device 200 of the present invention can ensure the bonding accuracy. The arrangement of the hollow area 2121 is the same as that of the chip A1, and the size of the hollow area 2121 is larger than the size of the glass cover plate, which can limit the offset position of the glass cover plate. The bump layer 2122 is arranged in the non-hollow area to avoid scratching the display area of ​​the wafer substrate A. When the mask device 200 and the wafer substrate A are bonded, the edge area 211 and the bump layer 2122 are in contact with the surface of the wafer substrate A, and there is a gap between the mesh surface of the mesh hollow opening and the surface of the wafer substrate A, which can make the mask device 200 uniformly stressed as a whole and will not deform after long-term use. The bump 21221 is arranged at the center of the mesh intersection of the mesh surface of the mesh hollow opening, which can avoid scratching the display area of ​​the wafer substrate A.

[0064] Figure 7 A flowchart of a method for packaging a display device provided in an embodiment of the present invention, which is used to package the display device provided in the above embodiment, with reference to Figure 7 , the packaging method of the display device includes:

[0065] S710, coating liquid optical adhesive on the wafer substrate to form an optical adhesive layer.

[0066] S720, aligning the mask device and the wafer substrate and attaching them together.

[0067] It is understandable that the alignment accuracy of the mask device is very important. If there is a deviation during alignment, it will cause the glass cover to collide with the mask device when the glass cover is subsequently attached. In order to ensure the bonding accuracy, when the package alignment mark and the wafer alignment mark completely overlap during alignment, it is determined that the alignment is completed and the mask device is lowered to align with the wafer substrate.

[0068] S730 , attaching glass cover plates one by one on the hollow areas of the mask device to form a glass cover plate layer.

[0069] Figure 8 A schematic diagram of a glass cover plate provided by an embodiment of the present invention, referring to Figure 8 , the glass cover plates 151 are attached one by one in the hollow areas 2121. It should be noted that a high-precision attaching device can be selected to avoid collision between the glass cover plate 151 and the mask device 200.

[0070] S740, uses high pressure degassing process and ultraviolet irradiation curing process to cure the optical adhesive layer.

[0071] It should be noted that during high-pressure degassing and UV curing, although the glass cover is located on the flowable liquid optical adhesive, the position deviation is strictly limited by the mask device until the liquid optical adhesive is completely cured. When the mask device and the wafer substrate are in the bonding state, since the hollow mesh surface of the mask device does not directly contact the surface of the wafer substrate, the mask device will not be contaminated by a small amount of glue overflowing from the periphery of the glass cover, ensuring the cleanliness and service life of the mask device.

[0072] S750, removing the mask device and cutting the wafer substrate to form a display device.

[0073] The packaging method of the display device provided by the present invention performs mounting of the glass cover plate after the mask device and the wafer substrate are precisely aligned. During the extension of the glue under the glass cover plate, the hollow opening of the mask device can limit the movement of the glass cover plate and keep the position fixed. The mask device is removed after the UV curing is completed. This process can significantly reduce the poor quality of the glass cover plate offset and eliminate the negative impact of the glass cover plate offset on the subsequent wafer cutting and optical module installation.

[0074] In addition, the packaging method of the display device provided in the embodiment of the present invention is used to package the display device provided in the above embodiment, and the display device provided in the above embodiment is packaged using the mask device provided in the above embodiment, and therefore has the same beneficial effects. For the contents not described in detail in this embodiment, reference can be made to the mask device provided in the above embodiment, and they will not be repeated here.

[0075] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A mask device, characterized in that: Used for packaging a display device, the display device comprises a wafer substrate and a packaging component; the wafer substrate comprises a plurality of chips, a light-emitting element layer and a wafer alignment mark; the packaging component comprises a glass cover layer, and the glass cover layer comprises a glass cover; The mask device comprises: a mask plate main body; The mask plate body includes an edge area located at the edge position of the mask plate body and a middle area located at the middle position of the mask plate body; the middle area includes a plurality of hollow areas and bump layers fixedly arranged in a direction perpendicular to the plane where the mask plate body is located; the edge area is designed with at least two package alignment marks, and the package alignment marks and the wafer alignment marks are arranged correspondingly; The arrangement of the hollow areas is the same as that of the chips, and the size of the hollow areas is larger than that of the glass cover plate, and a plurality of the hollow areas form a mesh of hollow openings; When the mask device and the wafer substrate are attached, the edge region and the bump layer are in contact with the surface of the wafer substrate, and a gap exists between the mesh surface of the mesh-shaped hollow opening and the surface of the wafer substrate.

2. The mask device according to claim 1, characterized in that: The bump layer includes at least two bumps; The convex point is arranged at the center of the mesh intersection of the mesh-shaped hollow opening.

3. The mask device according to claim 2, characterized in that: The cross-section of the protrusion along the direction parallel to the plane where the mask plate main body is located is circular.

4. The mask device according to claim 2, characterized in that: The number of the protrusions is the same as the number of mesh intersections of the mesh-shaped hollow openings.

5. The mask device according to claim 1, characterized in that: The package alignment mark includes a round hole.

6. The mask device according to claim 1, characterized in that: The material of the mask plate body includes iron-nickel alloy and stainless steel.

7. The mask device according to claim 1, characterized in that: The projection of the hollow area on the plane where the mask plate body is located is a rectangle, and the difference between the width of the hollow area and the width of the glass cover plate is in the range of 50-100 μm; the difference between the length of the hollow area and the length of the glass cover plate is in the range of 50-100 μm.

8. A display device, characterized in that: Using the mask device package according to any one of claims 1 to 7, the display device comprises: Silicon-based semiconductor circuit substrate; A light emitting element layer located on one side of the silicon-based semiconductor circuit substrate; A thin film encapsulation layer located on a side of the light emitting element layer away from the silicon-based semiconductor circuit substrate; An optical adhesive layer located on a side of the thin film encapsulation layer away from the light emitting element layer; A glass cover layer located on a side of the optical adhesive layer away from the thin film encapsulation layer; Wherein, the display device comprises a wafer substrate and a packaging component, the wafer substrate comprises the silicon-based semiconductor circuit substrate, the light-emitting element layer and the thin-film packaging layer, and the packaging component comprises the optical adhesive layer and the glass cover layer.

9. The display device according to claim 8, characterized in that: The wafer substrate further includes: a color filter layer; The color filter layer is located between the thin film encapsulation layer and the optical adhesive layer.

10. A method for packaging a display device, characterized in that: For packaging the display device according to claim 8 or 9, the packaging method of the display device comprises: Coating liquid optical adhesive on the wafer substrate to form an optical adhesive layer; Aligning the mask device with the wafer substrate and attaching them together; Mounting glass cover plates one by one on the hollow areas of the mask device to form a glass cover plate layer; The optical adhesive layer is cured by using a high-pressure degassing process and an ultraviolet irradiation curing process; The mask device is removed, and the wafer substrate is cut to form the display device.

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