Optical proximity effect correction method of ion implantation layer and semiconductor device manufacturing method

Abstract

The invention provides an optical proximity effect correction method of an ion implantation layer and a semiconductor device manufacturing method, and the method comprises the steps: firstly cutting off a convex corner in a corner-to-corner structure with a small interval in an original layout of the ion implantation layer, and then carrying out the OPC of the layout after the corner cutting, according to the method, the limitation of mask rule inspection on the corner-to-corner structures can be avoided, and the space for correcting the optical proximity effect is enlarged, so that the key size of a final layout obtained by OPC can meet a target value, the problem of process hot spots caused by easy distortion of a corner-to-corner structure pattern in an ion implantation layer in the prior art can be solved, and the quality of the ion implantation layer is improved. And the accuracy of OPC correction is improved, so that a more accurate final layout of the ion implantation layer is provided. According to the manufacturing method of the semiconductor device, the final layout of the required ion implantation layer is obtained by using the optical proximity effect correction method of the ion implantation layer, so that the yield and the performance of a product can be finally improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device manufacturing, and in particular to an optical proximity effect correction method for an ion implantation layer and a semiconductor device manufacturing method. Background Art

[0002] Ion implantation is an indispensable process in the manufacturing of semiconductor devices. It first uses a photolithography process to make the photoresist cover the silicon wafer areas that do not need ion implantation, and then uses an ion implanter to inject specific impurity atoms into the silicon wafer areas exposed by the photoresist to achieve doping of specific areas of the silicon wafer.

[0003] In advanced semiconductor device manufacturing processes, due to the particularity of the ion implantation layer, the original layout of the ion implantation layer is usually generated by logical operations on other levels of layout, in which some corner-to-corner structures are prone to appear.

[0004] Moreover, with the continuous development of semiconductor device manufacturing process technology, the characteristic size of the layout graphics of the ion implantation layer is getting smaller and smaller, and the spacing between these corner-to-corner structures is also getting smaller and smaller, which is very likely to become a process hotspot where the actual window is insufficient in the lithography process, and ultimately lead to poor lithography problems.

[0005] Please refer to Figure 1 , although the optical proximity correction (OPC) technology has been used in the prior art to compensate and correct the graphics of the original layout of the ion implantation layer to avoid certain deformation and deviation problems between the photolithography graphics obtained on the actual silicon wafer and the layout graphics of the ion implantation layer. However, since the layout graphics of the ion implantation layer are mostly generated by logical operations, the graphics are complex, and the influence of the reflection of the front layer is changeable, in order to avoid the waste of OPC computing resources, the existing OPC technology often undercompensates for these corner-to-corner structures, and even is limited by the mask rule check (MRC, which refers to the inspection that must be done before the design graphics are sent to the mask production factory after optical proximity correction processing) and does not compensate for these corner-to-corner structures, which directly leads to the problem of obvious corner-to-corner structural distortion in the photolithography graphics of the ion implantation layer obtained by the final exposure. Summary of the invention

[0006] An object of the present invention is to provide a method for correcting the optical proximity effect of an ion implantation layer, which can solve the problem that the corner-to-corner structure pattern in the ion implantation layer is easily distorted and causes process hot spots, and improve the accuracy of OPC correction.

[0007] Another object of the present invention is to provide a method for manufacturing a semiconductor device, which can improve product yield and electrical performance.

[0008] To achieve the above object, the present invention provides a method for correcting the optical proximity effect of an ion implantation layer, which comprises the following steps: Providing the original layout of the ion implantation layer; Finding a corner-to-corner structure to be processed from the original layout, wherein the corner-to-corner structure includes two convex corners with different angular directions, and the distance between the vertices of the two convex corners is less than a preset distance; Cut off each of the convex corners in the corner-to-corner structure, and after the corner cutting, a new straight edge or a rounded corner protruding outward is generated at each of the convex corners to obtain a layout after the corner cutting; The optical proximity effect is corrected for the corner-cut layout to obtain a final layout of the ion implantation layer.

[0009] Optionally, the preset distance is greater than or equal to the minimum spacing of the layout; and / or, before cutting the corners, the distance between the vertices of the two convex corners is less than the minimum spacing of the layout.

[0010] Optionally, each of the convex angles is a right angle; and / or, the vertices of the two convex angles in the corner-to-corner structure coincide.

[0011] Optionally, the corner-to-corner structure is two ion implantation regions in the ion implantation layer that are corner-to-corner and rectangular, and after corner cutting, the spacing between the convex corners of the two ion implantation regions is greater than or equal to the preset distance.

[0012] Optionally, before corner cutting, the length of each side of each convex corner is greater than the minimum graphic size of the layout.

[0013] Optionally, the sizes of the convex corners cut off in the corner-to-corner structure are the same; and / or, when a new straight edge is generated at each convex corner after cutting, the new straight edges generated at each convex corner are parallel.

[0014] Optionally, the length of each side of each of the convex corners that is cut off is not greater than 1 / 2 of the length of the corresponding side of the convex corner before the corner cutting process.

[0015] Optionally, the length of each side of each convex corner cut off is not greater than the minimum spacing of the layout. .

[0016] Optionally, a layout of a related front layer is provided, and a logic operation is performed based on the layout of the related front layer to generate the original layout; and / or each of the convex corners in the corner-to-corner structure is cut off by using EDA tool layout design software.

[0017] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which comprises: The optical proximity effect correction method of the ion implantation layer according to the present invention is used to obtain the final layout of the desired ion implantation layer; transferring the final layout of the ion implantation layer onto a photomask; Transferring the pattern on the photomask to the photoresist on the corresponding silicon wafer through a photolithography process; An ion implanter is used to implant specific impurity atoms into the silicon wafer region exposed by the photoresist, so as to form a desired ion implantation layer in the silicon wafer.

[0018] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: 1. The optical proximity effect correction method of the ion implantation layer of the present invention first cuts off the convex corners in the small-pitch corner-to-corner structure in the original layout of the ion implantation layer, and then performs optical proximity effect correction (OPC) on the layout after cutting, which can avoid the restrictions of mask rule checking (MRC) on these corner-to-corner structures, increase the space for optical proximity effect correction, so that the key size of the final layout obtained by OPC can meet the target value, and can solve the problem of process hotspots caused by the easy distortion of the corner-to-corner structure pattern in the ion implantation layer under the prior art, improve the accuracy of OPC correction, and thus provide a more accurate final layout of the ion implantation layer.

[0019] 2. The semiconductor device manufacturing method of the present invention utilizes the optical proximity effect correction method of the ion implantation layer of the present invention to obtain the desired final layout of the ion implantation layer, and transfers the final layout of the ion implantation layer to the mask, and further transfers it to the photoresist on the silicon wafer through the photolithography process. Since the final layout of the ion implantation layer is accurate, the difference between the photoresist pattern obtained on the actual silicon wafer and the layout pattern of the ion implantation layer can meet the requirements of the ion implantation process, thereby ultimately being able to improve the product yield and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Figure 1 It is a schematic diagram of layout changes in the existing proximity effect correction method of the ion implantation layer.

[0021] Figure 2 It is a schematic flow chart of a method for correcting proximity effect of an ion implantation layer according to a specific embodiment of the present invention.

[0022] Figure 3 It is an exemplary schematic diagram of layout changes in a method for correcting proximity effect of an ion implantation layer according to a specific embodiment of the present invention.

[0023] Figure 4It is another exemplary schematic diagram of layout changes in the method for correcting proximity effect of the ion implantation layer according to a specific embodiment of the present invention.

[0024] Figure 5 It is a schematic flow chart of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention.

[0025] Figure 6 It is a schematic diagram of the cross-sectional structure of a device in a semiconductor device manufacturing method according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0026] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0027] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0028] Please refer to Figure 2 and Figure 3 According to an embodiment of the present invention, a method for correcting an optical proximity effect of an ion implantation layer is provided, which comprises the following steps: S11, providing an original layout of the ion implantation layer; S12, finding a corner-to-corner structure to be processed from the original layout, wherein the corner-to-corner structure includes two convex corners with different angular directions, and a distance between the vertices of the two convex corners is less than a preset distance; S13, cutting off each of the convex corners in the corner-to-corner structure, generating a new straight edge or a rounded corner protruding outward at each of the convex corners after cutting, and obtaining a layout after cutting; S14, performing optical proximity effect correction on the corner-cut layout to obtain a final layout of the ion implantation layer.

[0029] In step S11, a layout of a related front layer (not shown) is provided, and the related front layer may include at least one of a fin, a shallow trench isolation structure, an active area, and a gate; then a logic operation is performed based on the layout of the related front layer to generate an original layout of the ion implantation layer. The original layout of the ion implantation layer may have a plurality of ion implantation areas spaced apart from each other, and these ion implantation areas may include at least one of any suitable shapes such as a rectangle, an L shape, a right angle U shape, etc., and adjacent ion implantation areas (such as Figure 2 ) can be due to the proximity of the vertex angles (such as Figure 2 ) to form a diagonal structure.

[0030] Please refer to Figure 2 and Figure 3 In step S12, the corner-to-corner structures to be processed are found from the original layout of the ion implantation layer. These corner-to-corner structures include two convex corners 3 and 4 with different angular directions, and the spacing between the vertices of the two convex corners 3 and 4 is less than a preset distance. The preset distance may be greater than or equal to the minimum spacing of the layout, for example, the preset distance is 1 to 3 times the minimum spacing of the layout. The minimum spacing of the layout refers to the minimum distance requirement between different layers or different geometric figures in the layout design, and is also the minimum line width and minimum spacing allowed for mask production. In layout design, the minimum spacing rule is one of the very important design rules. It ensures the minimum distance between different geometric figures, avoids electrical short circuits or open circuits, and ensures the stability and reliability of the layout design. The "minimum spacing of the layout" described in the present invention includes the minimum distance between the outer boundaries of geometric figures of different ion implantation areas in the same layer of the layout.

[0031] In one example, the preset distance is the minimum spacing of the layout. The spacing between the vertices of the two convex corners 3 and 4 in the corner-to-corner structure that needs to be processed (i.e., needs to be cut later) found in this step is less than the minimum spacing of the layout, and can be equal to 0, or even less than 0 (in this case, the two overlap to a degree not exceeding the minimum spacing of the layout). The convex corners 3 and 4 in this corner-to-corner structure need to be cut later, and the side length of the cut convex corner is greater than 0. If the spacing between the vertices of the two convex corners 3 and 4 is greater than or exactly equal to the minimum spacing of the layout, it is not the corner-to-corner structure that needs to be processed (i.e., needs to be cut later) found in this step, that is, this convex corner does not need to be cut later.

[0032] In one example, the vertices of the two convex corners 3 and 4 in the corner-to-corner structure to be processed found in this step overlap (that is, the distance between the vertices of the two convex corners 3 and 4 is 0).

[0033] In addition, it should be understood that the angles of the two convex corners 3 and 4 in the corner-to-corner structure to be processed found in this step depend on the graphic shape design of the ion implantation areas 1 and 2. For example, in one example, the corner-to-corner structure to be processed found in this step is two ion implantation areas 1 and 2 in the ion implantation layer that are corner-to-corner and rectangular, and at this time, the two convex corners 3 and 4 in the corner-to-corner structure are both right angles. In other examples, one or both of the convex corners 3 and 4 are acute angles or obtuse angles.

[0034] Furthermore, the lengths of the sides of each convex corner 3, 4 in the corner-to-corner structure to be processed found in this step are greater than the minimum graphic size of the layout. The minimum graphic size of the layout refers to the minimum size allowed for the graphic elements specified in the layout design rules (including the minimum line width, minimum spacing, shortest line length, etc. allowed by the layout design). The minimum graphic size of the layout ensures the manufacturability and reliability of each geometric figure in the layout, and prevents problems such as open circuits or short circuits during the integrated circuit manufacturing process. Generally speaking, the minimum spacing of the layout is smaller than the minimum graphic size of the layout. The "minimum graphic size of the layout" described in the present invention includes the minimum value of the side length of the geometric figure in the ion implantation area, etc.

[0035] For example, when the diagonal structures to be processed found in this step are two rectangular ion implantation regions 1 and 2, the length and width of the ion implantation regions 1 and 2 before corner cutting are both larger than the minimum pattern size of the layout.

[0036] Please continue to refer to Figure 2 and Figure 3 In step S13, each convex corner 3, 4 in the corner structure is cut off by the EDA tool layout design software to obtain a layout after corner cutting. The spacing d at the convex corners of the two ion implantation areas 1, 2 after corner cutting is greater than or equal to the preset distance. For example, the spacing d at the convex corners of the two ion implantation areas 1, 2 after corner cutting is greater than or equal to the minimum spacing of the layout.

[0037] Optionally, in step S13, the sizes of the convex corners 3 and 4 cut off in the corner-to-corner structure are the same.

[0038] In one example, in step S13, each convex corner 3, 4 cut off in the corner-to-corner structure is a triangle, and after the corner cutting, a new straight edge 5, 6 is generated at each convex corner 3, 4. Further optionally, the new straight edges 5, 6 generated at each convex corner 3, 4 are parallel. The spacing between the straight edges 5, 6 is also greater than or equal to the preset distance.

[0039] Please refer to Figure 4 In another example, in step S13, after cutting off each convex corner 3, 4, a rounded corner 3', 4' protruding outward can be generated at each convex corner 3, 4. After cutting, the distance between the rounded corners 3', 4' of the two ion implantation regions 1, 2 is also greater than or equal to the preset distance.

[0040] It should be understood that each convex corner 3, 4 cut off in this step S13 cannot be too small, otherwise the required optical proximity correction (OPC) effect cannot be achieved here later. Optionally, in this step S13, the length of each side of each convex corner 3, 4 cut off is greater than 0, and the distance between the straight edges 5, 6 generated after the corner cutting is not less than the minimum spacing of the layout. Similarly, each convex corner 3, 4 cut off in this step S13 cannot be too large, otherwise it will affect the injection area requirements corresponding to the ion implantation layer. Optionally, the length of each side of each convex corner cut off is not greater than 1 / 2 of the length of the corresponding side of the convex corner before the corner cutting process. For example, when the ion implantation areas 1, 2 are rectangular, the length of the side of the cut convex corners 3, 4 is not greater than 1 / 2 of the length of the long side of the ion implantation areas 1, 2, nor is it greater than 1 / 2 of the length of the wide side of the ion implantation areas 1, 2.

[0041] In one example, the length of each side of each of the convex corners 3 and 4 that are cut off is not greater than the minimum spacing of the layout. , and the distance between the straight edges 5 and 6 produced after cutting is not less than the minimum spacing of the layout.

[0042] Please continue to refer to Figure 2 and Figure 3In step S14, the optical proximity correction (OPC) software is used to perform optical proximity correction on the corner-cut layout according to a predetermined correction rule to obtain the final layout of the ion implantation layer. The optical proximity correction in this step can be an experience-based optical proximity correction or an experience-based optical proximity correction. The correction rule based on it can be any appropriate correction rule, for example, it can include moving the graphic edge of the corresponding ion implantation area in the layout of the ion implantation layer, adding additional polygons to the corresponding position of the ion implantation area, etc., which will not be described in detail here. contrast Figure 1 and Figure 3 It can be found that, when the changes to the layout design of the ion implantation layer are relatively small, the optical proximity effect correction method of the ion implantation layer described in the present invention not only avoids the restriction problem of the mask rule check (MRC) on the corner-to-corner structure in the ion implantation layer that is prone to become a process hotspot, but also increases the space for optical proximity effect correction by removing the convex corner thickness in the corner-to-corner structure, so that the key dimensions of the final layout obtained by OPC can meet the target value, and can solve the problem that the corner-to-corner structure pattern in the ion implantation layer is easily distorted and causes process hotspots under the prior art, improve the accuracy of OPC correction, and thus provide a more accurate final layout of the ion implantation layer. Therefore, the photoresist pattern after exposure obtained by the final layout obtained by OPC is closer to the target value, and thus when manufacturing semiconductor devices, the front layer structure formed before the ion implantation layer and the back layer structure formed after the ion implantation layer in the silicon wafer can have better coverage, thereby improving the product yield and performance.

[0043] Based on this, please refer to Figure 5 and Figure 6 An embodiment of the present invention further provides a method for manufacturing a semiconductor device, comprising: S20, using the optical proximity effect correction method of the ion implantation layer according to the present invention to obtain the final layout of the desired ion implantation layer; S21, transferring the final layout of the ion implantation layer onto the photomask 7; S22, transferring the pattern on the mask 7 to the photoresist 9 on the corresponding silicon wafer 8 through a photolithography process (including a series of processes such as coating, exposure, and development); S23 , using an ion implanter (not shown) to implant specific impurity atoms into the silicon wafer region exposed by the photoresist 9 , so as to form a desired ion implantation layer 10 in the silicon wafer 8 .

[0044] The semiconductor device manufacturing method of the present invention utilizes the optical proximity effect correction method of the ion implantation layer of the present invention to obtain the required final layout of the ion implantation layer, and transfers the final layout of the ion implantation layer to the mask, and further transfers it to the photoresist on the silicon wafer through the photolithography process. Since the final layout of the ion implantation layer is accurate, the difference between the photoresist pattern obtained on the actual silicon wafer and the layout pattern of the ion implantation layer can meet the requirements of the ion implantation process, thereby ultimately being able to improve the finished product yield and performance.

[0045] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for correcting the optical proximity effect of an ion implantation layer, characterized in that: The following steps are involved: Providing the original layout of the ion implantation layer; Finding a corner-to-corner structure to be processed from the original layout, wherein the corner-to-corner structure includes two convex corners with different angular directions, and the distance between the vertices of the two convex corners is less than a preset distance; Cut off each of the convex corners in the corner-to-corner structure, and after the corner cutting, a new straight edge or a rounded corner protruding outward is generated at each of the convex corners to obtain a layout after the corner cutting; The optical proximity effect is corrected for the corner-cut layout to obtain a final layout of the ion implantation layer.

2. The optical proximity effect correction method according to claim 1, characterized in that: The preset distance is greater than or equal to the minimum spacing of the layout; and / or, before cutting the corners, the distance between the vertices of the two convex corners is less than the minimum spacing of the layout.

3. The optical proximity effect correction method according to claim 1, characterized in that: The corner-to-corner structure is two ion implantation regions in the ion implantation layer that are corner-to-corner and rectangular, and after corner cutting, the distance between the convex corners of the two ion implantation regions is greater than or equal to the preset distance.

4. The optical proximity effect correction method according to claim 1, wherein: Each of the convex angles is a right angle; and / or, the vertices of the two convex angles in the corner-to-corner structure coincide.

5. The optical proximity effect correction method according to claim 1, wherein: The sizes of the convex corners cut off in the corner-to-corner structure are the same; and / or, when a new straight edge is generated at each convex corner after cutting, the new straight edges generated at each convex corner are parallel.

6. The optical proximity effect correction method according to claim 1, wherein: Before corner cutting, the length of each side of each convex corner is greater than the minimum graphic size of the layout.

7. The method for correcting the optical proximity effect according to claim 6, wherein: The length of each side of each of the convex corners that is cut off is not greater than 1 / 2 of the length of the corresponding side of the convex corner before the corner cutting process.

8. The method for correcting the optical proximity effect according to claim 6, wherein: The length of each side of each convex corner cut off is not greater than the minimum spacing of the layout. .

9. The method for correcting the optical proximity effect according to claim 1, wherein: Providing a layout of a related front layer, and performing a logic operation based on the layout of the related front layer to generate the original layout; and / or, cutting off each of the convex corners in the corner-to-corner structure through EDA tool layout design software.

10. A method for manufacturing a semiconductor device, characterized in that: include: Using the optical proximity effect correction method of the ion implantation layer according to any one of claims 1 to 9 to obtain the desired final layout of the ion implantation layer; transferring the final layout of the ion implantation layer onto a photomask; Transferring the pattern on the photomask to the photoresist on the corresponding silicon wafer through a photolithography process; An ion implanter is used to implant specific impurity atoms into the silicon wafer region exposed by the photoresist, so as to form a desired ion implantation layer in the silicon wafer.

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