Standard cell layout generation method and device, computer equipment and storage medium

Abstract

The invention relates to a standard cell layout generation method and device, computer equipment, a storage medium and a computer program product. The method comprises the steps that a layout unit frame is constructed based on layout design specifications and design parameters of a standard unit layout, and a transistor arrangement area, a metal layer line channel and a grid layer line channel in the standard unit layout are preset in the layout unit frame; according to the design parameters, the use number M of the layout unit frames is determined, the standard unit layout is drawn after the M layout unit frames are spliced, and M is a positive integer. By adopting the method, the standard cell layout meeting the DRC can be quickly designed.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method, apparatus, computer equipment, storage medium and computer program product for generating a standard cell layout. Background Art

[0002] Standard cell library is the basis of integrated circuit design. Integrated circuit design based on standard cell library can perform logic synthesis and layout routing, thus improving circuit design efficiency.

[0003] The standard cell library includes several pre-designed standard cell layout templates (English: Standard Cell template). The integrated circuit designer or circuit design synthesis tool calls the standard cell layout template in the standard cell library to complete the layout design of the integrated circuit according to the design requirements. Summary of the invention

[0004] Based on this, a standard cell layout generation method, apparatus, computer equipment, computer readable storage medium and computer program product are provided, which can quickly design a standard cell layout that meets the design specification (abbreviated as: DRC, Design Rule Check).

[0005] In a first aspect, the present application provides a method for generating a standard cell layout. The method comprises:

[0006] Constructing a layout unit framework based on the layout design specification and the design parameters of the standard unit layout, wherein the layout unit framework is preset with transistor arrangement areas, metal layer traces and gate layer traces in the standard unit layout;

[0007] The number M of the layout unit frames to be used is determined according to the design parameters, and the standard unit layout is drawn after splicing the M layout unit frames, where M is a positive integer.

[0008] In one embodiment, constructing a layout unit framework based on layout design specifications and design parameters of a standard unit layout includes:

[0009] Setting the position and size of the transistor layout area based on the design parameters of the standard cell layout;

[0010] Setting the position and quantity of the metal layer traces and the spacing between the metal layer traces based on the position and size of the transistor layout area and the layout design specification;

[0011] The position and number of the gate layer traces and the spacing between the gate layer traces are set based on the position and size of the transistor arrangement area and the layout design specification.

[0012] In one embodiment, constructing a layout unit framework based on the layout design specification and the design parameters of the standard unit layout further includes:

[0013] Determine the length of the layout unit frame according to the spacing between the metal layer traces and the number of the metal layer traces;

[0014] The width of the layout unit frame is determined according to the gate width of the transistor and the spacing between the gates of adjacent transistors.

[0015] In one embodiment, the width of the layout unit frame is the sum of the gate width of the transistor and the spacing between the gates of adjacent transistors, and the length of the layout unit frame is the product of the number of metal layer lines and the unit length, and the unit length is the sum of the metal layer line width and the spacing between the metal layer lines.

[0016] In one of the embodiments, the transistor includes a first conductivity type transistor and a second conductivity type transistor, and a layout region of the first conductivity type transistor and a layout region of the second conductivity type transistor are spaced apart along a first direction.

[0017] In one embodiment, the metal layer traces are arranged at intervals along the first direction, and the gate layer traces are arranged at intervals along the first direction.

[0018] In one embodiment, the M layout unit frames are arranged along a second direction, and the second direction is perpendicular to the first direction.

[0019] In one of the embodiments, a center line of the gate of the transistor extending along the first direction coincides with an edge line of adjacent layout unit frames.

[0020] In one embodiment, the number of the first conductive type transistors and the number of the second conductive type transistors are both less than M.

[0021] In one embodiment, M=n+1, where n is the larger value of the number of transistors of the first conductivity type and the number of transistors of the second conductivity type.

[0022] In one embodiment, the outermost standard cell frame is further provided with a dummy gate arrangement region.

[0023] In a second aspect, the present application also provides a standard cell layout generation device. The device comprises:

[0024] A framework construction module, used to construct a layout unit framework based on the layout design specification and the design parameters of the standard unit layout, wherein the layout unit framework is preset with the transistor layout area, metal layer traces and gate layer traces in the standard unit layout;

[0025] The frame splicing module is used to determine the number M of the layout unit frames to be used according to the design parameters, and to draw the standard unit layout after splicing the M layout unit frames, where M is a positive integer.

[0026] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0027] Constructing a layout unit framework based on the layout design specification and the design parameters of the standard unit layout, wherein the layout unit framework is preset with transistor arrangement areas, metal layer traces and gate layer traces in the standard unit layout;

[0028] The number M of the layout unit frames to be used is determined according to the design parameters, and the standard unit layout is drawn after splicing the M layout unit frames, where M is a positive integer.

[0029] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0030] Constructing a layout unit framework based on the layout design specification and the design parameters of the standard unit layout, wherein the layout unit framework is preset with transistor arrangement areas, metal layer traces and gate layer traces in the standard unit layout;

[0031] The number M of the layout unit frames to be used is determined according to the design parameters, and the standard unit layout is drawn after splicing the M layout unit frames, where M is a positive integer.

[0032] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0033] Constructing a layout unit framework based on the layout design specification and the design parameters of the standard unit layout, wherein the layout unit framework is preset with transistor arrangement areas, metal layer traces and gate layer traces in the standard unit layout;

[0034] The number M of the layout unit frames to be used is determined according to the design parameters, and the standard unit layout is drawn after splicing the M layout unit frames, where M is a positive integer.

[0035] The above-mentioned standard cell layout generation method, device, computer equipment, storage medium and computer program product first construct a layout unit framework based on the layout design specification and the design parameters of the standard cell layout. The layout unit framework is preset with the transistor layout area, metal layer line and gate layer line in the standard cell layout, and then the number M of layout unit frameworks to be used is determined according to the design parameters, and the M layout unit frameworks are spliced ​​to draw the standard cell layout. By defining the layout unit framework, the standard cell layout can be divided into multiple layout unit frames. In this way, the layout unit framework is first constructed based on the layout information, and then multiple layout unit frames are combined into a standard cell layout based on the layout information. With the assistance of the layout unit framework, the time for generating the standard cell layout can be effectively saved, and a standard cell layout that meets the DRC requirements can be quickly designed. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of a flow chart of a method for generating a standard cell layout in an embodiment;

[0037] Figure 2 is a schematic diagram of a layout unit framework in one embodiment;

[0038] Figure 3 for Figure 2 A schematic diagram of the transistor arrangement area;

[0039] Figure 4 for Figure 2 Schematic diagram of the middle metal layer line;

[0040] Figure 5 for Figure 2 Schematic diagram of the middle gate layer line;

[0041] Figure 6 for Figure 2 Schematic diagram of the power pin area in the middle;

[0042] Figure 7 is a circuit layout in one embodiment;

[0043] Figure 8 for Figure 7 The corresponding standard cell layout;

[0044] Fig. 9 for Figure 8 Schematic diagram of the middle metal layer line;

[0045] Fig.10 for Figure 8 Schematic diagram of the middle gate layer line;

[0046] Fig.11 is a flow chart of step 102 in one embodiment;

[0047] Fig.12 is a flow chart of step 102 in another embodiment;

[0048] Fig.13 is a schematic flow chart of a method for generating a standard cell layout in another embodiment;

[0049] Fig.14 is a structural block diagram of a standard cell layout generating device in one embodiment;

[0050] Fig.15 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0052] In one embodiment, Figure 1 As shown, a method for generating a standard cell layout is provided. This embodiment takes the method applied to a terminal as an example. It can be understood that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0053] Step 102 : constructing a layout unit framework based on the layout design specification and the design parameters of the standard unit layout.

[0054] The layout unit framework is preset with transistor arrangement areas, metal layer traces and gate layer traces in the standard unit layout.

[0055] Figure 2 is a schematic diagram of a layout unit framework in an embodiment, Figure 3 for Figure 2 Schematic diagram of the transistor layout area in the figure. Figure 4 for Figure 2 Schematic diagram of the middle metal layer line, Figure 5 for Figure 2 Schematic diagram of the middle gate layer line, Figure 6 for Figure 2 Schematic diagram of the power supply pin area, combined with Figure 2-Figure 6 The layout unit frame may include a transistor layout area 10, a metal layer trace 20, a gate layer trace 30, and a transistor pin area 40. The transistor layout area 10 is used to design transistors, the metal layer trace 20 is used to design metal layer traces, the gate layer trace 30 is used to design gate layer traces, and the transistor pin area 40 is used to design transistor pin connection points.

[0056] Specifically, Figure 3 As shown, the two transistor arrangement areas 10 are respectively a P-type transistor arrangement area 11 and an N-type transistor arrangement area 12, and the P-type transistor arrangement area 11 and the N-type transistor arrangement area 12 are arranged in a non-edge area of ​​the layout unit frame at intervals along the length direction of the layout unit frame. By splicing multiple layout unit frames, a standard unit layout of any number of transistors can be generated.

[0057] Combination Figure 4 , a power connection point 13 is provided in both the P-type transistor arrangement area 11 and the N-type transistor arrangement area 12, and a plurality of metal layer traces 20 are sequentially arranged in intervals along the length direction of the layout unit frame in the area except the power connection point 13 in the layout unit frame. Optionally, the plurality of metal layer traces 20 are evenly distributed in the area except the power connection point 13 in the layout unit frame, which can avoid interference between the traces to the greatest extent.

[0058] Combination Figure 5 A plurality of gate layer traces 30 are sequentially arranged in an area other than the transistor arrangement area 10 in the layout unit frame along a length direction of the layout unit frame.

[0059] like Figure 6 As shown, two transistor pin regions 40 are respectively arranged at two ends of the layout unit frame along the length direction.

[0060] Specifically, the layout design specification is a design rule that mainly includes two aspects: one is to specify the minimum allowable size of the graphics and the spacing between the graphics, and the other is to specify the maximum allowable overlay deviation between each layout. Designing the circuit layout based on the layout design specification can ensure the circuit performance, make the circuit easy to implement in the process, and achieve a higher yield rate.

[0061] Standard cell design refers to the technology of calling pre-designed functional cells from the library and arranging them in rows, leaving a certain wiring area between rows. These functional cells are standard cells. The shape of the standard cell layout is usually a rectangle, the length of the rectangle can be the same or almost the same, and the width of the rectangle can be different.

[0062] Figure 7 is a circuit layout in one embodiment, Figure 8 for Figure 7 The corresponding standard cell layout, combined with Figure 7 and Figure 8 A circuit layout is composed of multiple standard cell layouts. The multiple standard cell layouts can be partially or completely the same, and the multiple standard cell layouts can also be different from each other.

[0063] The transistor layout area in the standard cell layout is the layout area of ​​the transistor in the standard cell layout. The metal layer line in the standard cell layout is the layout area of ​​the metal layer line in the standard cell layout, such as Fig. 9 The grid pattern shown in FIG. 1 is located in the area where the gate layer line in the standard cell layout is arranged in the standard cell layout, such as Fig.10 The area where the dot pattern is shown.

[0064] The design parameters of the standard cell layout may include, but are not limited to, the overall planning of the standard cell, the number of metal layer lines, the spacing of the gates, the width of the transistors, the number of transistors, and the like.

[0065] Optionally, the terminal may first determine the relative position relationship between components such as transistors and wiring lines based on the overall planning of the standard unit, and then determine the layout area of ​​each component based on quantity requirements such as the number of wiring lines and the number of transistors, and finally determine the size of each component and the spacing between them based on layout design specifications and size requirements such as the spacing of the gate and the width of the transistor.

[0066] Step 104, determining the number M of layout unit frames to be used according to the design parameters, and connecting the M layout unit frames to draw a standard unit layout, where M is a positive integer.

[0067] The layout unit frame is preset with the transistor layout area, metal layer lines and gate layer lines in the standard unit layout. First, multiple layout unit frames are spliced ​​together, and then corresponding components are drawn in the corresponding areas of each layout unit frame. For example, transistors are designed in the transistor layout area, and routing is designed in the metal layer lines and gate layer lines to generate a standard unit layout.

[0068] In the above-mentioned standard cell layout generation method, a layout unit framework is first constructed based on the layout design specification and the design parameters of the standard cell layout. The layout unit framework is preset with the transistor layout area, metal layer traces and gate layer traces in the standard cell layout, and then the number M of layout unit frameworks to be used is determined according to the design parameters, and the M layout unit frameworks are spliced ​​to draw the standard cell layout. By defining the layout unit framework, the standard cell layout can be divided into multiple layout unit frameworks. In this way, a layout unit framework is first constructed based on the layout information, and then multiple layout unit frameworks are combined into a standard cell layout based on the layout information. With the assistance of the layout unit framework, the time for generating the standard cell layout can be effectively saved, and a standard cell layout that meets the DRC requirements can be quickly designed. Since the number of standard cells is large, generally about 1,000, the standard cell layout can be quickly designed, which can further effectively improve the design efficiency of the circuit.

[0069] Moreover, the generated standard cell layout has the following characteristics: first, they have the same height, second, they have the same lines, third, different standard cells are spliced ​​together to meet DRC, fourth, the two conductive types of transistors have corresponding areas, and fifth, they use the same power supply design. Such a standard cell layout can make full use of the lines, reduce the area and meet DRC.

[0070] In one embodiment, the transistor includes a first conductive type transistor and a second conductive type transistor, and the arrangement area of ​​the first conductive type transistor and the arrangement area of ​​the second conductive type transistor are arranged at intervals along a first direction. In this way, the layout unit frame includes the arrangement area of ​​the two transistors, which can be used to generate various standard cell layouts, such as a standard cell layout having both the first conductive type transistor and the second conductive type transistor, a standard cell layout having only the first conductive type transistor or the second conductive type transistor, and a standard cell layout without transistors.

[0071] Exemplarily, the first conductive type transistor may be a P-type transistor, and the second conductive type transistor may be an N-type transistor. Alternatively, the first conductive type transistor may be an N-type transistor, and the second conductive type transistor may be a P-type transistor. The first direction may be a length direction of the layout unit frame.

[0072] Optionally, the metal layer lines are spaced apart along the first direction, and the gate layer lines are spaced apart along the first direction. The metal layer lines and the gate layer lines are spaced apart along the first direction to avoid mutual interference between the lines, and the extension directions of the metal layer lines and the gate layer lines should be the same, which is also convenient for wiring.

[0073] Optionally, the M layout unit frames are arranged along a second direction, and the second direction is perpendicular to the first direction. Multiple layout unit frames are spliced ​​along the width direction of the layout unit frames, and the length and width of the generated standard unit layout are relatively good, and the various components in the layout unit frames are arranged in sequence along the length direction of the layout unit frames. Such splicing is conducive to arranging the same components together, which is convenient for routing.

[0074] Exemplarily, 2*M layout unit frames are arranged in two rows and M columns, the M layout unit frames in the same row are arranged along the second direction, and the two layout unit frames in the same column are arranged along the first direction. The number of metal layer traces in a layout unit frame can be L+0.5, where L is a positive integer, and at this time, 0.5 metal layer traces in the two layout unit frames in the same column are just spliced ​​into a complete metal layer trace.

[0075] Optionally, the middle line of the gate of the transistor extending along the first direction coincides with the edge line of the adjacent layout unit frames, so that when the layout unit frames are spliced ​​together, the spacing of the transistors in the layout unit frames can be ensured to meet the requirements.

[0076] Optionally, the number of transistors of the first conductivity type and the number of transistors of the second conductivity type are both less than M. In this way, a dummy transistor can be arranged in the standard cell layout so that a gap is left between the edge of the standard cell layout and the transistor arrangement position. Exemplarily, the size of the dummy transistor is the same as the size of the transistor, and the distance between the dummy transistor and the transistor is the same as the spacing between the transistors.

[0077] Optionally, M=n+1, where n is a larger value of the number of transistors of the first conductivity type and the number of transistors of the second conductivity type, so that dummy transistors can be provided outside both transistors.

[0078] Optionally, the outermost standard cell frame is further provided with a dummy gate arrangement region.

[0079] In one embodiment, Fig.11 As shown, step 102 includes:

[0080] Step 1102 , setting the position and size of the transistor layout area based on the design parameters of the standard cell layout.

[0081] Exemplarily, the layout area position and size of the transistors in the layout unit frame are determined according to the number, size and spacing of the transistors in the standard unit layout.

[0082] Step 1104 , setting the position and quantity of metal layer traces and the spacing between metal layer traces based on the position and size of the transistor layout area and the layout design specification.

[0083] For example, the position of the metal layer traces is first determined according to the position and size of the transistor layout area, and the spacing between the metal layer traces is then determined according to the layout design specification. Finally, the number of metal layer traces is determined according to the position of the metal layer traces and the spacing between the metal layer traces.

[0084] Step 1106 , setting the position and quantity of gate layer traces and the spacing between gate layer traces based on the position and size of the transistor layout area and the layout design specification.

[0085] For example, the position of the gate layer traces is first determined according to the position and size of the transistor layout area, and the spacing between the gate layer traces is then determined according to the layout design specification, and finally the number of gate layer traces is determined according to the position of the gate layer traces and the spacing between the gate layer traces.

[0086] In the above embodiment, the transistor layout area position and size are first set based on the design parameters of the standard cell layout, and then the metal layer line position, number and spacing between metal layer lines are set based on the transistor layout area position and size and the layout design specifications. The gate layer line position, number and spacing between gate layer lines are set based on the transistor layout area position and size and the layout design specifications. It is possible to construct a layout unit framework based on the layout design specifications and the design parameters of the standard cell layout.

[0087] Alternatively, if Fig.12 As shown, step 102 also includes:

[0088] Step 1202, determining the length of the layout unit frame according to the spacing between metal layer traces and the number of metal layer traces.

[0089] Exemplarily, the length of the layout unit frame is the product of the number of metal layer lines and the unit length, and the unit length is the sum of the metal layer line width and the spacing between the metal layer lines.

[0090] Optionally, the terminal first adds the metal layer line width and the spacing between the metal layer lines, and then multiplies the addition result by the number of metal layer lines to obtain the length of the layout unit frame.

[0091] Step 1204 , determining the width of the layout unit frame according to the gate width of the transistor and the spacing between the gates of adjacent transistors.

[0092] Exemplarily, the width of the layout unit frame is the sum of the gate width of the transistor and the spacing between the gates of adjacent transistors.

[0093] Optionally, the terminal adds the gate width of the transistor and the spacing between the gates of adjacent transistors to obtain the width of the layout unit frame.

[0094] In the above embodiment, the length of the layout unit frame is determined according to the spacing between metal layer lines and the number of metal layer lines, and the width of the layout unit frame is determined according to the gate width of the transistor and the spacing between the gates of adjacent transistors. The overall size of the layout unit frame can be obtained, which facilitates the construction of the layout unit frame and the generation of the standard unit layout.

[0095] In addition, standard cell layouts with the same gate width can be spliced ​​using the same layout cell framework to further improve layout generation efficiency.

[0096] In one embodiment, Fig.13 As shown, a specific implementation scheme of a standard cell layout generation method is provided, and the method includes the following steps:

[0097] Step 1302, determining the position, quantity and width of transistors according to the overall planning of the standard cell layout, and determining the length of the transistors based on the layout design specification.

[0098] Step 1304 , determining the location of the gate layer trace based on the length of the transistor.

[0099] Step 1306, determining the spacing of metal layer lines based on the layout design specification, and determining the position of the metal layer lines based on the position of the transistor, the spacing and the number of the metal layer lines.

[0100] For example, the position of the power connection point in the transistor arrangement area is first determined according to the position of the transistor, and then the position of the metal layer traces is determined according to the spacing and number of the metal layer traces on both sides opposite to the power connection point.

[0101] Step 1308, determining the length of the layout unit frame based on the location of the metal layer traces.

[0102] Step 1310 , determining the width of the layout unit frame based on the width of the transistor.

[0103] Exemplarily, the width of the layout unit frame is determined according to the gate width of the transistor and the spacing between the gates of adjacent transistors.

[0104] Step 1312, determine the number M of layout unit frames to be used, and splice the M layout unit frames to draw a standard unit layout, where M is a positive integer.

[0105] For example, when drawing a standard cell layout, the transistor is placed on the transistor layout area, the metal layer routing is placed on the metal layer line, and the gate layer routing is placed on the gate layer line, without the need to use a ruler for measurement. In addition, multiple layout unit frames can be directly spliced, and no further measurement is required. Therefore, the generation efficiency of the standard cell layout can be effectively improved.

[0106] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0107] Based on the same inventive concept, the embodiment of the present application also provides a standard cell layout generation device for implementing the standard cell layout generation method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more standard cell layout generation device embodiments provided below can refer to the limitations of the standard cell layout generation method above, and will not be repeated here.

[0108] In one embodiment, Fig.14 As shown, a standard cell layout generation device 1400 is provided, including: a frame construction module 1401 and a frame splicing module 1402, wherein:

[0109] The framework construction module 1401 is used to construct a layout unit framework based on the layout design specification and the design parameters of the standard unit layout. The layout unit framework is preset with the transistor layout area, metal layer traces and gate layer traces in the standard unit layout.

[0110] The frame splicing module 1402 is used to determine the number M of layout unit frames to be used according to the design parameters, and to splice the M layout unit frames to draw a standard unit layout, where M is a positive integer.

[0111] In one embodiment, the framework construction module 1401 is used to set the transistor layout area position and size based on the design parameters of the standard cell layout; set the metal layer line position, number and spacing between metal layer lines based on the transistor layout area position and size and the layout design specifications; set the gate layer line position, number and spacing between gate layer lines based on the transistor layout area position and size and the layout design specifications.

[0112] Optionally, the frame construction module 1401 is further used to determine the length of the layout unit frame according to the spacing between metal layer lines and the number of metal layer lines; determine the width of the layout unit frame according to the gate width of the transistor and the spacing between the gates of adjacent transistors.

[0113] Exemplarily, the width of the layout unit frame is the sum of the gate width of the transistor and the spacing between the gates of adjacent transistors, and the length of the layout unit frame is the product of the number of metal layer lines and the unit length, and the unit length is the sum of the metal layer line width and the spacing between the metal layer lines.

[0114] In one embodiment, the transistor includes a first conductive type transistor and a second conductive type transistor, and an arrangement region of the first conductive type transistor and an arrangement region of the second conductive type transistor are spaced apart along a first direction.

[0115] Optionally, the metal layer traces are arranged at intervals along the first direction, and the gate layer traces are arranged at intervals along the first direction.

[0116] Optionally, the M layout unit frames are arranged along a second direction, and the second direction is perpendicular to the first direction.

[0117] Exemplarily, a center line of a gate of a transistor extending along the first direction coincides with an edge line of adjacent layout unit frames.

[0118] Exemplarily, the number of first conductivity type transistors and the number of second conductivity type transistors are both less than M.

[0119] Further, M=n+1, where n is a larger value between the number of transistors of the first conductivity type and the number of transistors of the second conductivity type.

[0120] Furthermore, the outermost standard cell frame is also provided with a dummy gate arrangement area.

[0121] Each module in the above-mentioned standard cell layout generation device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0122] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.15 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a standard cell layout generation method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0123] Those skilled in the art will understand that Fig.15 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0124] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the following steps when executing the computer program: constructing a layout unit framework based on a layout design specification and design parameters of a standard unit layout, wherein the layout unit framework is preset with transistor arrangement areas, metal layer traces, and gate layer traces in the standard unit layout; determining the number M of layout unit frameworks to be used according to the design parameters, and drawing the standard unit layout after splicing M layout unit frameworks, where M is a positive integer.

[0125] In one embodiment, when the processor executes the computer program, the following steps are also implemented: setting the transistor layout area position and size based on the design parameters of the standard cell layout; setting the metal layer line position, number and spacing between metal layer lines based on the transistor layout area position and size and the layout design specifications; setting the gate layer line position, number and spacing between gate layer lines based on the transistor layout area position and size and the layout design specifications.

[0126] In one embodiment, when the processor executes the computer program, the following steps are also implemented: determining the length of the layout unit frame according to the spacing between metal layer lines and the number of metal layer lines; determining the width of the layout unit frame according to the gate width of the transistor and the spacing between the gates of adjacent transistors.

[0127] In one embodiment, when the processor executes the computer program, the following steps are also implemented: the width of the layout unit frame is the sum of the gate width of the transistor and the spacing between the gates of adjacent transistors, the length of the layout unit frame is the product of the number of metal layer lines and the unit length, and the unit length is the sum of the metal layer line width and the spacing between the metal layer lines.

[0128] In one embodiment, when the processor executes the computer program, the following steps are also implemented: the transistor includes a first conductivity type transistor and a second conductivity type transistor, and the arrangement area of ​​the first conductivity type transistor and the arrangement area of ​​the second conductivity type transistor are arranged at intervals along the first direction.

[0129] In one embodiment, when the processor executes the computer program, the following steps are further implemented: the metal layer traces are arranged at intervals along the first direction, and the gate layer traces are arranged at intervals along the first direction.

[0130] In one embodiment, when the processor executes the computer program, the following steps are further implemented: M layout unit frames are arranged along a second direction, and the second direction is perpendicular to the first direction.

[0131] In one embodiment, when the processor executes the computer program, the following steps are further implemented: a center line of the gate of the transistor extending along the first direction coincides with an edge line of adjacent layout unit frames.

[0132] In one embodiment, when the processor executes the computer program, the following steps are further implemented: the number of transistors of the first conductivity type and the number of transistors of the second conductivity type are both less than M.

[0133] In one embodiment, when the processor executes the computer program, the following steps are further implemented: M=n+1, where n is the larger value of the number of transistors of the first conductivity type and the number of transistors of the second conductivity type.

[0134] In one embodiment, when the processor executes the computer program, the following steps are further implemented: the outermost standard cell frame is further provided with a dummy gate arrangement region.

[0135] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: constructing a layout unit framework based on a layout design specification and design parameters of a standard unit layout, the layout unit framework being preset with transistor arrangement areas, metal layer traces, and gate layer traces in the standard unit layout; determining the number M of layout unit frameworks to be used according to the design parameters, and drawing the standard unit layout after splicing M layout unit frameworks, where M is a positive integer.

[0136] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: setting the transistor layout area position and size based on the design parameters of the standard cell layout; setting the metal layer line position, number and spacing between metal layer lines based on the transistor layout area position and size and the layout design specifications; setting the gate layer line position, number and spacing between gate layer lines based on the transistor layout area position and size and the layout design specifications.

[0137] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented: determining the length of the layout unit frame according to the spacing between metal layer lines and the number of metal layer lines; determining the width of the layout unit frame according to the gate width of the transistor and the spacing between the gates of adjacent transistors.

[0138] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented: the width of the layout unit frame is the sum of the gate width of the transistor and the spacing between the gates of adjacent transistors, the length of the layout unit frame is the product of the number of metal layer lines and the unit length, and the unit length is the sum of the metal layer line width and the spacing between the metal layer lines.

[0139] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the transistor includes a first conductivity type transistor and a second conductivity type transistor, and the arrangement area of ​​the first conductivity type transistor and the arrangement area of ​​the second conductivity type transistor are arranged at intervals along the first direction.

[0140] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: metal layer traces are arranged at intervals along a first direction, and gate layer traces are arranged at intervals along the first direction.

[0141] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: M layout unit frames are arranged along a second direction, and the second direction is perpendicular to the first direction.

[0142] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: a center line of the gate of the transistor extending along the first direction coincides with an edge line of adjacent layout unit frames.

[0143] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: the number of transistors of the first conductivity type and the number of transistors of the second conductivity type are both less than M.

[0144] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: M=n+1, where n is the larger value of the number of transistors of the first conductivity type and the number of transistors of the second conductivity type.

[0145] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: the outermost standard cell frame is further provided with a dummy gate arrangement region.

[0146] In one embodiment, a computer program product is provided, including a computer program, which implements the following steps when executed by a processor: constructing a layout unit framework based on a layout design specification and design parameters of a standard unit layout, the layout unit framework being preset with transistor arrangement areas, metal layer traces, and gate layer traces in the standard unit layout; determining the number M of layout unit frameworks to be used according to the design parameters, and drawing the standard unit layout after splicing M layout unit frameworks, where M is a positive integer.

[0147] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: setting the transistor layout area position and size based on the design parameters of the standard cell layout; setting the metal layer line position, number and spacing between metal layer lines based on the transistor layout area position and size and the layout design specifications; setting the gate layer line position, number and spacing between gate layer lines based on the transistor layout area position and size and the layout design specifications.

[0148] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented: determining the length of the layout unit frame according to the spacing between metal layer lines and the number of metal layer lines; determining the width of the layout unit frame according to the gate width of the transistor and the spacing between the gates of adjacent transistors.

[0149] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented: the width of the layout unit frame is the sum of the gate width of the transistor and the spacing between the gates of adjacent transistors, the length of the layout unit frame is the product of the number of metal layer lines and the unit length, and the unit length is the sum of the metal layer line width and the spacing between the metal layer lines.

[0150] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the transistor includes a first conductivity type transistor and a second conductivity type transistor, and the arrangement area of ​​the first conductivity type transistor and the arrangement area of ​​the second conductivity type transistor are arranged at intervals along the first direction.

[0151] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: metal layer traces are arranged at intervals along a first direction, and gate layer traces are arranged at intervals along the first direction.

[0152] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: M layout unit frames are arranged along a second direction, and the second direction is perpendicular to the first direction.

[0153] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: a center line of the gate of the transistor extending along the first direction coincides with an edge line of adjacent layout unit frames.

[0154] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: the number of transistors of the first conductivity type and the number of transistors of the second conductivity type are both less than M.

[0155] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: M=n+1, where n is the larger value of the number of transistors of the first conductivity type and the number of transistors of the second conductivity type.

[0156] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: the outermost standard cell frame is further provided with a dummy gate arrangement region.

[0157] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0158] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0159] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0160] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for generating a standard cell layout, characterized in that: The method comprises: Constructing a layout unit framework based on the layout design specification and the design parameters of the standard unit layout, wherein the layout unit framework is preset with transistor arrangement areas, metal layer traces and gate layer traces in the standard unit layout; The number M of the layout unit frames to be used is determined according to the design parameters, and the standard unit layout is drawn after splicing the M layout unit frames, where M is a positive integer.

2. The method for generating a standard cell layout according to claim 1, wherein: The construction of the layout unit framework based on the layout design specification and the design parameters of the standard unit layout includes: Setting the position and size of the transistor layout area based on the design parameters of the standard cell layout; Setting the position and quantity of the metal layer traces and the spacing between the metal layer traces based on the position and size of the transistor layout area and the layout design specification; The position and number of the gate layer traces and the spacing between the gate layer traces are set based on the position and size of the transistor arrangement area and the layout design specification.

3. The method for generating a standard cell layout according to claim 2, wherein: The construction of the layout unit framework based on the layout design specification and the design parameters of the standard unit layout also includes: Determine the length of the layout unit frame according to the spacing between the metal layer traces and the number of the metal layer traces; The width of the layout unit frame is determined according to the gate width of the transistor and the spacing between the gates of adjacent transistors.

4. The method for generating a standard cell layout according to claim 3, characterized in that: The width of the layout unit frame is the sum of the gate width of the transistor and the spacing between the gates of adjacent transistors, and the length of the layout unit frame is the product of the number of metal layer lines and the unit length, and the unit length is the sum of the metal layer line width and the spacing between the metal layer lines.

5. The method for generating a standard cell layout according to any one of claims 1 to 4, characterized in that: The transistor includes a first conductive type transistor and a second conductive type transistor, and an arrangement region of the first conductive type transistor and an arrangement region of the second conductive type transistor are arranged with an interval along a first direction.

6. The method for generating a standard cell layout according to claim 5, characterized in that: The metal layer traces are arranged at intervals along the first direction, and the gate layer traces are arranged at intervals along the first direction.

7. The method for generating a standard cell layout according to claim 5, characterized in that: The M layout unit frames are arranged along a second direction, and the second direction is perpendicular to the first direction.

8. The method for generating a standard cell layout according to claim 7, characterized in that: A center line of the gate of the transistor extending along the first direction coincides with an edge line of adjacent layout unit frames.

9. The method for generating a standard cell layout according to claim 8, characterized in that: The number of the first conductive type transistors and the number of the second conductive type transistors are both less than M.

10. The method for generating a standard cell layout according to claim 9, characterized in that: M=n+1, where n is the larger value of the number of the first conductive type transistors and the number of the second conductive type transistors.

11. The method for generating a standard cell layout according to claim 10, wherein: The outermost standard cell frame is also provided with a dummy gate arrangement area.

12. A standard cell layout generation device, characterized in that: The device comprises: A framework construction module, used to construct a layout unit framework based on the layout design specification and the design parameters of the standard unit layout, wherein the layout unit framework is preset with the transistor layout area, metal layer traces and gate layer traces in the standard unit layout; The frame splicing module is used to determine the number M of the layout unit frames to be used according to the design parameters, and to draw the standard unit layout after splicing the M layout unit frames, where M is a positive integer.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 11 are implemented.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

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