Memory bank testing method and device, equipment and storage medium

Abstract

The invention provides a memory bank testing method and device, equipment and a storage medium, relates to the technical field of computers, is applied to a server, and comprises the following steps: screening a current to-be-tested target address from a preset serial in-place detection address set when a to-be-tested memory bank on a memory slot is tested, the memory slot is controlled to be connected to a current target pull-down resistor corresponding to the current to-be-tested target address through a preset switching chip; testing the compatibility between the memory bank to be tested and the current target address to be tested; if the test is not passed, directly judging that the memory bank to be tested has function abnormality; and if the test is passed, screening out the next current target address to be tested, and skipping to the step of controlling the memory slot to be connected to the current target pull-down resistor corresponding to the current target address to be tested through the preset switching chip until the test is passed, and judging that the function of the memory bank to be tested is normal. Therefore, the memory testing efficiency is improved, and the influence on the service life of the memory is reduced.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory bar testing method, device, equipment and storage medium. Background Art

[0002] For servers, each CPU (Central Processing Unit) can support a large number of memory sticks. For example, in the Eagle Stream platform, a single CPU can support 4 IMCs (Integrated Memory Controllers), each IMC can support 2 memory channels, and each memory channel can support 2 memory slots, that is, a single CPU can support up to 16 memory sticks. Each CPU will connect IMC0 and IMC1 to a group of I2C channels, and IMC2 and IMC3 to a group of I2C channels. Therefore, if the CPU wants to read the EEPROM (Electrically Erasable Programmable Read-Only Memory) information in these 16 memory sticks, it is necessary to assign a different SPD (Serial Presence Detect) address to each memory stick in IMC0 and IMC1 in order to identify and read and write each memory stick separately. Similarly, it is necessary to assign a different SPD address to each memory stick in IMC2 and IMC3 in order to identify and read and write each memory stick separately. Since memory sticks are standard components and each memory stick is randomly inserted into a slot, each memory stick must be able to adapt to 8 SPD addresses and be able to be recognized and read and written normally. The commonly used method is to hard-code the SPD address of each memory slot in the memory stick test, and then insert and remove the same memory stick into different slots 8 times to verify the compatibility of the memory with each SPD address. This method is time-consuming and labor-intensive, and multiple insertions and removals of the memory also have a certain impact on its lifespan.

[0003] It can be seen that how to improve the test efficiency of the memory stick and reduce the impact on the life of the memory stick is a problem that those skilled in the art need to solve. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a memory stick testing method, device, equipment and storage medium, which avoids multiple plugging and unplugging of the memory stick during the testing process, can improve the testing efficiency and reduce the impact on the life of the memory stick.

[0005] In a first aspect, an embodiment of the present application provides a memory stick testing method, which is applied to a server, wherein a memory slot of a memory test motherboard in the server is connected to any one of a plurality of pull-down resistors through a corresponding preset switching chip, and different pull-down resistors correspond to different resistance values; the method comprises:

[0006] When testing the memory stick to be tested on the memory slot, a serial presence detection address is selected from the preset serial presence detection address set as the current target address to be tested, and the memory slot is controlled by the preset switching chip to be connected to the current target pull-down resistor corresponding to the current target address to be tested among the plurality of pull-down resistors;

[0007] When the memory slot is connected to the current target pull-down resistor, the compatibility between the memory stick to be tested and the current target address to be tested is tested to obtain a corresponding current compatibility test result, and it is determined whether the current compatibility test result indicates that the test is passed;

[0008] If the current compatibility test result indicates that the test fails, it is directly determined that the memory module to be tested on the current memory slot has a functional abnormality;

[0009] If the current compatibility test result indicates that the test has passed, the next serial in-place detection address is selected from the preset serial in-place detection address set as the current target address to be tested, and the process jumps to the step of controlling the memory slot to be connected to the current target pull-down resistor among the several pull-down resistors corresponding to the current target address to be tested through the preset switching chip, until the compatibility between the memory stick to be tested and each of the serial in-place detection addresses has been tested and passed, and it is determined that the memory stick to be tested on the current memory slot is functioning normally.

[0010] Optionally, before selecting a serial presence detection address from a preset serial presence detection address set as the current target address to be tested, the method further includes:

[0011] Determine the number of integrated memory controllers supported by the central processing unit on the memory test motherboard and the association relationship between the integrated memory controllers, and divide the integrated memory controllers based on the association relationship and the number of controllers to obtain a plurality of groups of test channels including the same number of integrated memory controllers; wherein each of the integrated memory controllers corresponds to two memory channels, and each of the memory channels corresponds to two memory slots;

[0012] A preset serial presence detection address set corresponding to each memory slot in the test channel is constructed using a plurality of serial presence detection addresses for testing memory sticks corresponding to each memory slot in the test channel, so as to select a serial presence detection address from the preset serial presence detection address set as the current target address to be tested.

[0013] Optionally, before testing the memory stick to be tested on the memory slot, the method further includes:

[0014] The central processing unit and the plurality of test channels are respectively connected through a plurality of preset communication switch circuits on the memory test mainboard; wherein one end of the preset communication switch circuit is connected to the central processing unit, and the other end is connected to any one of the plurality of memory slots corresponding to a single group of test channels;

[0015] Sorting the test channels in the groups according to the memory test tasks corresponding to the memory bars to be tested on the memory slots in the test channels in each group to obtain a first sequence representing the order of the test channels in the memory test process, and sorting the memory test tasks corresponding to the memory bars to be tested on the memory slots in a single group of the test channels to obtain a second sequence representing the order of the memory test tasks in the single group of the test channels in the memory test process;

[0016] When performing memory testing on the memory testing mainboard, the current test channel and the current memory slot where the memory test task to be executed is located are determined based on the first sequence and the second sequence respectively, and the central processing unit and the current memory slot of the current test channel are connected through the preset communication switch line to test the memory stick to be tested on the current memory slot.

[0017] Optionally, the testing the memory bar to be tested on the current memory slot includes:

[0018] If the memory bar to be tested on the current memory slot is determined to be malfunctioning or functioning normally, then based on the second sequence, the next memory test task is used as the current memory test task to be executed, and the process jumps to the step of connecting the central processing unit and the current memory slot of the current test channel through the preset communication switch line;

[0019] If the memory sticks to be tested in the current test channel have all been determined to be functionally abnormal or functionally normal, the next test channel is used as the current test channel based on the first sequence, and the memory test task to be executed and the corresponding current memory slot are determined based on the second sequence, and the process jumps to the step of connecting the central processing unit and the current memory slot of the current test channel through the preset communication switch line, so as to test the memory stick to be tested on the current memory slot.

[0020] Optionally, when the memory slot is connected to the current target pull-down resistor, testing the compatibility between the memory stick to be tested and the current target address to be tested to obtain a corresponding current compatibility test result includes:

[0021] When the memory slot is connected to the current target pull-down resistor, based on preset memory test rules, corresponding functional test operations are performed on the memory stick to be tested through the central processing unit on the memory test mainboard, so as to generate a current compatibility test result characterizing the compatibility between the memory stick to be tested and the current target address to be tested according to the test information corresponding to the functional test operation.

[0022] Optionally, after directly determining that the memory module to be tested on the current memory slot has a functional abnormality, the method further includes:

[0023] Trigger an alarm message indicating that the memory stick to be tested has a functional abnormality, so that relevant staff can replace the memory stick to be tested on the memory slot based on the alarm message, and then test the replaced memory stick on the memory slot.

[0024] Optionally, the step of selecting a serial presence detection address from a preset serial presence detection address set as the current target address to be tested includes:

[0025] Acquire the interaction information between the staff and the preset test software through the baseboard management controller, and select a serial presence detection address matching the interaction information from the preset serial presence detection address set as the current target address to be tested;

[0026] Or, based on the test code preset in the baseboard management controller, a serial presence detection address is selected from a preset serial presence detection address set as the current target address to be tested.

[0027] In a second aspect, the present application provides a memory stick test device, which is applied to a server, wherein a memory slot of a memory test motherboard in the server is connected to any one of a plurality of pull-down resistors through a corresponding preset switching chip, and different pull-down resistors correspond to different resistance values, and the device comprises:

[0028] An address determination module is used to select a serial presence detection address from a preset serial presence detection address set as a current target address to be tested when testing the memory bar to be tested on the memory slot, and control the memory slot to be connected to a current target pull-down resistor corresponding to the current target address to be tested among the plurality of pull-down resistors through the preset switching chip;

[0029] A compatibility test module, configured to test the compatibility between the memory stick to be tested and the current target address to be tested when the memory slot is connected to the current target pull-down resistor, so as to obtain a corresponding current compatibility test result, and determine whether the current compatibility test result indicates that the test has passed;

[0030] A first determination module, configured to directly determine that the memory module to be tested on the current memory slot has a functional abnormality when the current compatibility test result indicates that the test fails;

[0031] The second determination module is used for selecting the next serial in-place detection address from the preset serial in-place detection address set as the current target address to be tested when the current compatibility test result characterizes that the test has passed, and jumping to the step of controlling the memory slot to be connected to the current target pull-down resistor corresponding to the current target address to be tested among the several pull-down resistors through the preset switching chip, until the compatibility between the memory stick to be tested and each of the serial in-place detection addresses has been tested and passed, and it is determined that the memory stick to be tested on the current memory slot is functioning normally.

[0032] In a third aspect, the present application provides an electronic device, including:

[0033] Memory for storing computer programs;

[0034] A processor is used to execute the computer program to implement the steps of the above-mentioned memory bar testing method.

[0035] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the memory stick testing method described above are implemented.

[0036] It can be seen that in the present application, the memory slot of the memory test mainboard in the server is connected to any one of the pull-down resistors through the corresponding preset switching chip, and different pull-down resistors correspond to different resistance values. First, when testing the memory stick to be tested on the memory slot, a serial in-place detection address is screened out from the preset serial in-place detection address set as the current target address to be tested, and the memory slot is controlled by the preset switching chip to be connected to the current target pull-down resistor corresponding to the current target address to be tested among the several pull-down resistors; then, when the memory slot is connected to the current target pull-down resistor, the compatibility between the memory stick to be tested and the current target address to be tested is tested to obtain the corresponding current compatibility test result, and Determine whether the current compatibility test result indicates that the test has passed; if the current compatibility test result indicates that the test has not passed, directly determine that the memory bar to be tested on the current memory slot has a functional abnormality; if the current compatibility test result indicates that the test has passed, filter out the next serial in-place detection address from the preset serial in-place detection address set as the current target address to be tested, and jump to the step of controlling the memory slot to be connected to the current target pull-down resistor corresponding to the current target address to be tested among the several pull-down resistors through the preset switching chip, until the compatibility between the memory bar to be tested and each of the serial in-place detection addresses has been tested and passed, and determine that the memory bar to be tested on the current memory slot is functionally normal.

[0037] It can be seen from the above technical scheme that the beneficial effect of the present application lies in that the serial presence detection address of the memory slot on the memory test motherboard is controlled by adding a preset switching chip, and different serial presence detection addresses can be switched on a memory slot by connecting different pull-down resistors, thereby enabling a complete compatibility test of the memory stick on a single memory slot, avoiding multiple plugging and unplugging of the memory stick during the memory test process, improving the test efficiency of the memory stick, and reducing the impact of the memory test process on the life of the memory stick. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A flow chart of a memory stick testing method disclosed in this application;

[0040] Figure 2 A schematic diagram of a memory test mainboard with hard-coded serial in-place detection addresses for memory slots disclosed in the present application;

[0041] Figure 3 A schematic diagram of a memory test mainboard for switching serial in-place detection addresses of a memory slot disclosed in the present application;

[0042] Figure 4 A schematic diagram of the structure of a memory stick testing device disclosed in this application;

[0043] Figure 5 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0046] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0047] like Figure 1 As shown, the embodiment of the present application discloses a memory stick testing method, which is applied to a server, wherein a memory slot of a memory testing mainboard in the server is connected to any one of a plurality of pull-down resistors through a corresponding preset switching chip, and different pull-down resistors correspond to different resistance values; the method comprises:

[0048] Step S11, when testing the memory stick to be tested on the memory slot, select a serial presence detection address from the preset serial presence detection address set as the current target address to be tested, and control the memory slot to be connected to the current target pull-down resistor corresponding to the current target address to be tested among the several pull-down resistors through the preset switching chip.

[0049] In an embodiment of the present application, the memory slots of the memory test mainboard are all connected to any one of a number of pull-down resistors through a preset switching chip. The preset switching chip can connect the memory slot to a current target pull-down resistor corresponding to the current target address to be tested among a number of pull-down resistors according to the current target address to be tested selected from a preset serial in-place detection address set, thereby switching the serial in-place detection address of the memory slot. In a specific embodiment, during the process of testing the memory stick to be tested on the memory slot, a serial in-place detection address is selected from the preset serial in-place detection address as the current target address to be tested, wherein, before selecting a serial in-place detection address from the preset serial in-place detection address set as the current target address to be tested, it can also include: determining the number of integrated memory controllers supported by the central processing unit on the memory test motherboard and the association relationship between the integrated memory controllers, and dividing the integrated memory controllers based on the association relationship and the number of controllers to obtain a plurality of groups of test channels containing the same number of integrated memory controllers; wherein each of the integrated memory controllers corresponds to two memory channels, and each of the memory channels corresponds to two memory slots; and utilizing a plurality of serial in-place detection addresses for testing the memory sticks corresponding to the memory slots in a single group of the test channels to construct a preset serial in-place detection address set corresponding to each memory slot in the test channel, so as to select a serial in-place detection address from the preset serial in-place detection address set as the current target address to be tested. Specifically, the central processing unit on the memory test motherboard can support several integrated memory controllers; for example, a single CPU supports 4 IMCs, each IMC can support 2 memory channels, each memory channel can support 2 memory slots, that is, a single CPU can support up to 16 memory sticks; and the CPU can connect IMC0 and IMC1 to a group of I2C channels, and connect IMC2 and IMC3 to a group of I2C channels, and then it is necessary to assign SPD addresses to the memory sticks in each group of I2C channels in order to identify and test the corresponding memory sticks individually; accordingly, it is also necessary to assign SPD addresses to each memory stick in IMC2 and IMC3 in order to identify each memory stick individually and perform read and write tests; therefore, the memory stick needs to adapt 8 SPD addresses to be judged as functioning normally. In other words, a serial in-place detection address set can be constructed based on the default SPD addresses of each memory slot in the memory test motherboard, and in the subsequent process of testing the memory stick in a memory slot, an SPD address of the memory stick that has not been tested is selected from the serial in-place detection address set as the current target address to be tested.

[0050] In another specific embodiment, before testing the memory stick to be tested on the memory slot, the method may further include: connecting the central processing unit and several groups of the test channels respectively through several preset communication switch lines on the memory test mainboard; wherein one end of the preset communication switch line is connected to the central processing unit, and the other end is connected to any one of the several memory slots corresponding to the single group of the test channels; sorting the several groups of the test channels according to the memory test tasks corresponding to the memory stick to be tested on the memory slots in each group of the test channels to obtain a first sequence representing the order of the test channels during the memory test process, and sorting the memory test tasks corresponding to the memory stick to be tested on each memory slot in the single group of the test channels to obtain a second sequence representing the order of the several memory test tasks in the single group of the test channels during the memory test process; when performing a memory test on the memory test mainboard, determining the current test channel and the current memory slot where the current memory test task to be executed is located based on the first sequence and the second sequence respectively, and connecting the central processing unit and the current memory slot of the current test channel through the preset communication switch line, so as to test the memory stick to be tested on the current memory slot. Specifically, the memory test mainboard can connect the central processor and several groups of test channels through a preset communication switch line. During the memory test, one end of the preset communication switch line is connected to the central processor, and the other end is connected to the memory slot where the current memory bar to be tested in the single group of test channels is located, so as to test the memory bar to be tested; further, the several groups of test channels can be sorted according to the memory test tasks corresponding to the memory bars to be tested on the memory slots in each test channel to obtain a first sequence, so as to test the memory bars to be tested in several test channels based on the first sequence; and, for the memory bars to be tested in several memory slots in a single group of test channels, the several memory test tasks related to them can be sorted to obtain a second sequence, so as to test the several memory bars to be tested in the single group of test channels based on the second sequence. Correspondingly, in the subsequent memory test process, the current test channel is first determined based on the first sequence, and the current memory slot where the current memory bar to be tested is located is determined based on the second sequence corresponding to the test channel that represents the order of memory test tasks, and then the central processor and the current memory slot are connected through the preset communication switch line to test the current memory bar to be tested.

[0051] Further, in a specific embodiment, the testing of the memory bar to be tested on the current memory slot may include: if the memory bar to be tested on the current memory slot is determined to have a functional abnormality or to be functioning normally, then based on the second sequence, the next memory test task is used as the current memory test task to be executed, and the step of jumping to the current memory slot connecting the central processing unit and the current test channel through the preset communication switch line; if the memory bars to be tested in the current test channel have all been determined to have a functional abnormality or to be functioning normally, then based on the first sequence, the next test channel is used as the current test channel, and based on the second sequence, the current memory test task to be executed and the corresponding current memory slot are determined, and the step of jumping to the current memory slot connecting the central processing unit and the current test channel through the preset communication switch line is performed, so as to test the memory bar to be tested on the current memory slot. Specifically, in the process of testing the memory sticks to be tested based on the first sequence and the second sequence, in a single group of test channels, if a memory stick to be tested is determined to have a functional abnormality or to be functioning normally after testing, that is, when the test of a single memory stick to be tested is completed, the next memory test task can be used as the current memory test task to be executed based on the second sequence, and the central processing unit and the memory slot where the memory test task is located are connected through a preset communication switch line to perform a memory test; correspondingly, if all the memory sticks to be tested in the current test channel have been determined to have a functional abnormality or to be functioning normally, that is, all memory test tasks have been completed, the next test channel can be used as the current test channel based on the first sequence, and then the memory sticks to be tested therein can be tested based on the second sequence corresponding to the current test channel.

[0052] In a specific embodiment, the staff can intervene in the memory testing process according to actual needs, which may include: controlling the preset communication switch line through the preset interactive interface to connect the target memory slot to the central processing unit through the preset communication switch line; then the target memory slot can be used to test a single memory stick; after the test is completed, the staff can replace the new memory stick to be tested on the target memory slot and conduct a test. In addition, the staff can directly control the preset communication line switch to intervene in the memory testing process. For example, in a certain scenario, it is only necessary to test the compatibility of two memory sticks with different SPD addresses. The staff can use a single memory slot to test the two memory sticks in turn. During this period, the first memory stick needs to be manually unplugged and replaced with the second memory stick. In this way, the staff can choose the memory testing method according to the actual situation and personal preferences.

[0053] Step S12: When the memory slot is connected to the current target pull-down resistor, the compatibility between the memory stick to be tested and the current target address to be tested is tested to obtain a corresponding current compatibility test result, and determine whether the current compatibility test result indicates that the test has passed.

[0054] In an embodiment of the present application, during the process of testing the memory stick to be tested on the memory slot, the memory slot is first connected to the current target pull-down resistor corresponding to the current target address to be tested through a preset switching chip, and then the compatibility between the memory stick to be tested and the current target address to be tested is tested, and the corresponding current compatibility test result can be obtained. In a specific embodiment, when the memory slot is connected to the current target pull-down resistor, the compatibility between the memory stick to be tested and the current target address to be tested is tested to obtain the corresponding current compatibility test result, which may include: when the memory slot is connected to the current target pull-down resistor, based on the preset memory test rules, and through the central processing unit on the memory test motherboard, the memory stick to be tested is subjected to a corresponding functional test operation, so as to generate a current compatibility test result characterizing the compatibility between the memory stick to be tested and the current target address to be tested according to the test information corresponding to the functional test operation. Specifically, when the memory slot is connected to the current target pull-down resistor, the compatibility between the serial in-place detection address corresponding to the current target pull-down resistor and the memory stick to be tested can be tested based on the preset memory rules. For example, the central processor on the memory test motherboard can perform functional test operations such as reading and writing on the memory stick to be tested. After that, the current compatibility test result can be generated according to the test information corresponding to the functional test operation, which represents the compatibility between the memory stick to be tested and the current target address to be tested corresponding to the current target pull-down resistor.

[0055] Step S13: If the current compatibility test result indicates that the test fails, it is directly determined that the memory module to be tested on the current memory slot has a functional abnormality.

[0056] In an embodiment of the present application, after the compatibility test is performed on the memory bar to be tested, if the current compatibility test result obtained indicates that the test fails, such as the performance displayed by the memory bar test does not match the theoretical performance, it can be directly determined that the memory bar to be tested on the current memory slot has a functional abnormality. Further, in a specific embodiment, after the direct determination that the memory bar to be tested on the current memory slot has a functional abnormality, it can also include: triggering an alarm message indicating that the memory bar to be tested has a functional abnormality, so that the relevant staff can replace the memory bar to be tested on the memory slot based on the alarm message, and then test the replaced memory bar on the memory slot. Specifically, if it is determined that the memory bar to be tested has a functional abnormality, the corresponding alarm message can be triggered so that the relevant staff can replace the memory bar to be tested on the memory slot after checking the alarm message, and insert the new memory bar to be tested into the memory slot for memory testing.

[0057] Step S14: If the current compatibility test result indicates that the test has passed, the next serial in-place detection address is selected from the preset serial in-place detection address set as the current target address to be tested, and the process jumps to the step of controlling the memory slot to be connected to the current target pull-down resistor among the plurality of pull-down resistors corresponding to the current target address to be tested through the preset switching chip, until the compatibility between the memory stick to be tested and each of the serial in-place detection addresses has been tested and passed, and it is determined that the memory stick to be tested on the current memory slot is functioning normally.

[0058] In an embodiment of the present application, if the current compatibility test result indicates that the test has passed, that is, the memory stick to be tested on the current memory slot is normally compatible with the serial in-place detection address of the current memory slot, and the memory stick to be tested can exert theoretical performance, then the next serial in-place detection address can be screened out from the preset serial in-place detection address set as the current target address to be tested, and then the current memory slot is connected to the current target pull-down resistor corresponding to the latest screened current target address to be tested through the preset switching chip, so as to test the memory stick to be tested on the current memory slot using the next serial in-place detection address. Furthermore, if the compatibility test results between the memory stick to be tested on the current memory slot and all the serial in-place detection addresses in the preset serial in-place detection address set indicate that the test has passed, then it can be determined that the function of the memory stick to be tested is normal.

[0059] In a specific embodiment, the filtering out of a serial in-place detection address from a preset serial in-place detection address set as the current target address to be tested may include: obtaining interaction information between a staff member and a preset test software through a baseboard management controller, and filtering out a serial in-place detection address that matches the interaction information from the preset serial in-place detection address set as the current target address to be tested; or, filtering out a serial in-place detection address from a preset serial in-place detection address set as the current target address to be tested based on a test code preset in the baseboard management controller. Specifically, the staff member may interact with the baseboard management controller (BaseboardManager Controller, BMC) through the preset test software, send down the interaction information to filter out a serial in-place detection address from the preset serial in-place detection address set as the current target address to be tested, and control the connection relationship between the memory slot and a plurality of pull-down resistors through a preset switching chip, so as to realize the switching of the SPD address of the memory slot. Accordingly, the staff can pre-set the test code for testing the memory stick in the baseboard management controller, and then filter out the current target address to be tested from the preset serial in-situ detection address set based on the test code, so as to control the connection relationship between the memory slot and several pull-down resistors through the preset switching chip.

[0060] It can be seen that the present application is to connect the memory slot with the pull-down resistor representing the serial in-place detection address through a preset switching chip in the memory test motherboard, and the pull-down resistor connected to a single memory slot can be switched through the preset switching chip, and the serial in-place detection address of a single memory slot can be switched; on a single memory slot, the memory stick to be tested can be tested by switching the serial in-place detection address, ensuring that the memory stick's compatibility test with different serial in-place detection addresses is completed without plugging and unplugging the memory stick, which can improve the test efficiency of the memory stick and reduce the impact of plugging and unplugging on the life of the memory stick. In addition, the central processing unit and the memory slot can be connected separately through a one-to-many preset communication switch line, which can avoid the address conflict problem caused by different memory slots being connected to the pull-down resistors of the same resistance value, and realize the independent control of each memory slot.

[0061] The following embodiments will introduce the technical solutions of the present application in detail by comparing with the currently commonly used technical solutions, specifically including:

[0062] Among the commonly used technical solutions, taking the test platform (motherboard) that supports DDR5 (memory specification) memory sticks as an example, the memory stick SPD mainly confirms its specific address through the pull-down resistor value of the address pin of the memory stick. The motherboard hardware design directly uses the corresponding pull-down resistor to hard-code the SPD address of each memory slot, as shown in Table 1 below:

[0063] Table 1

[0064]

[0065] Further, such as Figure 2 As shown, during the memory stick test, the SPD address of each memory slot is hard-coded on the motherboard (i.e., the memory stick test board), and the same memory stick is inserted into different memory slots through multiple memory stick insertion and removal operations to verify the compatibility of the memory stick with each SPD address.

[0066] In this application, if Figure 3 As shown, a Switch chip (the switch chip of the above embodiment) is added to the Address pin of the memory slot on the motherboard. The Switch chip switches the Address pin of the memory slot to connect to a pull-down resistor with different resistance values, thereby realizing the switching of the SPD address of each memory slot. The Address Switch chip can switch the A pin to any pin of B0-B7 by controlling its SEL pin, wherein the B0-B7 pins are grounded through pull-down resistors with different resistance values, and the resistance values ​​can refer to Table 1 above. In addition, the Address pin of the memory slot is connected to the A pin of the Address Switch chip, so that the Address pin of the memory slot can be connected to a pull-down resistor with different resistance values ​​connected to any pin of B0-B7. Further, the SEL pin of the Address Switch chip is controlled by the BMC chip on the motherboard. The SEL of each Switch chip includes 3 pins. The specific control logic is shown in Table 2 below. In actual testing, the BMC chip controls the SEL pin to switch the SPD address by interacting with the test software. In addition, the BMC can also be controlled to switch the pins through a pre-set script.

[0067] Table 2

[0068]

[0069] In addition, since multiple memory slots are mounted in the same I3C (Improved Inter Integrated Circuit, a serial communication interface) link of the CPU, in order to prevent the I3C address conflict caused by multiple Address Switch chips switching the memory slots to the same SPD address, causing communication abnormality in the entire link, an I3C Switch line (the communication switch line of the above embodiment) can be added to the I3C line between the CPU and the memory slots, thereby ensuring that the SPD address of each memory slot can be independently and arbitrarily controlled to avoid address conflicts.

[0070] It can be seen that the current motherboard hard-codes the serial in-place detection address of the memory slot. In this way, when testing the memory stick, the memory stick needs to be plugged and unplugged multiple times and tested on different memory slots to achieve compatibility testing of different serial in-place detection addresses. However, the present application connects the memory slot to the pull-down resistor representing the serial in-place detection address through a preset switching chip in the memory test motherboard, and switches the pull-down resistor connected to a single memory slot through a preset switching chip, so as to switch the serial in-place detection address of a single memory slot; on a single memory slot, the memory stick to be tested can be tested by switching the serial in-place detection address, ensuring that the memory stick's compatibility test with different serial in-place detection addresses is completed without plugging and unplugging the memory stick; compared with the method of hard-coding the serial in-place detection address of the memory slot, the present application can significantly improve the test efficiency of the memory stick and reduce the impact of plugging and unplugging on the life of the memory stick.

[0071] like Figure 4 As shown, the embodiment of the present application discloses a memory stick test device, which is applied to a server, wherein a memory slot of a memory test motherboard in the server is connected to any one of a plurality of pull-down resistors through a corresponding preset switching chip, and different pull-down resistors correspond to different resistance values. The device comprises:

[0072] The address determination module 11 is used to select a serial presence detection address from a preset serial presence detection address set as a current target address to be tested when testing the memory stick to be tested on the memory slot, and control the memory slot to be connected to a current target pull-down resistor corresponding to the current target address to be tested among the plurality of pull-down resistors through the preset switching chip;

[0073] A compatibility test module 12 is used to test the compatibility between the memory stick to be tested and the current target address to be tested when the memory slot is connected to the current target pull-down resistor, so as to obtain a corresponding current compatibility test result, and determine whether the current compatibility test result indicates that the test has passed;

[0074] The first determination module 13 is used to directly determine that the memory module to be tested on the current memory slot has a functional abnormality when the current compatibility test result indicates that the test fails;

[0075] The second determination module 14 is used for selecting the next serial in-place detection address from the preset serial in-place detection address set as the current target address to be tested when the current compatibility test result indicates that the test has passed, and jumping to the step of controlling the memory slot to be connected to the current target pull-down resistor corresponding to the current target address to be tested among the plurality of pull-down resistors through the preset switching chip, until the compatibility between the memory stick to be tested and each of the serial in-place detection addresses has been tested and passed, and it is determined that the memory stick to be tested on the current memory slot is functioning normally.

[0076] It can be seen that the present application controls the serial presence detection address of the memory slot on the memory test motherboard through a preset switching chip, and can switch different serial presence detection addresses on a memory slot by connecting different pull-down resistors, thereby enabling a complete compatibility test of the memory stick on a single memory slot, avoiding multiple plugging and unplugging of the memory stick during the memory test process, improving the test efficiency of the memory stick, and reducing the impact of the memory test process on the life of the memory stick.

[0077] In a specific embodiment, the device may further include:

[0078] A test channel determination module is used to determine the number of integrated memory controllers supported by the central processing unit on the memory test motherboard and the association relationship between the integrated memory controllers, and divide the integrated memory controllers based on the association relationship and the number of controllers to obtain a plurality of groups of test channels containing the same number of integrated memory controllers; wherein each of the integrated memory controllers corresponds to two memory channels, and each of the memory channels corresponds to two memory slots;

[0079] The address set construction module is used to use a number of serial presence detection addresses for testing memory sticks corresponding to each memory slot in a single group of the test channels to construct a preset serial presence detection address set corresponding to each memory slot in the test channel, so as to filter out a serial presence detection address from the preset serial presence detection address set as the current target address to be tested.

[0080] In a specific embodiment, the device may further include:

[0081] A communication switch circuit connection module, used to connect the central processing unit and several groups of the test channels respectively through several preset communication switch circuits on the memory test mainboard; wherein one end of the preset communication switch circuit is connected to the central processing unit, and the other end is connected to any one of the several memory slots corresponding to a single group of the test channels;

[0082] A sorting module, used to sort the test channels of the groups according to the memory test tasks corresponding to the memory bars to be tested on the memory slots in the test channels of each group, to obtain a first sequence representing the order of the test channels in the memory test process, and to sort the memory test tasks corresponding to the memory bars to be tested on the memory slots in a single group of the test channels, to obtain a second sequence representing the order of the memory test tasks in the single group of the test channels in the memory test process;

[0083] A line switching module is used to determine the current test channel and the current memory slot where the memory test task to be executed is located based on the first sequence and the second sequence respectively when performing memory testing on the memory test mainboard, and connect the central processing unit and the current memory slot of the current test channel through the preset communication switch line to test the memory bar to be tested on the current memory slot.

[0084] In a specific embodiment, the line switching module may include:

[0085] A memory test task determination unit, configured to, when the memory bar to be tested on the current memory slot is determined to be malfunctioning or functioning normally, determine the next memory test task as the current memory test task to be executed based on the second sequence, and jump to the step of connecting the central processing unit and the current memory slot of the current test channel through the preset communication switch line;

[0086] A test channel determination unit is used to, when the memory bars to be tested in the current test channel have all been determined to be functionally abnormal or functionally normal, use the next test channel as the current test channel based on the first sequence, determine the current memory test task to be executed and the corresponding current memory slot based on the second sequence, and jump to the step of connecting the central processing unit and the current memory slot of the current test channel through the preset communication switch line, so as to test the memory bars to be tested on the current memory slot.

[0087] In a specific embodiment, the compatibility testing module 12 may include:

[0088] A testing unit is used to perform corresponding functional testing operations on the memory stick to be tested based on preset memory testing rules and through a central processing unit on the memory testing mainboard when the memory slot is connected to the current target pull-down resistor, so as to generate a current compatibility test result representing the compatibility between the memory stick to be tested and the current target address to be tested according to the test information corresponding to the functional testing operation.

[0089] In a specific embodiment, the device may further include:

[0090] The alarm trigger module is used to trigger an alarm message indicating that the memory stick to be tested has a functional abnormality, so that relevant staff can replace the memory stick to be tested on the memory slot based on the alarm message, and then test the replaced memory stick on the memory slot.

[0091] In a specific embodiment, the address determination module 11 may include:

[0092] The first address determination unit is used to obtain the interaction information between the staff and the preset test software through the baseboard management controller, and select a serial presence detection address matching the interaction information from the preset serial presence detection address set as the current target address to be tested;

[0093] The second address determination unit is used to select a serial presence detection address from a preset serial presence detection address set as a current target address to be tested based on a test code preset in the baseboard management controller.

[0094] Furthermore, an embodiment of the present application also discloses a computer program product, including a computer program / instruction, which implements the steps of the memory stick testing method when executed by a processor.

[0095] Furthermore, the present application also discloses an electronic device. Figure 5 This is a structural diagram of an electronic device according to an exemplary embodiment, and the content in the diagram cannot be regarded as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the memory bar testing method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0096] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0097] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0098] The operating system 221 is used to manage and control various hardware devices on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the memory bar testing method performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0099] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed memory bar testing method. The specific steps of the method can refer to the corresponding contents disclosed in the aforementioned embodiments, and will not be repeated here.

[0100] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0101] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0102] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0103] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0104] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A memory bar testing method, characterized in that: Applied to a server, a memory slot of a memory test mainboard in the server is connected to any one of a plurality of pull-down resistors through a corresponding preset switching chip, and different pull-down resistors correspond to different resistance values; the method comprises: When testing the memory stick to be tested on the memory slot, a serial presence detection address is selected from the preset serial presence detection address set as the current target address to be tested, and the memory slot is controlled by the preset switching chip to be connected to the current target pull-down resistor corresponding to the current target address to be tested among the plurality of pull-down resistors; When the memory slot is connected to the current target pull-down resistor, the compatibility between the memory stick to be tested and the current target address to be tested is tested to obtain a corresponding current compatibility test result, and it is determined whether the current compatibility test result indicates that the test is passed; If the current compatibility test result indicates that the test fails, it is directly determined that the memory module to be tested on the current memory slot has a functional abnormality; If the current compatibility test result indicates that the test has passed, the next serial in-place detection address is selected from the preset serial in-place detection address set as the current target address to be tested, and the process jumps to the step of controlling the memory slot to be connected to the current target pull-down resistor among the several pull-down resistors corresponding to the current target address to be tested through the preset switching chip, until the compatibility between the memory stick to be tested and each of the serial in-place detection addresses has been tested and passed, and it is determined that the memory stick to be tested on the current memory slot is functioning normally.

2. The memory bar testing method according to claim 1, characterized in that: Before selecting a serial presence detection address from the preset serial presence detection address set as the current target address to be tested, the method further includes: Determine the number of integrated memory controllers supported by the central processing unit on the memory test motherboard and the association relationship between the integrated memory controllers, and divide the integrated memory controllers based on the association relationship and the number of controllers to obtain a plurality of groups of test channels including the same number of integrated memory controllers; wherein each of the integrated memory controllers corresponds to two memory channels, and each of the memory channels corresponds to two memory slots; A preset serial presence detection address set corresponding to each memory slot in the test channel is constructed using a plurality of serial presence detection addresses for testing memory sticks corresponding to each memory slot in the test channel, so as to select a serial presence detection address from the preset serial presence detection address set as the current target address to be tested.

3. The memory bar testing method according to claim 2, characterized in that: Before testing the memory bar to be tested on the memory slot, the method further includes: The central processing unit and the plurality of test channels are respectively connected through a plurality of preset communication switch circuits on the memory test mainboard; wherein one end of the preset communication switch circuit is connected to the central processing unit, and the other end is connected to any one of the plurality of memory slots corresponding to a single group of test channels; Sorting the test channels in the groups according to the memory test tasks corresponding to the memory bars to be tested on the memory slots in the test channels in each group to obtain a first sequence representing the order of the test channels in the memory test process, and sorting the memory test tasks corresponding to the memory bars to be tested on the memory slots in a single group of the test channels to obtain a second sequence representing the order of the memory test tasks in the single group of the test channels in the memory test process; When performing memory testing on the memory testing mainboard, the current test channel and the current memory slot where the memory test task to be executed is located are determined based on the first sequence and the second sequence respectively, and the central processing unit and the current memory slot of the current test channel are connected through the preset communication switch line to test the memory stick to be tested on the current memory slot.

4. The memory bar testing method according to claim 3, characterized in that: The testing of the memory bar to be tested on the current memory slot includes: If the memory bar to be tested on the current memory slot is determined to be malfunctioning or functioning normally, then based on the second sequence, the next memory test task is used as the current memory test task to be executed, and the process jumps to the step of connecting the central processing unit and the current memory slot of the current test channel through the preset communication switch line; If the memory sticks to be tested in the current test channel have all been determined to be functionally abnormal or functionally normal, the next test channel is used as the current test channel based on the first sequence, and the memory test task to be executed and the corresponding current memory slot are determined based on the second sequence, and the process jumps to the step of connecting the central processing unit and the current memory slot of the current test channel through the preset communication switch line, so as to test the memory stick to be tested on the current memory slot.

5. The memory bar testing method according to claim 1, characterized in that: When the memory slot is connected to the current target pull-down resistor, the compatibility between the memory stick to be tested and the current target address to be tested is tested to obtain a corresponding current compatibility test result, including: When the memory slot is connected to the current target pull-down resistor, based on preset memory test rules, corresponding functional test operations are performed on the memory stick to be tested through the central processing unit on the memory test mainboard, so as to generate a current compatibility test result characterizing the compatibility between the memory stick to be tested and the current target address to be tested according to the test information corresponding to the functional test operation.

6. The memory bar testing method according to claim 1, characterized in that: After directly determining that the memory module to be tested on the current memory slot has a functional abnormality, the method further includes: Trigger an alarm message indicating that the memory stick to be tested has a functional abnormality, so that relevant staff can replace the memory stick to be tested on the memory slot based on the alarm message, and then test the replaced memory stick on the memory slot.

7. The memory stick testing method according to any one of claims 1 to 6, characterized in that: The step of selecting a serial presence detection address from a preset serial presence detection address set as the current target address to be tested includes: Acquire the interaction information between the staff and the preset test software through the baseboard management controller, and select a serial presence detection address matching the interaction information from the preset serial presence detection address set as the current target address to be tested; Or, based on the test code preset in the baseboard management controller, a serial presence detection address is selected from the preset serial presence detection address set as the current target address to be tested.

8. A memory bar testing device, characterized in that: Applied to a server, a memory slot of a memory test motherboard in the server is connected to any one of a plurality of pull-down resistors through a corresponding preset switching chip, and different pull-down resistors correspond to different resistance values. The device comprises: An address determination module is used to select a serial presence detection address from a preset serial presence detection address set as a current target address to be tested when testing the memory bar to be tested on the memory slot, and control the memory slot to be connected to a current target pull-down resistor corresponding to the current target address to be tested among the plurality of pull-down resistors through the preset switching chip; A compatibility test module, configured to test the compatibility between the memory stick to be tested and the current target address to be tested when the memory slot is connected to the current target pull-down resistor, so as to obtain a corresponding current compatibility test result, and determine whether the current compatibility test result indicates that the test has passed; A first determination module, configured to directly determine that the memory module to be tested on the current memory slot has a functional abnormality when the current compatibility test result indicates that the test fails; The second determination module is used for selecting the next serial in-place detection address from the preset serial in-place detection address set as the current target address to be tested when the current compatibility test result characterizes that the test has passed, and jumping to the step of controlling the memory slot to be connected to the current target pull-down resistor corresponding to the current target address to be tested among the several pull-down resistors through the preset switching chip, until the compatibility between the memory stick to be tested and each of the serial in-place detection addresses has been tested and passed, and it is determined that the memory stick to be tested on the current memory slot is functioning normally.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the memory stick testing method as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the memory stick testing method according to any one of claims 1 to 7 are implemented.

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