Data access method and device based on last-stage cache

Abstract

The embodiment of the invention provides a data access method and device based on a last-stage cache, the method is applied to a distributed memory system, the distributed memory system comprises a plurality of cores, a memory subsystem of the distributed memory system is provided with a three-stage cache structure, and the three-stage cache structure comprises a first-stage cache, a second-stage cache and the last-stage cache. A label matrix corresponding to the last-stage cache at least comprises an exclusive core flag bit corresponding to a cache line and other core flag bits, and the method comprises the following steps: responding to a data access request of a target core; determining a target cache line corresponding to the data access request from the distributed memory system based on a target data access rule corresponding to the core type of the target core; and sending a response message to the target core according to the core occupation state corresponding to the target cache line. According to the data access method and device, the problem that when a distributed memory system is used for processing data access requests of different cores, data cannot be accurately accessed is solved, and then the effect of improving the data access accuracy is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and in particular, to a data access method and device based on a last-level cache. Background Art

[0002] In modern computing environments, distributed memory systems are often used to process massive amounts of data and provide users with high-availability services. As the amount of data grows and service requirements change, the scale and complexity of distributed memory systems are also increasing. In order to improve the performance and response speed of distributed memory systems, cache technology has been introduced. The cache itself is a high-speed storage mechanism that can temporarily store frequently accessed data, reduce the load on the back-end storage system, and improve the system's throughput and response time, thereby reducing the access latency of the back-end storage system. However, when multiple cores access data in a distributed memory system at the same time, incorrect data may be returned to the core due to inconsistencies between the data in the cache and the data in the memory, thus affecting the reliability and accuracy of the system.

[0003] Therefore, in the related art, there is no effective solution to the technical problem that data cannot be accurately accessed when a distributed memory system is used to process data access requests from different cores. Summary of the invention

[0004] The embodiments of the present application provide a data access method and device based on a last-level cache, so as to at least solve the technical problem in the related art that data cannot be accurately accessed when a distributed memory system is used to process data access requests from different cores.

[0005] According to one embodiment of the present application, a data access method based on a last-level cache is provided, which is applied to a distributed memory system, wherein the distributed memory system includes multiple cores, and the memory subsystem of the distributed memory system has a three-level cache structure, wherein the three-level cache structure includes a first-level cache, a second-level cache and a last-level cache, and the tag matrix corresponding to the last-level cache includes at least an exclusive core flag bit and other core flag bits corresponding to a cache line, including: responding to a data access request of a target core, wherein the target core is one of the multiple cores; determining a target cache line corresponding to the data access request from the distributed memory system based on a target data access rule corresponding to a core type of the target core; and sending a response message to the target core according to a core occupancy status corresponding to the target cache line.

[0006] In an exemplary embodiment, the memory subsystem is also provided with a victim cache for the last-level cache, and a target cache line corresponding to the data access request is determined from the distributed memory system based on a target data access rule corresponding to a core type of the target core, including: when it is determined that the core type of the target core is a local core, if it is determined that the data access request is used to access first data corresponding to a local memory address, then based on the target data access rule, the first data is queried from the first-level cache and the second-level cache in sequence; if the first data is found in the first-level cache or the second-level cache, then the cache line corresponding to the first data is determined as the target cache line.

[0007] In an exemplary embodiment, the method further includes: when it is determined that the first data is not found in both the first-level cache and the second-level cache, querying the first data in parallel from the last-level cache and the victim cache based on the target data access rule; or, when it is determined that the exclusive core flag bit of the target cache line is used to indicate that the core occupancy state of the target cache line is not locally exclusive, querying the first data in parallel from the last-level cache and the victim cache based on the target data access rule.

[0008] In an exemplary embodiment, the method further includes: if the first data is found in the last-level cache, determining the cache line corresponding to the first data as the target cache line; determining the exclusive core flag corresponding to the target cache line from the tag matrix where the target cache line is located; when it is determined that the exclusive core flag of the target cache line is used to indicate that the core occupancy state of the target cache line is not locally exclusive, determining the other core flag corresponding to the target cache line from the tag matrix; if it is determined that the other core flag is used to indicate that the core occupancy state of the target cache line is occupied by other cores, sending a first snoop message to the other cores. receiving a reply message sent by the other cores based on the first monitoring message, modifying the flag bits of the other cores in the tag matrix according to the reply message to update the tag matrix, and obtaining an updated tag matrix; sending a response message to the target core when it is determined that the exclusive core flag bit of the target cache line is used to indicate that the core occupancy state of the target cache line is locally exclusive; searching for the first data from the memory space if the first data is not found in the last-level cache; synchronizing the first data to a newly added cache line of the last-level cache when it is determined that the remaining storage space of the last-level cache is greater than the storage space required for the first data.

[0009] In an exemplary embodiment, the method further includes: determining a shared cache line from all cache lines when it is determined that all cache lines of the last-level cache are occupied; replacing the shared cache line to the victim cache, determining a blank cache line where the shared cache line was located before the replacement, and synchronizing the first data to the blank cache line.

[0010] In an exemplary embodiment, a target cache line corresponding to the data access request is determined from the distributed memory system based on a target data access rule corresponding to the core type of the target core, including: when it is determined that the core type of the target core is other cores, if it is determined that the data access request is used to access second data corresponding to a local core address, querying the second data from the last-level cache based on the target data access rule; if the second data is found in the last-level cache, determining the cache line corresponding to the second data as the target cache line.

[0011] In an exemplary embodiment, after querying the second data from the last-level cache based on the target data access rule, the method further includes: if the second data is not found in the last-level cache, searching for the second data from the victim cache; if the second data is not found from the victim cache, searching for the second data from the memory space; if the second data is found from the victim cache, determining the victim cache line corresponding to the second data as the target cache line, and sending a second snoop message to the local core; in response to a reply message sent by the target core based on the second snoop message, replacing the target cache line with the cache line of the last-level cache.

[0012] According to another embodiment of the present application, a data access device based on a last-level cache is provided, including: a response module, used to respond to a data access request of a target core, wherein the target core is one of the multiple cores; a determination module, used to determine the target cache line corresponding to the data access request from the distributed memory system based on a target data access rule corresponding to the core type of the target core; and a sending module, used to send a response message to the target core according to the core occupancy status corresponding to the target cache line.

[0013] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0014] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0015] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0016] Through this application, for a distributed memory system with a three-level cache structure (including a first-level cache, a second-level cache and a final-level cache), the final-level cache is optimized. In addition to recording the effective value, label, etc. describing the cache line attribute in the metadata of the final-level cache, the core occupancy status used to indicate the situation where the cache line is occupied by the core is added to the metadata. By additionally assuming the function of the directory in the label matrix, the resources occupied by the directory can be saved, thereby saving memory space. Then, facing the target core that initiates the access, in response to the data access request of the target core, the target cache line corresponding to the data access request is determined from the distributed memory system based on the target data access rule corresponding to the core type of the target core, and a response message is sent to the target core according to the core occupancy status corresponding to the target cache line. Therefore, the technical problem that the data cannot be accurately accessed when using a distributed memory system to process data access requests of different cores can be solved, so as to achieve the effect of improving the accuracy and access efficiency of data access. Moreover, for the situation where multiple cores initiate requests, the cache consistency of the distributed system can be maintained by optimizing the design of the final-level cache on the basis of saving the extra space occupied by the directory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a hardware structure block diagram of a server device of a data access method based on a last-level cache according to an embodiment of the present application;

[0018] Figure 2 is a flow chart of a data access method based on last-level cache according to an embodiment of the present application;

[0019] Figure 3 is a structural block diagram of a distributed memory system according to an embodiment of the present application;

[0020] Figure 4 is a schematic diagram of a cache line structure according to an embodiment of the present application;

[0021] Figure 5 is a flow chart of data access based on last-level cache according to an embodiment of the present application;

[0022] Figure 6It is a structural diagram of a data access device based on last-level cache according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0025] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 1 is a hardware structure block diagram of a server device of a data access method based on a last-level cache in an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the figure) processor 102 (processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0026] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the data access method based on the last-level cache in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the data access method based on the last-level cache is realized. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0027] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0028] In this embodiment, a data access method based on a last-level cache is provided, which is applied to a distributed memory system, wherein the distributed memory system includes multiple cores, and a memory subsystem of the distributed memory system has a three-level cache structure, wherein the three-level cache structure includes a first-level cache, a second-level cache, and a last-level cache, and a tag matrix corresponding to the last-level cache includes at least an exclusive core flag bit and other core flag bits corresponding to a cache line. Figure 2 is a flow chart of a data access method based on last-level cache according to an embodiment of the present application. Figure 2 As shown, the process includes the following steps:

[0029] Step S202, responding to a data access request of a target core, wherein the target core is one of the multiple cores;

[0030] Step S204, determining a target cache line corresponding to the data access request from the distributed memory system based on a target data access rule corresponding to the core type of the target core;

[0031] Step S206: Send a response message to the target core according to the core occupancy status corresponding to the target cache line.

[0032] It should be noted that the above core occupancy status may indicate whether the target cache line is exclusively occupied by the local core, and may also indicate the usage of the target cache line by each core.

[0033] It can be understood that the above response message may include the data stored in the target cache line corresponding to the data access request.

[0034] It is understandable that, in the case where multiple cores simultaneously issue data access requests, the above steps can be used to process each core individually, and finally a corresponding response message is sent.

[0035] Through the above steps, for a distributed memory system with a three-level cache structure (including a first-level cache, a second-level cache and a final-level cache), the final-level cache is optimized. In addition to recording the effective value, label, etc. describing the cache line attribute in the metadata of the final-level cache, the core occupancy status used to indicate the situation where the cache line is occupied by the core is added to the metadata. By additionally assuming the function of the directory in the label matrix, the resources occupied by the directory can be saved, thereby saving memory space. Then, facing the target core that initiates the access, in response to the data access request of the target core, the target cache line corresponding to the data access request is determined from the distributed memory system based on the target data access rule corresponding to the core type of the target core, and a response message is sent to the target core according to the core occupancy status corresponding to the target cache line. Therefore, the technical problem that the data cannot be accurately accessed when using a distributed memory system to process data access requests of different cores can be solved, and the accuracy and access efficiency of data access can be improved. In addition, for the situation where multiple cores initiate requests, the cache consistency of the distributed system can be maintained by optimizing the design of the final-level cache on the basis of saving the extra space occupied by the directory.

[0036] The execution subject of the above steps may be a server, a terminal, etc., but is not limited thereto.

[0037] like Figure 3 As shown, the distributed memory system has N cores (i.e. Figure 3 The kernel in the system maintains cache consistency based on the CHI protocol. The states of each node are I, SC, SD, and U, and 2 bits are needed to describe the four states. The I state is Invalid, which means that the data in the cache line is invalid. The SC state is SharedClean, which means that the data in the cache line is the same as the memory, and there is a cache copy in the system. The SD state is SharedDirty, which means that the data in the cache line is different from the memory, and there is a cache copy in the system. The U state is Unique, which means that the data in the cache line is exclusively used by a core. Among them, 1Byte=8bit.

[0038] Among them, the CHI protocol (Consistent Hashing with lnhomogeneous Replication) is a data distribution and replication strategy in a distributed memory system. In a distributed memory system, data is distributed across multiple nodes to achieve load balancing, high availability, and fault tolerance.

[0039] The last level cache is part of the memory subsystem and is a shared cache that can be accessed by every core in the distributed memory system. The last level cache consists of metadata and data. The metadata is used to describe the actual data content attributes. Figure 4 As shown in the figure, in the cache metadata, an additional 2N+1 bits are needed to describe whether the cache line is exclusively occupied by the local core and the usage of other cores. Log2N bits are used to distinguish which core the address belongs to, and the data size of each cache line is 64Bytes.

[0040] The memory subsystem of the distributed memory system adopts Figure 3 In the three-level cache structure shown in the figure, L1 cache (i.e., first-level cache) and L2 cache (i.e., second-level cache) are private caches, and L3 cache is the last-level cache. The memory addresses of the distributed memory system are uniformly allocated and encoded, and the high bits are used to distinguish which core the address belongs to. When each core issues a request for a certain address, the router routes it to different cores based on the high-bit encoding of the address. The last-level core controller decides which core to send the snoop request to based on the possession of the cache line data by each core recorded by the last-level core, and sends a response to the requesting core after waiting for the snoop response to be collected.

[0041] In the traditional cache line structure, the rows of the tag matrix and the data matrix are one-to-one corresponding. In this application, Figure 4 As shown, the metadata not only records the Tag, Valid, and dirty bits that describe the cache line attributes, but also adds whether the cache line is exclusively occupied by the local core and the usage of the cache line by each core. The Tag matrix (i.e., the above-mentioned tag matrix) additionally assumes the function of a directory. This application saves memory space by optimizing the structure of the metadata.

[0042] In addition, a victim cache is additionally provided in the memory subsystem. When the last-level cache is full and a new request is received, the original cache line can be replaced. Generally speaking, each core accesses its own core memory more frequently than other cores, that is, more than half of the cache lines are generally exclusively occupied by the local core. Only in rare cases are half of the cache lines shared. Therefore, the cache line replacement strategy adopted is: 1. Replace the shared cache lines first, 2. When the occupancy rate of the shared cache lines is less than 30%, replace the cache lines exclusively occupied by the local core. Since CPU memory access has temporal locality and spatial locality, in order to reduce the increase in memory access time caused by cache misses, the cache lines exclusively occupied by the local core to be replaced are replaced with the victim cache.

[0043] In one embodiment, when the local core accesses the local memory address, the victim cache and the last-level cache are queried at the same time. Specifically, when the local core accesses the data of the local memory address, if the L1 cache or L2 cache hits, and the occupancy status of the cache line indicates that the cache line is occupied by the local core, then the cache hits, and the data is directly returned to the CPU. If the L1 cache or L2 cache hits, but the cache line permission occupancy status indicates that the cache line is not occupied by the local core, or it does not hit, then the request is sent to the victim cache and L3 cache for parallel search. If the L3 cache hits, check whether the state of the cache line is exclusive. If it is exclusive, directly reply with a response. If it is non-exclusive, according to the state desired by the requesting core and the state of other cores recorded in the cache metadata, send a listening message to the corresponding core, change the occupancy state of other cores for this cache line, wait for other cores to return the listening response, change the state of each core in the metadata of the cache line, and send a response to the local core. If the L3 cache misses, the data is taken out from the memory to the L3 cache. If the L3 cache is not full, a new cache line is directly opened. If the cache line is full, it is replaced according to the replacement rules described above and a response is given to the local core.

[0044] In one embodiment, when other cores access their own memory addresses, they first access the last-level cache, and then decide whether to query the victim cache based on whether it hits. Specifically, when other cores access the address of the local core, they first query whether the address of the local core hits in the L3 cache. If the L3 cache hits, the states of each core recorded in the metadata are queried, a snoop request is sent to each core, and each core is waited for to reply with a snoop response, the states of each core recorded in the metadata are changed, and the core that sent the request replies with a response. If the L3 cache does not hit, the victim cache is searched. If the victim cache does not hit, data is fetched from the memory to the L3 cache. If it hits in the victim cache, a snoop is directly sent to the local core, and after the snoop response is returned, the victim cache line is replaced with the L3 cache. In this case, if both the victim cache and the L3 cache are full, a victim cache line needs to be cleared first, and after the L3 cache line is replaced with the victim cache line, the victim cache line that has been changed from exclusive to shared is moved into the L3 cache. This replacement method can avoid deadlock.

[0045] Through the above embodiments, the cache consistency of the system can be maintained by using the last-level cache and the victim cache in the distributed memory system.

[0046] In an exemplary embodiment, the memory subsystem is also provided with a victim cache for the last-level cache, and an implementation scheme for determining the target cache line corresponding to the data access request from the distributed memory system based on the target data access rule corresponding to the core type of the target core specifically includes: when it is determined that the core type of the target core is a local core, if it is determined that the data access request is used to access the first data corresponding to the local memory address, then querying the first data from the first-level cache and the second-level cache in sequence based on the target data access rule; if the first data is found in the first-level cache or the second-level cache, then determining the cache line corresponding to the first data as the target cache line.

[0047] Exemplarily, the first data is, for example, Figure 4 The data in the matrix is ​​data1, data2 etc.

[0048] This embodiment can determine the target cache line for the local core that initiates the data access request. That is, when the local core accesses the data of the local memory address, the corresponding target data access rule is to first access the first-level cache and the second-level cache. If the first data cannot be found in the first-level cache and the second-level cache, the first data is searched from the last-level cache and the victim cache at the same time, thereby improving data access efficiency.

[0049] In an exemplary embodiment, further, when it is determined that the first data is not found in both the first-level cache and the second-level cache, the first data is queried in parallel from the last-level cache and the victim cache based on the target data access rule; or, when it is determined that the exclusive core flag of the target cache line is used to indicate that the core occupancy state of the target cache line is not locally exclusive, the first data is queried in parallel from the last-level cache and the victim cache based on the target data access rule.

[0050] In an exemplary embodiment, if the first data is found in the last-level cache, the cache line corresponding to the first data is determined as the target cache line; the exclusive core flag corresponding to the target cache line is determined from the tag matrix where the target cache line is located; when it is determined that the exclusive core flag of the target cache line is used to indicate that the core occupancy state of the target cache line is not locally exclusive, the other core flags corresponding to the target cache line are determined from the tag matrix; if it is determined that the other core flag is used to indicate that the core occupancy state of the target cache line is occupied by other cores, a first monitoring message is sent to the other cores; receiving The other cores send a reply message based on the first listening message, and modify the other core flags in the tag matrix according to the reply message to update the tag matrix to obtain an updated tag matrix; when it is determined that the exclusive core flag of the target cache line is used to indicate that the core occupancy state of the target cache line is locally exclusive, a response message is sent to the target core; if the first data is not found in the last-level cache, the first data is searched from the memory space; when it is determined that the remaining storage space of the last-level cache is greater than the storage space required for the first data, the first data is synchronized to the newly added cache line of the last-level cache. Through this embodiment, a response message can be sent to the target core according to the exclusive core flag corresponding to the target cache line, thereby improving data access accuracy.

[0051] Optionally, modifying the other core flag bits in the label matrix according to the reply message to update the label matrix may mean modifying the other core flag bits from being occupied to being unoccupied.

[0052] Optionally, after modifying the other core flag bits in the label matrix according to the reply message to update the label matrix and obtaining the updated label matrix, if a new data access request is received and the above conditions are met, the other core flag bits can be queried from the updated label matrix, and it is determined whether to send a monitoring message based on the other core flag bits.

[0053] In an exemplary embodiment, further, when it is determined that all cache lines of the last-level cache are occupied, a shared cache line is determined from all the cache lines; the shared cache line is replaced to the victim cache, a blank cache line where the shared cache line was located before the replacement is determined, and the first data is synchronized to the blank cache line.

[0054] In an exemplary embodiment, the implementation process of determining the target cache line corresponding to the data access request from the distributed memory system based on the target data access rule corresponding to the core type of the target core may also include other steps, as follows: in the case where the core type of the target core is determined to be other cores, if it is determined that the data access request is used to access the second data corresponding to the local core address, query the second data from the last-level cache based on the target data access rule; if the second data is found in the last-level cache, determine the cache line corresponding to the second data as the target cache line. This embodiment can determine the target cache line for other cores that initiate data access requests, that is, when other cores access data at a memory address, the corresponding target data access rule is to directly access the last-level cache and search for the second data from the last-level cache, thereby improving data access efficiency.

[0055] Exemplarily, the second data can be understood as Figure 4 The data in the data matrix is ​​1, etc.

[0056] Optionally, when it is determined that the core type of the target core is other cores, if it is determined that the data access request is used to access the second data corresponding to the memory address, the above embodiment can be referred to to query the second data from the last-level cache based on the target data access rule, and this application does not impose any restrictions on this.

[0057] In an exemplary embodiment, after querying the second data from the last-level cache based on the target data access rule, if the second data is not found in the last-level cache, the second data is searched from the victim cache; if the second data is not found from the victim cache, the second data is searched from the memory space; if the second data is found from the victim cache, the victim cache line corresponding to the second data is determined as the target cache line, and a second snoop message is sent to the local core; in response to a reply message sent by the target core based on the second snoop message, the target cache line is replaced with the cache line of the last-level cache.

[0058] Optionally, the process of replacing the target cache line with the cache line of the last-level cache may include: if it is determined that all cache lines of the victim cache and all cache lines of the last-level cache are occupied, first clearing a victim cache line, and after one of the cache lines of the last-level cache is replaced with the victim cache line, moving the victim cache line (i.e., the target cache line) that has been changed from exclusive to shared into the cache line of the last-level cache.

[0059] Further, combined with Figure 5The process of determining the target cache line corresponding to the data access request from the distributed memory system based on the target data access rule corresponding to the core type of the target core is described, and the specific steps include:

[0060] Step S501: any core issues an access request.

[0061] Step S502, obtaining a target core according to the address routing of the access request.

[0062] Step S503, check whether the cache is hit. If yes, execute step S504, if not, execute step S505.

[0063] Step S504, determine whether the core status meets the requirements. If yes, execute step S506, if not, execute step S507.

[0064] Step S505, fetching data from the memory to the cache.

[0065] Step S506, updating the core status in the tag matrix.

[0066] Step S507: Send a monitoring request to each core.

[0067] Step S508: reply a monitoring response to each core.

[0068] Step S509: Send a response to the core corresponding to the request.

[0069] It can be seen that the distributed memory system proposes different memory access processes for the local core and other cores respectively, which can classify access and improve the access speed of each core to the local memory address, thereby improving the memory access efficiency of the entire system.

[0070] Furthermore, the cache and directory mentioned in this application are not limited to a certain hardware system, and can be applied to a variety of cache consistency protocols. This method saves the extra space occupied by the directory, optimizes the design of the last-level cache, and uses the last-level cache to maintain the cache consistency of the distributed memory system. It can save the storage space of the system and efficiently achieve the cache consistency of the distributed memory system.

[0071] Optionally, in one embodiment, data access may be implemented in other ways:

[0072] Method 1: In response to the data access request of the target core, the request is sent to all cores included in the distributed memory system in a broadcast manner, and each core returns a response. However, when this method is used in a large-scale distributed memory system, a large number of messages need to be sent, which occupies a large amount of bandwidth. Therefore, the use of broadcast to maintain cache consistency is only suitable for small-scale distributed memory systems.

[0073] Method 2: Use the directory to maintain cache consistency and uniformly record the data occupancy of each core in the directory. In response to the data access request of the target core, first send the request to the directory, and then send the request to the core that occupies the data according to the record in the directory. This method can reduce unnecessary message transmission, but the directory requires additional space for recording, which increases storage overhead.

[0074] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0075] In this embodiment, a data access device based on a last-level cache is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0076] Figure 6 is a structural block diagram of a data access device based on a last-level cache according to an embodiment of the present application, such as Figure 6 As shown, the device comprises:

[0077] a response module 62, configured to respond to a data access request of a target core, wherein the target core is one of the multiple cores;

[0078] A determination module 64, configured to determine a target cache line corresponding to the data access request from the distributed memory system based on a target data access rule corresponding to a core type of the target core;

[0079] The sending module 66 is used to send a response message to the target core according to the core occupancy status corresponding to the target cache line.

[0080] Through the above device, for a distributed memory system with a three-level cache structure (including a first-level cache, a second-level cache and a final-level cache), the final-level cache is optimized. In addition to recording the effective value, label, etc. describing the cache line attribute in the metadata of the final-level cache, the core occupancy status used to indicate the situation where the cache line is occupied by the core is added to the metadata. By additionally assuming the function of the directory in the label matrix, the resources occupied by the directory can be saved, thereby saving memory space. Then, facing the target core that initiates the access, in response to the data access request of the target core, the target cache line corresponding to the data access request is determined from the distributed memory system based on the target data access rule corresponding to the core type of the target core, and a response message is sent to the target core according to the core occupancy status corresponding to the target cache line. Therefore, the technical problem that the data cannot be accurately accessed when using a distributed memory system to process data access requests of different cores can be solved, and the accuracy and access efficiency of data access can be improved. In addition, for the situation where multiple cores initiate requests, the cache consistency of the distributed system can be maintained by optimizing the design of the final-level cache on the basis of saving the extra space occupied by the directory.

[0081] In an exemplary embodiment, the memory subsystem is also provided with a victim cache for the last-level cache, and the determination module 64 is further used for: when it is determined that the core type of the target core is a local core, if it is determined that the data access request is used to access the first data corresponding to the local memory address, then query the first data from the first-level cache and the second-level cache in sequence based on the target data access rule; if the first data is found in the first-level cache or the second-level cache, then determine the cache line corresponding to the first data as the target cache line.

[0082] In an exemplary embodiment, the determination module 64 is further used to: when it is determined that the first data is not found in both the first-level cache and the second-level cache, query the first data in parallel from the last-level cache and the victim cache based on the target data access rule; or, when it is determined that the exclusive core flag bit of the target cache line is used to indicate that the core occupancy state of the target cache line is not locally exclusive, query the first data in parallel from the last-level cache and the victim cache based on the target data access rule.

[0083] In an exemplary embodiment, the determination module 64 is further used to: if the first data is found in the last-level cache, determine the cache line corresponding to the first data as the target cache line; determine the exclusive core flag corresponding to the target cache line from the tag matrix where the target cache line is located; when it is determined that the exclusive core flag of the target cache line is used to indicate that the core occupancy state of the target cache line is not locally exclusive, determine the other core flag corresponding to the target cache line from the tag matrix; if it is determined that the other core flag is used to indicate that the core occupancy state of the target cache line is occupied by other cores, send the first monitor to the other cores. Listen to the message; receive the reply message sent by the other cores based on the first listening message, modify the flag bits of the other cores in the tag matrix according to the reply message to update the tag matrix, and obtain the updated tag matrix; when it is determined that the exclusive core flag bit of the target cache line is used to indicate that the core occupancy state of the target cache line is locally exclusive, send a response message to the target core; if the first data is not found in the last-level cache, search for the first data from the memory space; when it is determined that the remaining storage space of the last-level cache is greater than the storage space required for the first data, synchronize the first data to the newly added cache line of the last-level cache.

[0084] In an exemplary embodiment, the determination module 64 is further used to: determine a shared cache line from all the cache lines when it is determined that all cache lines of the last-level cache are occupied; replace the shared cache line to the victim cache, determine a blank cache line where the shared cache line was located before the replacement, and synchronize the first data to the blank cache line.

[0085] In an exemplary embodiment, the determination module 64 is also used to: when it is determined that the core type of the target core is other cores, if it is determined that the data access request is used to access second data corresponding to the local core address, query the second data from the last-level cache based on the target data access rule; if the second data is found in the last-level cache, determine the cache line corresponding to the second data as the target cache line.

[0086] In an exemplary embodiment, the determination module 64 is further used to: if the second data is not found in the last-level cache, search for the second data from the victim cache; if the second data is not found from the victim cache, search for the second data from the memory space; if the second data is found from the victim cache, determine the victim cache line corresponding to the second data as the target cache line, and send a second snoop message to the local core; in response to a reply message sent by the target core based on the second snoop message, replace the target cache line with the cache line of the last-level cache.

[0087] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0088] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0089] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0090] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0091] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0092] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0093] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0094] The embodiments of the present application also provide a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the steps in any one of the above method embodiments.

[0095] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0096] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0097] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data access method based on last-level cache, characterized in that: Applied to a distributed memory system, the distributed memory system includes multiple cores, the memory subsystem of the distributed memory system has a three-level cache structure, the three-level cache structure includes a first-level cache, a second-level cache and a final-level cache, the tag matrix corresponding to the final-level cache includes at least an exclusive core flag bit and other core flag bits corresponding to a cache line, include: responding to a data access request of a target core, wherein the target core is one of the plurality of cores; Determining a target cache line corresponding to the data access request from the distributed memory system based on a target data access rule corresponding to a core type of the target core; A response message is sent to the target core according to the core occupancy state corresponding to the target cache line.

2. The method according to claim 1, characterized in that The memory subsystem is also provided with a victim cache for the last level cache. Determining a target cache line corresponding to the data access request from the distributed memory system based on a target data access rule corresponding to the core type of the target core includes: In the case where it is determined that the core type of the target core is a local core, if it is determined that the data access request is used to access first data corresponding to a local memory address, querying the first data from the first level cache and the second level cache in sequence based on the target data access rule; If the first data is found in the first-level cache or the second-level cache, the cache line corresponding to the first data is determined as the target cache line.

3. The method according to claim 2, characterized in that The method further comprises: When it is determined that the first data is not found in the first level cache and the second level cache, querying the first data in parallel from the last level cache and the victim cache based on the target data access rule; Alternatively, when it is determined that the exclusive core flag of the target cache line is used to indicate that the core occupancy state of the target cache line is not locally exclusive, the first data is queried in parallel from the last-level cache and the victim cache based on the target data access rule.

4. The method according to claim 3, characterized in that The method further comprises: If the first data is found in the last-level cache, determining the cache line corresponding to the first data as the target cache line; Determine an exclusive core flag bit corresponding to the target cache line from a tag matrix where the target cache line is located; In a case where it is determined that the exclusive core flag bit of the target cache line is used to indicate that the core occupancy state of the target cache line is not locally exclusive, determining other core flag bits corresponding to the target cache line from the tag matrix; If it is determined that the other core flag is used to indicate that the core occupancy state of the target cache line is occupied by other cores, sending a first monitoring message to the other cores; receiving a reply message sent by the other core based on the first monitoring message, and modifying the flag bits of the other cores in the label matrix according to the reply message to update the label matrix to obtain an updated label matrix; In a case where it is determined that the exclusive core flag bit of the target cache line is used to indicate that the core occupancy state of the target cache line is local exclusive, sending a response message to the target core; If the first data is not found in the last-level cache, searching for the first data in the memory space; When it is determined that the remaining storage space of the last-level cache is greater than the storage space required by the first data, the first data is synchronized to a newly added cache line of the last-level cache.

5. The method according to claim 4, characterized in that The method further comprises: In the case where it is determined that all cache lines of the last-level cache are occupied, determining a shared cache line from all the cache lines; The shared cache line is replaced to the victim cache, a blank cache line where the shared cache line was located before the replacement is determined, and the first data is synchronized to the blank cache line.

6. The method according to claim 2, characterized in that Determining a target cache line corresponding to the data access request from the distributed memory system based on a target data access rule corresponding to the core type of the target core includes: In the case where it is determined that the core type of the target core is other cores, if it is determined that the data access request is used to access second data corresponding to the local core address, querying the second data from the last-level cache based on the target data access rule; If the second data is found in the last-level cache, the cache line corresponding to the second data is determined as the target cache line.

7. The method according to claim 6, characterized in that After querying the second data from the last-level cache based on the target data access rule, the method further includes: If the second data is not found in the last-level cache, searching the victim cache for the second data; If the second data is not found in the victim cache, searching for the second data in a memory space; In the case where the second data is found in the victim cache, determining the victim cache line corresponding to the second data as the target cache line, and sending a second monitoring message to the local core; In response to a reply message sent by the target core based on the second snoop message, the target cache line is replaced into a cache line of the last-level cache.

8. A data access device based on last-level cache, characterized in that: include: a response module, configured to respond to a data access request of a target core, wherein the target core is one of the multiple cores; A determination module, configured to determine a target cache line corresponding to the data access request from a distributed memory system based on a target data access rule corresponding to a core type of the target core; The sending module is used to send a response message to the target core according to the core occupancy state corresponding to the target cache line.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

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