SGT transistor and manufacturing method thereof

Abstract

The invention discloses an SGT transistor and a manufacturing method thereof, and the method comprises the steps: forming a second oxide layer which is flush with the surface of a substrate on the surface of a gate oxide layer in a trench, removing silicon nitride at two sides of the second oxide layer, and filling the two sides of the second oxide layer with second polysilicon which is lower than the surface of the substrate, the second polycrystalline silicon is of a relatively narrow long-strip-shaped structure, and the parasitic capacitance between the gate and the source is obviously reduced, so that the switching frequency of the device is effectively improved, and the switching loss is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device design, and in particular to an SGT transistor and a manufacturing method thereof. Background Art

[0002] The gate polysilicon in the existing shielded gate trench transistor cell structure is located in the upper half of the trench, basically filling the trench opening, making the gate area relatively large, so that the parasitic capacitance between the gate and the source is also relatively large, limiting the further increase of the switching frequency, and the device is not suitable for working under higher frequency conditions. Summary of the invention

[0003] The purpose of the present invention is to provide an SGT transistor in view of the technical problems existing in the background technology.

[0004] In order to achieve the above technical objectives, the technical solution adopted by the present invention is as follows:

[0005] In a first aspect, the present invention provides a method for manufacturing an SGT transistor, comprising:

[0006] S100, providing a substrate, and forming a plurality of grooves on the substrate;

[0007] S200, forming a first oxide layer and a first polysilicon layer in sequence in the trench and on the surface of the substrate;

[0008] S300, etching the first oxide layer and the first polysilicon, and sequentially forming a gate oxide layer and silicon nitride on the surface of the oxide layer and the surface of the first polysilicon;

[0009] S400, forming a second oxide layer flush with the surface of the substrate on the surface of the gate oxide layer in the trench, and removing silicon nitride on both sides of the second oxide layer;

[0010] S500, filling the second polysilicon below the surface height of the substrate on both sides of the second oxide layer;

[0011] S600, forming a plurality of stacked P-type well regions and N-type source regions correspondingly on adjacent sides of the plurality of trenches;

[0012] S700, covering the surface of the first oxide layer, the surface of the second polysilicon, and the surface of the second oxide layer with a dielectric layer, and opening a plurality of contact holes on the dielectric layer that penetrate into the P-type well region;

[0013] S800, covering the plurality of contact holes and the surface of the dielectric layer with a metal layer.

[0014] Optionally, the step S100 includes:

[0015] A substrate is provided, and a surface of the substrate is covered Thickness of the third oxide layer;

[0016] A photolithography process is used to expose a preset groove pattern, and a dry etching process is used to form a plurality of grooves with intervals and a depth of 5 to 6 μm on the substrate according to the groove pattern.

[0017] Optionally, step S200 includes:

[0018] The thickness is formed by a deposition process a first oxide layer covering a surface inside the trench and extending onto a surface of the third oxide layer;

[0019] The thickness is formed by thin film process The first polysilicon fills the inside of the trench and covers the second oxide layer.

[0020] Optionally, step S300 includes:

[0021] A preset first polysilicon pattern is exposed by a photolithography process, and the first polysilicon is etched to 1.0 to 1.4 μm below the surface height of the substrate according to the first polysilicon pattern by a dry etching process;

[0022] A photolithography process is used to expose a preset active area pattern, and a wet etching process is used to etch the first oxide layer according to the active area pattern;

[0023] The thickness is formed by diffusion process A gate oxide layer, the gate oxide layer covers the surface of the first polysilicon and extends to the surface of the third oxide layer;

[0024] A thin film process is used to form a of silicon nitride.

[0025] Optionally, the surface height of the second polysilicon is 0.1-0.18 um lower than the surface height of the substrate.

[0026] Optionally, step S600 includes:

[0027] A plurality of P-type well regions are formed on the surface of the substrate by using an ion implantation process, wherein the plurality of P-type well regions are respectively arranged on adjacent sides of the plurality of trenches;

[0028] By adopting ion implantation technology and according to the active area pattern, a plurality of N-type source regions are formed on the surface of the substrate, and the plurality of N-type source regions are respectively overlapped with a plurality of P-type well regions.

[0029] Optionally, step S700 includes:

[0030] The thickness is formed by thin film process A dielectric layer covering a surface of the second oxide layer, a surface of the second polysilicon, and a surface of the third oxide layer;

[0031] A photolithography process is used to expose a preset contact hole pattern, a dry etching process is used to form multiple contact holes according to the contact hole pattern, the contact holes are interspersed into the P-type well area, and an ion implantation process is used to form a P-type contact area in the contact holes.

[0032] Optionally, step S800 includes:

[0033] Using a thin film process to cover the metal layer in the plurality of contact holes and on the surface of the dielectric layer;

[0034] A photolithography process is used to expose a preset gate pattern and a preset source pattern, and an etching process is used to etch the metal layer according to the gate pattern and the source pattern to form a gate and a source.

[0035] Optionally, the metal layer includes titanium, titanium nitride, tungsten and aluminum.

[0036] In a second aspect, the present invention provides an SGT transistor, which is made by the manufacturing method of the SGT transistor as any of the above-mentioned schemes, and the SGT transistor includes a substrate, a dielectric layer and a metal layer, the substrate is provided with a plurality of grooves and a plurality of contact holes, the plurality of contact holes and the plurality of grooves are cross-arranged, the dielectric layer covers the plurality of grooves, the metal layer covers the dielectric layer and penetrates the plurality of contact holes; the grooves are filled with a first oxide layer, a first polysilicon, a gate oxide layer, silicon nitride, a second polysilicon and a second oxide layer, wherein the first oxide layer, the first polysilicon, the gate oxide layer, the silicon nitride and the second oxide layer are stacked in sequence, the second polysilicon is arranged on both sides of the second oxide layer, the surface height of the second oxide layer is flush with the surface height of the substrate, and the surface height of the second polysilicon is lower than the surface height of the substrate.

[0037] Compared with the prior art, the present invention has the following beneficial technical effects: by forming a second oxide layer flush with the surface height of the substrate on the surface of the gate oxide layer in the groove, removing the silicon nitride on both sides of the second oxide layer, and filling the second polysilicon on both sides of the second oxide layer with a surface height lower than the substrate, the second polysilicon presents a relatively narrow and long strip structure, and the parasitic capacitance between the gate and the source is significantly reduced, thereby effectively improving the switching frequency of the device and reducing the switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of a flow chart of an embodiment of the first aspect of the present invention;

[0039] Figure 2 The process steps of the first embodiment of the present invention are Figure 1 ;

[0040] Figure 3 The process steps of the first embodiment of the present invention are Figure 2 ;

[0041] Figure 4 The process steps of the first embodiment of the present invention are Figure 3 ;

[0042] Figure 5 The process steps of the first embodiment of the present invention are Figure 4 ;

[0043] Figure 6 The process steps of the first embodiment of the present invention are Figure 5 ;

[0044] Figure 7 The process steps of the first embodiment of the present invention are Figure 6 ;

[0045] Figure 8 The process steps of the first embodiment of the present invention are Figure 7 ;

[0046] Fig. 9 The process steps of the first embodiment of the present invention are Figure 8 ;

[0047] Fig.10 The process steps of the first embodiment of the present invention are Figure 9 ;

[0048] Fig.11 The process steps of the first embodiment of the present invention are Figure 10 ;

[0049] Fig.12 The process steps of the first embodiment of the present invention are Figure 10 one;

[0050] Fig.13 The process steps of the first embodiment of the present invention are Figure 10 two;

[0051] Fig.14 The process steps of the first embodiment of the present invention are Figure 10 three;

[0052] Fig.15 The process steps of the first embodiment of the present invention are Figure 10 Four.

[0053] Reference numerals: 100 substrate, 101 third oxide layer, 200 trench, 201 first oxide layer, 202 first polysilicon, 203 gate oxide layer, 204 silicon nitride, 205 second oxide layer, 206 second polysilicon, 300 P-type well region, 400 N-type source region, 500 dielectric layer, 600 contact hole, 700 metal layer. DETAILED DESCRIPTION

[0054] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0055] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", etc. may explicitly or implicitly include one or more features. In the description of the present invention, unless otherwise specified, "" means two or more.

[0056] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or a specific connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0057] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0058] For ease of understanding, the specific process of the embodiment of the first aspect of the present invention is described below. Figure 1-Figure 15 , the manufacturing method of the SGT transistor includes:

[0059] S100, providing a substrate 100, and forming a plurality of grooves 200 on the substrate 100;

[0060] Step S100 includes:

[0061] A substrate 100 is provided, and a surface of the substrate 100 is covered with A third oxide layer 101 having a thickness of 100 mm;

[0062] The pattern of the preset grooves 200 is exposed by a photolithography process, and a plurality of grooves 200 arranged at intervals and having a depth of 5 to 6 μm are formed on the substrate 100 by a dry etching process according to the pattern of the grooves 200 .

[0063] See attached Figure 2 And attached Figure 3 The substrate 100 is made of N-type silicon, the third oxide layer 101 is made of silicon dioxide, and Thickness is deposited on N-type silicon.

[0064] S200, forming a first oxide layer 201 and a first polysilicon layer 202 in sequence in the trench 200 and on the surface of the substrate 100;

[0065] Step S200 includes:

[0066] The thickness is formed by a deposition process The first oxide layer 201 covers the surface inside the trench 200 and extends to the surface of the third oxide layer 101;

[0067] The thickness is formed by thin film process The first polysilicon 202 fills the inside of the trench 200 and covers the second oxide layer 205 .

[0068] See attached Figure 4 And attached Figure 5 The first oxide layer 201 is also made of silicon dioxide, and its deposition thickness is higher than that of the third oxide layer 101 , wherein the first oxide layer 201 can also be grown by a diffusion process.

[0069] S300, etching the first oxide layer 201 and the first polysilicon 202, and sequentially forming a gate oxide layer 203 and a silicon nitride 204 on the surface of the oxide layer and the surface of the first polysilicon 202;

[0070] Step S300 includes:

[0071] A preset first polysilicon 202 pattern is exposed by a photolithography process, and the first polysilicon 202 is etched to 1.0 to 1.4 μm below the surface height of the substrate 100 by a dry etching process according to the first polysilicon 202 pattern;

[0072] A photolithography process is used to expose a preset active area pattern, and a wet etching process is used to etch the first oxide layer 201 according to the active area pattern;

[0073] The thickness is formed by diffusion process A gate oxide layer 203, the gate oxide layer 203 covers the surface of the first polysilicon 202 and extends to the surface of the third oxide layer 101;

[0074] A thin film process is used to form a Silicon nitride 204.

[0075] See attached Figure 6 -Attached Fig. 9 , the side of the first oxide layer 201 etched in the groove 200 close to the first polysilicon 202 is lower than the surface height of the first polysilicon 202. It can be seen from the figure that the surface of the first oxide layer 201 is concave toward the first polysilicon 202. The gate oxide layer 203 and the silicon nitride 204 are sequentially covered on the surface of the oxide layer 201 and the surface of the first polysilicon 202 through corresponding processes. Figure 8 shown.

[0076] S400+, forming a second oxide layer 205 flush with the surface of the substrate 100 on the surface of the gate oxide layer 203 in the trench 200, and removing the silicon nitride 204 on both sides of the second oxide layer 205;

[0077] S500, filling the second polysilicon 206 below the surface height of the substrate 100 on both sides of the second oxide layer 205;

[0078] See attached Fig.10 -Attached Fig.12 The surface height of the second polysilicon 206 is 0.1-0.18um lower than the surface height of the substrate 100, and the width of the second polysilicon 206 is less than 0.5um, that is, the total width of the two second polysilicons 206 on both sides of the second oxide layer 205 is less than 1um, while the height of the gate polysilicon in the conventional SGT transistor is designed to be 1.8-1.9um. The SGT transistor manufactured by the SGT transistor manufacturing method has a smaller volume occupied by the second polysilicon 206 than the conventional SGT transistor under controlled variables, so that theoretically the gate-source capacitance will decrease proportionally, which greatly improves the operating frequency of the device.

[0079] S600 , forming a plurality of stacked P-type well regions 300 and N-type source regions 400 on adjacent sides of the plurality of trenches 200 ;

[0080] Step S600 includes:

[0081] A plurality of P-type well regions 300 are formed on the surface of the substrate 100 by using an ion implantation process. The plurality of P-type well regions 300 are respectively disposed on adjacent sides of the plurality of trenches 200 .

[0082] By adopting an ion implantation process and according to the active region pattern, a plurality of N-type source regions 400 are formed on the surface of the substrate 100 , and the plurality of N-type source regions 400 are respectively overlapped with the plurality of P-type well regions 300 .

[0083] See attached Fig.13 , P-type impurities (boron) are implanted into the surface of the substrate 100 using an ion implantation process, and a P-type well region 300 is formed after furnace annealing; then the active region is exposed using a photolithography process, and N-type impurities (arsenic) are implanted into the surface of the substrate 100, and an N-type source region 400 is formed after furnace annealing.

[0084] S700, covering the surface of the first oxide layer 201, the surface of the second polysilicon 206 and the surface of the second oxide layer 205 with a dielectric layer 500, and opening a plurality of contact holes 600 penetrating to the P-type well region 300 on the dielectric layer 500;

[0085] Step S700 includes:

[0086] The thickness is formed by thin film process The dielectric layer 500 covers the surface of the second oxide layer 205, the surface of the second polysilicon 206 and the surface of the third oxide layer 101;

[0087] A photolithography process is used to expose a preset contact hole 600 pattern, a dry etching process is used to form multiple contact holes 600 according to the contact hole 600 pattern, the contact holes 600 are inserted into the P-type well region 300, and an ion implantation process is used to form a P-type contact region in the contact holes 600.

[0088] S800 , covering the plurality of contact holes 600 and the surface of the dielectric layer 500 with a metal layer 700 .

[0089] Step S800 includes:

[0090] A metal layer 700 is coated in the plurality of contact holes 600 and on the surface of the dielectric layer 500 by using a thin film process;

[0091] A photolithography process is used to expose a preset gate pattern and a preset source pattern, and an etching process is used to etch the metal layer 700 according to the gate pattern and the source pattern to form a gate and a source.

[0092] Specifically, the metal layer 700 includes titanium, titanium nitride, tungsten and aluminum. Titanium, titanium nitride, tungsten and aluminum are deposited in sequence using a CVD (chemical vapor deposition) or PVD (physical vapor deposition) thin film process. The gate and source regions are exposed using a photolithography process. The metal is etched using a dry or wet process (or a combination of the two) to form a gate and source. Finally, the back side is thinned and metallized to form a drain.

[0093] In a second aspect, the present invention provides an SGT transistor, which is manufactured by the manufacturing method of the SGT transistor as described in any one of the above schemes, and the SGT transistor includes a substrate 100, a dielectric layer 500 and a metal layer 700, wherein a plurality of grooves 200 and a plurality of contact holes 600 are provided on the substrate 100, the plurality of contact holes 600 and the plurality of grooves 200 are arranged crosswise, the dielectric layer 500 covers the plurality of grooves 200, and the metal layer 700 covers the dielectric layer 500 and penetrates into the plurality of contact holes 600;

[0094] The groove 200 is filled with a first oxide layer 201, a first polysilicon 202, a gate oxide layer 203, a silicon nitride 204, a second polysilicon 206 and a second oxide layer 205, wherein the first oxide layer 201, the first polysilicon 202, the gate oxide layer 203, the silicon nitride 204 and the second oxide layer 205 are stacked in sequence, the second polysilicon 206 is arranged on both sides of the second oxide layer 205, the surface height of the second oxide layer 205 is flush with the surface height of the substrate 100, and the surface height of the second polysilicon 206 is lower than the surface height of the substrate 100.

[0095] The above is a SGT transistor or multiple implementations provided in combination with specific content, and it is not considered that the specific implementation of the present invention is limited to these descriptions. Any similarity or similarity with the method, structure, etc. of the present invention, or a number of technical deductions or replacements based on the concept of the present invention, should be regarded as the protection scope of the present invention.

Claims

1. A method for manufacturing an SGT transistor, characterized in that: include: S100, providing a substrate (100), and forming a plurality of grooves (200) on the substrate (100); S200, sequentially forming a first oxide layer (201) and a first polysilicon (202) in the trench (200) and on the surface of the substrate (100); S300, etching the first oxide layer (201) and the first polysilicon (202), and sequentially forming a gate oxide layer (203) and silicon nitride (204) on the surface of the oxide layer and the surface of the first polysilicon (202); S400, forming a second oxide layer (205) flush with the surface height of the substrate (100) on the surface of the gate oxide layer (203) in the trench (200), and removing the silicon nitride (204) on both sides of the second oxide layer (205); S500, filling the second polysilicon (206) on both sides of the second oxide layer (205) with a surface height lower than that of the substrate (100); S600, forming a plurality of stacked P-type well regions (300) and N-type source regions (400) on adjacent sides of the plurality of trenches (200); S700, covering the surface of the first oxide layer (201), the surface of the second polysilicon (206), and the surface of the second oxide layer (205) with a dielectric layer (500), and opening a plurality of contact holes (600) on the dielectric layer (500) that penetrate into the P-type well region (300); S800, covering the inside of the plurality of contact holes (600) and the surface of the dielectric layer (500) with a metal layer (700).

2. The method for manufacturing a SGT transistor according to claim 1, characterized in that: The step S100 includes: A substrate (100) is provided, and a surface of the substrate (100) is covered with A third oxide layer (101) having a thickness of A photolithography process is used to expose a preset groove (200) pattern, and a dry etching process is used to form a plurality of grooves (200) arranged at intervals and having a depth of 5 to 6 μm on the substrate (100) according to the groove (200) pattern.

3. The method for manufacturing a SGT transistor according to claim 2, characterized in that: The S200 includes: The thickness is formed by a deposition process a first oxide layer (201), wherein the first oxide layer (201) covers the surface inside the groove (200) and extends to the surface of the third oxide layer (101); The thickness is formed by thin film process The first polysilicon (202) is filled in the interior of the trench (200) and covers the second oxide layer (205).

4. The method for manufacturing a SGT transistor according to claim 3, characterized in that: The S300 includes: Using a photolithography process to expose a preset first polysilicon (202) pattern, and using a dry etching process to etch the first polysilicon (202) to a height of 1.0 to 1.4 μm below the surface height of the substrate (100) according to the first polysilicon (202) pattern; Using a photolithography process to expose a preset active area pattern, and using a wet etching process to etch the first oxide layer (201) according to the active area pattern; The thickness is formed by diffusion process a gate oxide layer (203), the gate oxide layer (203) covering the surface of the first polysilicon (202) and extending to the surface of the third oxide layer (101); A thin film process is used to form a Silicon nitride (204).

5. The method for manufacturing a SGT transistor according to claim 4, characterized in that: The surface height of the second polysilicon (206) is 0.1 to 0.18 um lower than the surface height of the substrate (100).

6. The method for manufacturing a SGT transistor according to claim 5, characterized in that: The S600 includes: An ion implantation process is used to form a plurality of P-type well regions (300) on the surface of the substrate (100), wherein the plurality of P-type well regions (300) are respectively and correspondingly arranged on adjacent sides of the plurality of grooves (200); A plurality of N-type source regions (400) are formed on the surface of the substrate (100) by using an ion implantation process and according to the active region pattern, and the plurality of N-type source regions (400) are respectively and correspondingly stacked on the plurality of P-type well regions (300).

7. The method for manufacturing a SGT transistor according to claim 6, characterized in that: The S700 includes: The thickness is formed by thin film process a dielectric layer (500), wherein the dielectric layer (500) covers a surface of the second oxide layer (205), a surface of the second polysilicon (206), and a surface of the third oxide layer (101); A photolithography process is used to expose a preset contact hole (600) pattern, a dry etching process is used to form a plurality of contact holes (600) according to the contact hole (600) pattern, the contact holes (600) are inserted into the P-type well region (300), and an ion implantation process is used to form a P-type contact region in the contact holes (600).

8. The method for manufacturing a SGT transistor according to claim 7, characterized in that: The S800 includes: Using a thin film process to cover the metal layer (700) in the plurality of contact holes (600) and on the surface of the dielectric layer (500); A photolithography process is used to expose a preset gate pattern and a preset source pattern, and an etching process is used to etch the metal layer (700) according to the gate pattern and the source pattern to form a gate and a source.

9. The method for manufacturing a SGT transistor according to claim 8, characterized in that: The metal layer (700) includes titanium, titanium nitride, tungsten and aluminum.

10. An SGT transistor, characterized in that: It is manufactured by the manufacturing method of the SGT transistor according to any one of claims 1 to 9, and the SGT transistor comprises: A substrate (100) having a plurality of grooves (200) and a plurality of contact holes (600) disposed thereon, wherein the plurality of contact holes (600) and the plurality of grooves (200) are arranged crosswise; A dielectric layer (500), covering the plurality of grooves (200); A metal layer (700), covering the dielectric layer (500) and penetrating into the plurality of contact holes (600); The groove (200) is filled with a first oxide layer (201), a first polysilicon (202), a gate oxide layer (203), silicon nitride (204), a second polysilicon (206) and a second oxide layer (205), wherein the first oxide layer (201), the first polysilicon (202), the gate oxide layer (203), the silicon nitride (204) and the second oxide layer (205) are stacked in sequence, the second polysilicon (206) is arranged on both sides of the second oxide layer (205), the surface height of the second oxide layer (205) is flush with the surface height of the substrate (100), and the surface height of the second polysilicon (206) is lower than the surface height of the substrate (100).

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