Wafer bonding method

Abstract

The invention provides a wafer bonding method, which comprises the following steps that a first silicon substrate is provided, a plurality of concave cavities are formed in a preset area of the first silicon substrate, the concave cavities are opened from the top surface of the first silicon substrate and extend downwards by a preset depth, and getter layers are formed on the bottom walls and the side walls of the concave cavities; providing a second silicon substrate, and directly bonding the first silicon substrate and the second silicon substrate; and annealing treatment. According to the invention, by introducing the activation treatment, the first silicon substrate and the second silicon substrate can realize high-quality bonding at a low temperature, and a strong bonding force is maintained. Meanwhile, a plurality of concave cavities filled with getter layers are formed in the first silicon substrate, and the getter layers are activated by adopting vacuum heating treatment, so that the getter layers can quickly and effectively absorb gases such as water vapor and the like generated on an interface in the low-temperature annealing process, the gases are effectively prevented from being accumulated at the bonding interface, cavities are effectively prevented from being formed, and the bonding quality of the semiconductor device is improved. And the reliability and the stability of direct bonding are further improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a wafer bonding method. Background Art

[0002] In the field of semiconductor technology, the direct bonding process between silicon wafers (silicon-silicon direct bonding) has become a key technology in integrated circuit manufacturing, micro-electromechanical system (MEMS) packaging, and multi-functional chip integration because it can achieve high-strength and high-stability connection characteristics without the need for adhesives.

[0003] The direct bonding process between silicon wafers mainly includes two core steps: pre-bonding and annealing. Among them, the annealing stage is carried out in a high temperature environment, and its main purpose is to promote the chemical reaction of hydroxyl groups (-OH) on the surface of the silicon wafer to form a stable covalent bond (Si-O-Si) structure to achieve a strong bond between silicon wafers. However, this chemical reaction is accompanied by the generation of byproduct water vapor, which may further react with the silicon wafer under high temperature annealing conditions to generate hydrogen. If these water vapor and hydrogen and other gases are not removed in time, they will accumulate at the bonding interface, resulting in the formation of voids or microgaps at the bonding interface, which seriously affects the quality of the bonding interface. Therefore, in the prior art, annealing is usually required at a high temperature of more than 800°C to promote the formation of (Si-O-Si) covalent bonds and improve the bonding strength. At the same time, the escape and diffusion of byproducts such as water vapor and hydrogen are accelerated to reduce the risk of voids forming at the bonding interface. However, this high-temperature annealing condition of over 800°C will also pose challenges to some temperature-sensitive components, which may cause changes in material properties, performance degradation, and even failure, thereby limiting the application of silicon wafer direct bonding technology in a wider range of fields.

[0004] Therefore, how to provide a new wafer bonding method to avoid damage to temperature-sensitive components caused by high-temperature annealing conditions during silicon-silicon direct bonding while ensuring high-quality direct bonding between silicon wafers has become an important technical problem that needs to be urgently solved by technical personnel in this field.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a wafer bonding method for solving the technical problem of damage to temperature sensitive components caused by high temperature annealing conditions during the prior art silicon-silicon direct bonding process, while ensuring high-quality direct bonding between silicon wafers.

[0007] To achieve the above object and other related objects, the present invention provides a wafer bonding method, comprising the following steps:

[0008] Providing a first silicon substrate, wherein a plurality of cavities are formed in a preset area of ​​the first silicon substrate, the cavities are opened from the top surface of the first silicon substrate and extend downward to a preset depth, and a getter layer is formed on the bottom wall and side wall of the cavities;

[0009] Providing a second silicon substrate, and directly bonding the first silicon substrate to the second silicon substrate;

[0010] The first silicon substrate and the second silicon substrate that have been bonded are annealed.

[0011] Optionally, before directly bonding the first silicon substrate and the second silicon substrate, the method further includes performing an activation treatment on the surface of the first silicon substrate and the surface of the second silicon substrate.

[0012] Optionally, the activation treatment includes any one of plasma activation treatment and wet activation treatment.

[0013] Optionally, before directly bonding the first silicon substrate to the second silicon substrate, the method further includes performing a vacuum heating treatment on the first silicon substrate to activate the getter layer.

[0014] Optionally, the getter layer comprises a porous structure, and a material of the getter layer comprises at least one of nickel, aluminum, titanium and copper.

[0015] Optionally, the getter layer has a thickness ranging from 0.2 micrometers to 0.5 micrometers.

[0016] Optionally, the temperature of the annealing treatment does not exceed 400°C.

[0017] Optionally, the forming of the cavity comprises the following steps:

[0018] forming a photoresist layer on the first silicon substrate;

[0019] Patterning the photoresist layer to form an opening exposing the surface of the first silicon substrate, wherein the opening is located in a blank area of ​​the first silicon substrate;

[0020] The first silicon substrate is etched based on the opening to form a plurality of the cavities.

[0021] Optionally, the method further comprises the following steps:

[0022] forming a getter film layer on the photoresist layer, wherein the getter film layer partially fills the cavity and covers the bottom wall and side walls of the cavity;

[0023] removing the photoresist layer and the getter film layer on the photoresist layer, wherein the portion of the getter film layer covering the bottom wall and the side wall of the cavity serves as the getter layer;

[0024] The surface of the first silicon substrate is planarized.

[0025] Optionally, the depth of the cavity ranges from 2 microns to 3 microns.

[0026] As described above, the present invention provides a wafer bonding method, which includes the following steps: providing a first silicon substrate, a preset area of ​​the first silicon substrate is formed with a plurality of cavities, the cavities are opened from the top surface of the first silicon substrate and extend downward to a preset depth, and a getter layer is formed on the bottom wall and side wall of the cavities; providing a second silicon substrate, directly bonding the first silicon substrate to the second silicon substrate; and annealing the bonded first silicon substrate and the second silicon substrate. The wafer bonding method of the present invention introduces an activation treatment, so that the first silicon substrate and the second silicon substrate can achieve high-quality bonding under low temperature conditions and maintain a strong bonding force. At the same time, the present invention forms a plurality of cavities filled with a getter layer in the first silicon substrate, and activates the getter layer by vacuum heating treatment, so that it can quickly and effectively absorb water vapor and other gases generated at the interface during low-temperature annealing, thereby effectively avoiding the accumulation of gas at the bonding interface, effectively preventing the formation of voids, and improving the reliability and stability of direct bonding. In addition, the wafer bonding method of the present invention effectively avoids thermal damage or defects to semiconductor devices caused by high-temperature annealing by achieving bonding under low temperature conditions. This low-temperature bonding technology has broad application value and market prospects in precision manufacturing fields such as micro-electromechanical system devices, silicon-on-insulator devices, and piezoelectric and acousto-optic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a process flow chart of a wafer bonding method of the present invention.

[0028] Figure 2 It is a schematic diagram of a cross-sectional structure after a photoresist layer is formed on the first silicon substrate in a wafer bonding method of the present invention.

[0029] Figure 3 It is a schematic diagram of a cross-sectional structure after an opening is formed in the photoresist layer to expose the surface of the first silicon substrate in a wafer bonding method of the present invention.

[0030] Figure 4 It is a schematic diagram of a cross-sectional structure after a plurality of cavities are formed in a wafer bonding method of the present invention.

[0031] Figure 5It shows a schematic cross-sectional structure diagram after a getter film layer is formed on the photoresist layer in a wafer bonding method of the present invention, and the getter film layer partially fills the cavity and covers the bottom wall and side wall of the cavity.

[0032] Figure 6 It is a schematic diagram of a cross-sectional structure after removing the photoresist layer and the getter film layer on the photoresist layer in a wafer bonding method of the present invention.

[0033] Figure 7 A top view showing the distribution of the getter layer on the first silicon substrate in a wafer bonding method of the present invention.

[0034] Figure 8 It is a schematic diagram of the cross-sectional structure after the first silicon substrate and the second silicon substrate are directly bonded in a wafer bonding method of the present invention.

[0035] Component number description

[0036] 1 The first silicon substrate

[0037] 11 Photoresist layer

[0038] 12 Opening

[0039] 13 Cavity

[0040] 14 Getter film layer

[0041] 15 Getter layer

[0042] 2 Second silicon substrate

[0043] Steps S1 to S3 DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] See also Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0046] This embodiment provides a wafer bonding method. Figure 1 , shown as a process flow chart of the method, comprising the following steps:

[0047] S1: providing a first silicon substrate, wherein a plurality of cavities are formed in a preset area of ​​the first silicon substrate, the cavities are opened from the top surface of the first silicon substrate and extend downward to a preset depth, and a getter layer is formed on the bottom wall and side wall of the cavities;

[0048] S2: providing a second silicon substrate, and directly bonding the first silicon substrate to the second silicon substrate;

[0049] S3: performing annealing treatment on the first silicon substrate and the second silicon substrate after bonding.

[0050] Combine the following Figure 2-Figure 8 The specific technical solutions of each step of the wafer bonding method of the present invention are described in detail.

[0051] First see Figure 2-Figure 7 , perform step S1: provide a first silicon substrate 1, a preset area of ​​the first silicon substrate 1 is formed with a plurality of cavities 13, the cavities 13 are opened from the top surface of the first silicon substrate 1 and extend downward to a preset depth, and the bottom wall and side wall of the cavities 13 are formed with a getter layer 15.

[0052] As an example, the first silicon substrate 1 may be a silicon wafer commonly used in the semiconductor manufacturing field or a silicon wafer with an insulating layer, ie, Silicon On Insulator (SOI).

[0053] Specifically, in some embodiments, the first silicon substrate 1 includes a silicon wafer and semiconductor devices fabricated on the surface of the silicon wafer, and includes various films and structures required for these semiconductor devices. The size and thickness of the first silicon substrate 1 are not excessively limited here.

[0054] As an example, the formation of the cavity 13 includes the following steps:

[0055] (1) Figure 2 As shown, a photoresist layer 11 is formed on the first silicon substrate 1;

[0056] (2) Figure 3 As shown, the photoresist layer 11 is patterned to form an opening 12 exposing the surface of the first silicon substrate 1, and the opening 12 is located in a blank area of ​​the first silicon substrate 1;

[0057] (3) Figure 4 As shown, the first silicon substrate 1 is etched based on the opening 12 to form a plurality of the concave cavities 13 .

[0058] Specifically, the method of forming the photoresist layer 11 includes spraying, spin coating or other suitable methods.

[0059] Specifically, the photoresist layer 11 is patterned by conventional photolithography and development processes to form the opening 12 , and the opening 12 is located in a blank area of ​​the first silicon substrate 1 , that is, the opening 12 is located in a non-device area of ​​the first silicon substrate 1 .

[0060] Specifically, the method of etching the first silicon substrate 1 includes wet etching, dry etching or other suitable methods.

[0061] As an example, the depth of the cavity 13 ranges from 2 micrometers to 3 micrometers.

[0062] As an example, at least one of the concave cavities 13 has a preset distance from the edge of the first silicon substrate 1 .

[0063] Specifically, in some embodiments, the plurality of cavities 13 are located in the central region of the first silicon substrate 1. In other embodiments, the plurality of cavities 13 are located in the central region and the edge region of the first silicon substrate 1.

[0064] Of course, in some other embodiments, the plurality of cavities 13 may also be located only in the edge region of the first silicon substrate 1 .

[0065] It should be noted that, in this embodiment, the specific positions and distribution of the plurality of cavities 13 are determined by the positions and distribution of the non-device area of ​​the first silicon substrate 1, and are not limited to a single layout or distribution. More importantly, the cavities 13 will not adversely affect the performance of the semiconductor devices or other structures in the first silicon substrate 1, nor will they affect the subsequent process. In this embodiment, the layout of the cavities 13 is preferably such that the plurality of cavities 13 are located in the central area and the edge area of ​​the first silicon substrate 1.

[0066] Specifically, the number of the concave cavities 13 can be selected according to the amount of water vapor generated during the bonding process, the wafer size, the bonding process requirements, etc., and is not limited here.

[0067] As an example, the wafer bonding method further includes the following steps:

[0068] (1) Figure 5 As shown, a getter film layer 14 is formed on the photoresist layer 11, and the getter film layer 14 partially fills the cavity 13 and covers the bottom wall and side wall of the cavity 13;

[0069] (2) Figure 6As shown, the photoresist layer 11 and the getter film layer 14 on the photoresist layer 11 are removed, wherein the getter film layer 14 covers the bottom wall and the side wall of the cavity 13 as the getter layer 15;

[0070] (3) Planarizing the surface of the first silicon substrate 1 (not shown).

[0071] Specifically, the method of forming the getter film layer 14 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0072] Specifically, while forming the getter film layer 14, the performance of the getter film layer 14 can be optimized by adjusting process parameters such as chamber pressure, deposition time, temperature, gas composition, gas flow rate, substrate bias, etc., thereby regulating key characteristics of the getter film layer 14 such as thickness, particle size, uniformity and porosity.

[0073] Specifically, the photoresist layer 11 and the getter film layer 14 on the photoresist layer 11 are removed by a stripping method or other appropriate methods.

[0074] As an example, the material of the getter layer 15 includes at least one of nickel, aluminum, titanium and copper. In this embodiment, the material of the getter layer 15 is preferably nickel.

[0075] As an example, the getter layer 15 has a thickness ranging from 0.2 micrometers to 0.5 micrometers.

[0076] As an example, the getter layer 15 comprises a porous structure.

[0077] As an example, the porosity of the getter layer 15 is in the range of 25%-65%.

[0078] Specifically, by controlling the internal porosity of the getter layer 15, the adsorption capacity of the getter layer 15 for gases such as water vapor can be significantly optimized. The porous structure of the getter layer 15 has more adsorption sites, which promote the attachment and fixation of gas molecules such as water vapor in the getter layer 15, thereby effectively enhancing the adsorption efficiency of the getter layer 15.

[0079] Specifically, a CMP (Chemical Mechanical Polishing) process or other suitable process may be used to planarize the surface of the first silicon substrate 1 to improve the flatness of the surface of the first silicon substrate 1 and provide a good bonding interface.

[0080] Please see again Figure 7 , which is a top view showing the distribution of the getter layer 15 on the first silicon substrate 1 in this embodiment.

[0081] Specifically, for the sake of simplicity of illustration, Figure 7 Only one example is shown, in which the plurality of cavities 13 are located in the central region and the edge region of the first silicon substrate 1, and the getter layer 15 fills the bottom walls and the side walls of the plurality of cavities 13. However, this is not the only layout mode, that is, the distribution of the plurality of cavities 13 and the getter layer 15 filling the bottom walls and the side walls of the cavities 13 on the first silicon substrate 1 is not limited to this layout mode or distribution, and can be flexibly adjusted according to the actual design layout of the first silicon substrate 1.

[0082] Please see again Figure 8 , perform the step S2: provide a second silicon substrate 2, and directly bond the first silicon substrate 1 to the second silicon substrate 2.

[0083] Specifically, the second silicon substrate 2 may also be a silicon wafer commonly used in the semiconductor manufacturing field or a silicon wafer with an insulating layer, ie, Silicon On Insulator (SOI).

[0084] Specifically, in some embodiments, the second silicon substrate 2 may also include a silicon wafer and semiconductor devices fabricated on the surface of the silicon wafer, and include various films and various structures required for these semiconductor devices. The size, thickness, etc. of the second silicon substrate 2 are not excessively limited here.

[0085] As an example, before directly bonding the first silicon substrate 1 and the second silicon substrate 2 , the method further includes a step of activating the surface of the first silicon substrate 1 and the surface of the second silicon substrate 2 .

[0086] As an example, before activating the surface of the first silicon substrate 1 and the surface of the second silicon substrate 2 , a step of performing RCA standard cleaning on the first silicon substrate 1 and the second silicon substrate 2 is also included.

[0087] Specifically, in this embodiment, the first silicon substrate 1 and the second silicon substrate 2 are cleaned according to the RCA standard to remove organic or inorganic pollutants on the surfaces of the first silicon substrate 1 and the second silicon substrate 2 and provide a clean surface for subsequent activation treatment.

[0088] As an example, the activation process includes any one of a plasma activation process and a wet activation process.

[0089] As an example, the activation treatment is a plasma activation treatment. The plasma activation treatment is used to enhance the hydrophilicity of the surfaces of the first silicon substrate 1 and the second silicon substrate 2 and improve the surface energy.

[0090] As an example, the gas used in the plasma activation process includes at least one of hydrogen, argon, nitrogen and oxygen.

[0091] Specifically, when the surface of the first silicon substrate 1 and the surface of the second silicon substrate 2 are not oxidized, at least one gas selected from hydrogen, argon and nitrogen may be used to perform plasma activation treatment on the surface of the first silicon substrate 1 and the surface of the second silicon substrate 2 to remove organic pollutants on the surface of the first silicon substrate 1 and the second silicon substrate 2, and to form active sites on the surface of the first silicon substrate 1 and the second silicon substrate 2. When an oxide layer exists on the surface of the first silicon substrate 1 and the surface of the second silicon substrate 2, oxygen may be used to perform plasma activation treatment on the surface of the first silicon substrate 1 and the surface of the second silicon substrate 2 to remove oxides on the surface of the first silicon substrate 1 and the second silicon substrate 2, and to further activate the surface of the first silicon substrate 1 and the second silicon substrate 2.

[0092] More specifically, after the plasma activation treatment, hydroxyl groups (-OH) are formed on the surface of the first silicon substrate 1 and the surface of the second silicon substrate 2, and these hydroxyl groups (-OH) greatly increase the hydrophilicity of the surface of the first silicon substrate 1 and the second silicon substrate 2, and significantly improve the surface energy. This enhanced hydrophilicity and improved surface energy significantly optimize the interface characteristics between the first silicon substrate 1 and the second silicon substrate 2, and provide a tighter, stronger and more stable bonding surface for the direct bonding of the two. In addition, the improvement of the surface energy and hydrophilicity of the first silicon substrate 1 and the second silicon substrate 2 helps to promote viscous flow during the bonding process, thereby improving the uniformity and strength of the direct bonding of the first silicon substrate 1 and the second silicon substrate 2. In this embodiment, the surface characteristics of the first silicon substrate 1 and the second silicon substrate 2 can be effectively improved by the plasma activation treatment, so that the bonding process that originally needed to be carried out under high temperature annealing can now be achieved at a lower annealing temperature, and the bonding strength meets the product's requirements for bonding strength.

[0093] As an example, before directly bonding the first silicon substrate 1 to the second silicon substrate 2 , a step of vacuum heating the first silicon substrate 1 is further included to activate the getter layer 15 .

[0094] As an example, the temperature range of the vacuum heating treatment is 100°C to 400°C, and the time range of the vacuum heating treatment is 10 minutes to 50 minutes. Specifically, in this embodiment, the temperature of the vacuum heating treatment is preferably 350°C, and the time of the vacuum heating treatment is preferably 30 minutes. This embodiment can effectively improve the chemical activity of the getter layer 15, improve the absorption efficiency of the getter layer 15, and enhance the adsorption capacity of the getter layer 15 to water vapor or other gases by precisely controlling the temperature and time of the vacuum heating treatment.

[0095] Specifically, in this embodiment, the getter layer 15 after vacuum heating treatment can quickly and effectively absorb water vapor and gases such as hydrogen generated during the annealing bonding process of the first silicon substrate 1 and the second silicon substrate 2, thereby effectively avoiding the generation of voids at the bonding interface and improving the quality of the bonding interface.

[0096] Please perform the step S3: perform annealing treatment on the first silicon substrate 1 and the second silicon substrate 2 after bonding (not shown).

[0097] Specifically, the first silicon substrate 1 and the second silicon substrate 2 after bonding are annealed in a furnace tube.

[0098] As an example, the temperature of the annealing process does not exceed 400°C.

[0099] Specifically, in this embodiment, the first silicon substrate 1 and the second silicon substrate 2 treated by plasma activation can be directly bonded under low temperature annealing conditions not exceeding 400° C. and maintain strong bonding strength. This embodiment not only avoids thermal damage or defects that may be caused by high temperature annealing to the semiconductor devices in the first silicon substrate 1 and the second silicon substrate 2, but also ensures high quality of bonding.

[0100] Specifically, the water vapor and hydrogen generated during the annealing process have two diffusion paths: one is to diffuse into the interior of the first silicon substrate 1 and the second silicon substrate 2; the other is to diffuse to the edge of the substrate along the bonding interface between the two. In this embodiment, the highly absorbent getter layer 15 ensures that the escape and diffusion of water vapor and hydrogen generated during the annealing process in any direction can be quickly and effectively absorbed, thereby effectively avoiding the accumulation of gas at the bonding interface and effectively preventing the formation of voids.

[0101] In summary, the present invention provides a wafer bonding method, which includes the following steps: providing a first silicon substrate, a preset area of ​​the first silicon substrate is formed with a plurality of cavities, the cavities are opened from the top surface of the first silicon substrate and extend downward to a preset depth, and a getter layer is formed on the bottom wall and side wall of the cavities; providing a second silicon substrate, directly bonding the first silicon substrate to the second silicon substrate; and annealing the bonded first silicon substrate and the second silicon substrate. The wafer bonding method of the present invention introduces an activation treatment, so that the first silicon substrate and the second silicon substrate can achieve high-quality bonding under low temperature conditions and maintain a strong bonding force. At the same time, the present invention forms a plurality of cavities filled with a getter layer in the first silicon substrate, and activates the getter layer by vacuum heating treatment, so that it can quickly and effectively absorb water vapor and other gases generated at the interface during low-temperature annealing, thereby effectively avoiding the accumulation of gas at the bonding interface, effectively preventing the formation of voids, and improving the reliability and stability of direct bonding. In addition, the wafer bonding method of the present invention effectively avoids thermal damage or defects to semiconductor devices caused by high-temperature annealing by achieving bonding under low temperature conditions. This low temperature bonding technology has broad application value and market prospects in the precision manufacturing fields of micro-electromechanical system devices, silicon-on-insulator devices, piezoelectric and acousto-optic devices, etc. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0102] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A wafer bonding method, characterized in that: The following steps are involved: Providing a first silicon substrate, wherein a plurality of cavities are formed in a preset area of ​​the first silicon substrate, the cavities are opened from the top surface of the first silicon substrate and extend downward to a preset depth, and a getter layer is formed on the bottom wall and side wall of the cavities; Providing a second silicon substrate, and directly bonding the first silicon substrate to the second silicon substrate; The first silicon substrate and the second silicon substrate that have been bonded are annealed.

2. The wafer bonding method according to claim 1, characterized in that: Before directly bonding the first silicon substrate and the second silicon substrate, the method further includes a step of activating the surface of the first silicon substrate and the surface of the second silicon substrate.

3. The wafer bonding method according to claim 2, characterized in that: The activation treatment includes any one of plasma activation treatment and wet activation treatment.

4. The wafer bonding method according to claim 1, characterized in that: Before directly bonding the first silicon substrate to the second silicon substrate, the method further includes performing a vacuum heating treatment on the first silicon substrate to activate the getter layer.

5. The wafer bonding method according to claim 1, characterized in that: The getter layer comprises a porous structure, and a material of the getter layer comprises at least one of nickel, aluminum, titanium and copper.

6. The wafer bonding method according to claim 1, characterized in that: The thickness of the getter layer is in the range of 0.2 micrometer to 0.5 micrometer.

7. The wafer bonding method according to claim 1, characterized in that: The temperature of the annealing treatment does not exceed 400°C.

8. The wafer bonding method according to claim 1, characterized in that: The formation of the cavity comprises the following steps: forming a photoresist layer on the first silicon substrate; Patterning the photoresist layer to form an opening exposing the surface of the first silicon substrate, wherein the opening is located in a blank area of ​​the first silicon substrate; The first silicon substrate is etched based on the opening to form a plurality of the cavities.

9. The wafer bonding method according to claim 8, characterized in that: The following steps are also included: forming a getter film layer on the photoresist layer, wherein the getter film layer partially fills the cavity and covers the bottom wall and side walls of the cavity; removing the photoresist layer and the getter film layer on the photoresist layer, wherein the portion of the getter film layer covering the bottom wall and the side wall of the cavity serves as the getter layer; The surface of the first silicon substrate is planarized.

10. The wafer bonding method according to claim 1, characterized in that: The depth of the cavity is in the range of 2 micrometers to 3 micrometers.

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