Double-gate LDMOS device and preparation method thereof

Abstract

The invention discloses a double-gate LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, the double-gate LDMOS device comprises a substrate, a buried gate layer, a body region, a drift region, a body electrode, a source electrode, a shallow trench isolation, a drain electrode and a gate oxide layer, wherein the body electrode and the source electrode are positioned in the body region and on the same side as the buried gate layer; the shallow trench isolation is positioned at the top of the drift region; the second grid electrode is positioned above the gate oxide layer; the buried gate layer sequentially comprises a first oxide layer, a first gate and a second oxide layer from bottom to top; and side walls are arranged at two ends of the second grid electrode. Through the arrangement of the buried gate layer, the depletion region can extend more in the N-type drift region, the electric field intensity between the source electrode and the drain electrode is reduced, and then the off-state voltage endurance capability is improved; besides, the structure can generate a channel at the buried gate layer in an on state, so that a current path is increased, the conduction current is increased under the same voltage, and the on-state conduction resistance is reduced while the off-state breakdown voltage is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a double-gate LDMOS device and a preparation method thereof. Background Art

[0002] In the post-Moore era, the development trend of integrated circuits has shifted from miniaturization to functionalization, and power integrated circuits have been widely used in many fields such as power control, automotive electronics, consumer and communication electronics. BCD (Bipolar-CMOS-DMOS) technology is currently the most critical single-chip power integrated circuit technology. It is a manufacturing process that integrates Bipolar (bipolar), CMOS (complementary metal oxide semiconductor) and DMOS (double diffused metal oxide semiconductor) structures. Compared with traditional bipolar power processes, BCD technology has significant advantages. Its most basic advantage is that designers can flexibly choose between high-precision analog bipolar, highly integrated CMOS and DMOS as a power stage. Since the DMOS process is compatible with the CMOS process and has the characteristics of high efficiency (low loss), high strength (no secondary breakdown), and high withstand voltage, the DMOS structure is particularly suitable for power integrated circuits.

[0003] In the DMOS structure used in BCD technology, lateral double-diffused metal oxide semiconductor (LDMOS) is widely used in power integrated circuits. LDMOS uses lateral double diffusion technology to dope B (boron) and P (phosphorus) ions in the same window at the same time, and forms a channel structure by taking advantage of the different diffusion rates of different ions. The lateral double diffusion technology can accurately control the device channel size, so that LDMOS has a large input impedance, low power consumption in driving applications and easy coupling with the previous stage. In addition, LDMOS has negative temperature characteristics, and the leakage current can automatically flow at high temperatures, so it is not easy to form local hot spots and has high reliability. Since the source, drain, and gate of LDMOS devices are all on the chip surface, they can be integrated with CMOS and Bipolar, making them very suitable for use as power output devices. With the development of medium and low voltage consumer electronics applications such as motor drive, power management, and automotive electronics, high-density and small-size BCD process technology integrated with LDMOS devices has gradually become a mainstream platform technology, and LDMOS has also become the focus and difficulty of device design in BCD technology. Therefore, studying how to develop a stable LDMOS process has important economic benefits.

[0004] How to balance the off-state breakdown voltage and on-state on-resistance of LDMOS is a difficult point in the development of LDMOS devices. The traditional LDMOS structure relies on the drift region with lower doping to bear the voltage. The lower doping concentration means a decrease in the number of carriers. According to the formula σ=nqμn+pqμp, ρ=1 / σ, it can be seen that the resistivity will increase due to low doping, making the on-resistance larger and the current smaller; if you want to reduce the on-resistance, you need to increase the doping concentration of the drift region, which will lead to an increase in the peak value of the electric field when the off-state is under pressure, reducing the off-state breakdown voltage. Therefore, there is an irreconcilable contradiction between the on-state on-resistance and the off-state breakdown voltage of the traditional LDMOS. When developing devices, you have to make a trade-off between the two. This contradiction can only be solved through the development of new LDMOS device structures. Summary of the invention

[0005] The first object of the present invention is to provide a dual-gate LDMOS device in view of the deficiencies in the prior art.

[0006] A dual-gate LDMOS device comprises a substrate, a buried gate layer on the substrate, a P-type body region and an N-type drift region above the buried gate layer, a body electrode and a source electrode located in the P-type body region and on the same side as the buried gate layer, a shallow trench isolation located at the top of the N-type drift region, a drain electrode located inside the N-type drift region, a gate oxide layer located above the P-type body region and the N-type drift region, and a second gate electrode located above the gate oxide layer; the buried gate layer comprises a first oxide layer, a first gate electrode and a second oxide layer in order from bottom to top; and side walls are provided at both ends of the second gate electrode.

[0007] Preferably, the sum of the thickness of the first oxide layer and the second oxide layer accounts for 20% to 90% of the total thickness of the buried gate layer.

[0008] Preferably, an isolation oxide layer is provided between the second gate and the sidewall.

[0009] Preferably, the substrate is made of silicon, and the sidewalls are made of silicon nitride.

[0010] Preferably, the position of the buried gate layer can be adjusted up and down in the P-type body region and the N-type drift region.

[0011] A second object of the present invention is to provide a method for preparing the above-mentioned dual-gate LDMOS device, comprising the following steps:

[0012] Doping the substrate, and then forming a first oxide layer, a first gate, and a second oxide layer on the surface of the substrate to complete the preparation of the buried gate layer;

[0013] An epitaxial layer is grown on the buried gate layer, and an N-type drift region and a P-type body region are formed after doping;

[0014] A shallow trench isolation is etched on the top of the N-type drift region;

[0015] Growing a gate oxide layer on the surface of the epitaxial layer, and then forming a second gate on the surface of the gate oxide layer;

[0016] An isolation oxide layer and a sidewall are formed on both sides of the second gate, and ion implantation is performed to form a body electrode / source and a drain.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention provides a dual-gate structure LDMOS with a buried gate layer, which is used to solve the contradiction that the on-state conduction resistance of LDMOS cannot be reduced and the off-state breakdown voltage cannot be increased at the same time. In the design of LDMOS, the depletion region is a key concept, which refers to the charge depletion region formed in the semiconductor material due to the difference in doping concentration. The existence of the depletion region is crucial for controlling the electrical characteristics of the device. In the present invention, the first gate and the second gate are both arranged inside the overall device structure, which can make the depletion region extend more in the N-type drift region, reduce the electric field strength between the source and the drain, and thus improve the off-state withstand voltage capability; in addition, the structural design of the gate arranged inside the device also enables the structure to generate a channel at the buried gate layer when in the on state, thereby increasing the current path, so that the on-state current increases at the same voltage, that is, the on-resistance decreases, and the on-state conduction resistance is reduced while the off-state breakdown voltage is increased; and the structure of the present invention is relatively simple, easy to prepare, and operable.

[0019] In the present invention, the position of the buried gate layer can be adjusted up and down. When the buried gate layer is located in the lower middle part, the breakdown voltage can be increased and the on-resistance can be reduced at the same time. If the buried gate layer is located at the upper part, only the on-resistance can be reduced and the breakdown voltage will be reduced. If it is located at the lower part, the breakdown voltage will increase and the on-resistance optimization will be smaller. It can be adjusted according to actual needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a dual-gate LDMOS device of the present invention.

[0021] Figure 2 (a) to (t) are the preparation process of the dual-gate LDMOS device of the present invention.

[0022] Figure 3 It is a schematic diagram of upward adjustment of the position of the buried gate layer in the dual-gate LDMOS device of the present invention.

[0023] Figure 4 (a) is the depletion region image without the buried gate layer structure when testing the breakdown voltage, and (b) is the depletion region image with the buried gate layer structure when testing the breakdown voltage (the white line is the edge of the depletion region).

[0024] Figure 5 Comparison of breakdown voltage with and without buried gate layer structure.

[0025] Figure 6 (a) is the output characteristic curve in the on state, (b) is the current density distribution diagram without the buried gate layer when testing the on current, and (c) is the current density distribution diagram with the buried gate layer when testing the on current.

[0026] Markings in the figure: 1, substrate; 2, buried gate layer; 2-1, first oxide layer; 2-2, first gate; 2-3, second oxide layer; 3, P-type body region; 4, N-type drift region; 5, shallow trench isolation; 6, gate oxide layer; 7, second gate; 8, isolation oxide layer; 9, side wall; 10, body electrode; 11, source; 12, drain. DETAILED DESCRIPTION

[0027] In order to make the technical solutions and advantages in the embodiments of the present invention more clearly understood, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0028] like Figure 1 As shown, the present invention provides a dual-gate LDMOS device, including a substrate 1, a buried gate layer 2 located on the substrate 1, a P-type body region 3 and an N-type drift region 4 located above the buried gate layer 2, a body electrode 10 and a source electrode 11 located in the P-type body region 3 and on the same side as the buried gate layer 2, a shallow trench isolation 5 located at the top of the N-type drift region 4, a drain electrode 12 located inside the N-type drift region 4, a gate oxide layer 6 located above the P-type body region 3 and the N-type drift region 4, and a second gate electrode 7 located above the gate oxide layer 6; the buried gate layer 2 includes a first oxide layer 2-1, a first gate electrode 2-2 and a second oxide layer 2-3 from bottom to top; and sidewalls 9 are provided at both ends of the second gate electrode 7.

[0029] In this embodiment, the material of the substrate 1 is silicon, and the material of the sidewall spacer 9 is silicon nitride.

[0030] like Figure 2 As shown, in the present invention, the dual-gate LDMOS device is prepared by the following steps:

[0031] See also Figure 2 (a)-(b), doping the silicon substrate 1, and then anisotropically depositing a layer of SiO2 on the silicon substrate 1 to form a first oxide layer 2-1 in the buried gate layer 2;

[0032] See also Figure 2 (c) anisotropically depositing a layer of PolySilicon on the first oxide layer 2-1 to form a first gate 2-2 in the middle of the buried gate layer 2;

[0033] The first oxide layer 2-1 and the first gate 2-2 are photolithographically covered with a layer of photoresist and then the redundant parts are etched away ( Figure 2(d), where the purple part is photoresist), and then anisotropically deposit a layer of SiO2 to form a second oxide layer 2-3 ( Figure 2 (e)), and then the redundant part of the second oxide layer 2-3 is etched away to complete the preparation of the buried gate layer 2 ( Figure 2 (f)-(g));

[0034] See also Figure 2 (h) growing a silicon epitaxial layer on the buried gate layer 2 and performing chemical mechanical polishing to ensure that the silicon surface is highly consistent and has a uniform roughness. Figure 2 (i) shown in the form; then a double diffusion process is used for doping to form an N-type drift region 4 and a P-type body region 3 in the silicon epitaxial layer ( Figure 2 (j));

[0035] See also Figure 2 (k), coating the surface of the silicon epitaxial layer with photoresist, and etching an inverted trapezoidal STI (shallow trench isolation 5) groove in the N-type drift region 4;

[0036] See also Figure 2 (1) Filling the groove with oxide, completing the preparation of STI, and removing the photoresist;

[0037] A gate oxide layer 6 is grown on the surface of the silicon epitaxial layer using a thermal oxidation process. Figure 2 (m)), anisotropically deposit a layer of polysilicon ( Figure 2 (n)), photolithography exposes the part to be etched, and etching the excess polysilicon to form the second gate 7 ( Figure 2 (o)), removing the photoresist;

[0038] An oxide layer ( Figure 2 (p)), and then a layer of silicon nitride ( Figure 2 (q)), anisotropic etching to form sidewall 9 ( Figure 2 (r)), etching the excess oxide layer ( Figure 2 (s)), photolithography exposes the part that needs ion implantation and performs ion implantation to form the body electrode 10, the source electrode 11 and the drain electrode 12 ( Figure 2 (t)), the preparation is completed.

[0039] The position of the buried gate layer of the present invention can be adjusted up and down. Figure 3 An example of a situation where the buried gate layer structure moves upward is given.

[0040] The electrical characteristics of the dual-gate LDMOS device of the present invention were tested, and the results are as follows: Figures 4 to 6 shown; Figure 4 The depletion region images of the structure without buried gate layer and the structure with buried gate layer illustrate that the structure of the present invention can make the depletion region extend more in the N-type drift region, thereby improving the off-state withstand voltage capability; Figure 5 This is a comparison diagram of the breakdown voltages of the two structures, which shows that the structure of the present invention can improve the off-state withstand voltage capability; Figure 6 The output characteristic curves of the two structures and the current density distribution diagram when measuring the on-state current illustrate that the structure of the present invention can generate a channel at the buried gate layer when in the on-state, thereby increasing the current path, so that the on-state current increases at the same voltage, that is, the on-state resistance decreases.

[0041] Obviously, the above described embodiments are only a part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0042] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A dual-gate LDMOS device, characterized in that: It comprises a substrate (1), a buried gate layer (2) located on the substrate (1), and a body region and a drift region located above the buried gate layer (2); the buried gate layer (2) comprises, from bottom to top, a first oxide layer (2-1), a first gate (2-2), and a second oxide layer (2-3); It also includes a body electrode (10) and a source electrode (11) located in the body region, and the body electrode (10) and the source electrode (11) are located on the same side as the buried gate layer (2); a shallow trench isolation (5) located at the top of the drift region, a drain electrode (12) located inside the drift region, a gate oxide layer (6) located above the body region and the drift region, and a second gate electrode (7) located above the gate oxide layer (6); and sidewalls (9) are provided at both ends of the second gate electrode (7).

2. The dual-gate LDMOS device according to claim 1, characterized in that: The sum of the thicknesses of the first oxide layer (2-1) and the second oxide layer (2-3) accounts for 20% to 90% of the total thickness of the buried gate layer (2).

3. The dual-gate LDMOS device according to claim 1, characterized in that: An isolation oxide layer (8) is provided between the second gate (7) and the sidewall (9).

4. The dual-gate LDMOS device according to claim 1, characterized in that: The material of the substrate (1) is silicon.

5. The dual-gate LDMOS device according to claim 1, characterized in that: The material of the side wall (9) is silicon nitride.

6. The dual-gate LDMOS device according to claim 1, characterized in that: The position of the buried gate layer (2) can be adjusted up and down in the dual-gate LDMOS device.

7. The dual-gate LDMOS device according to claim 1, characterized in that: The body region is a P-type body region (3).

8. The dual-gate LDMOS device according to claim 1, characterized in that: The drift region is an N-type drift region (4).

9. A method for preparing the dual-gate LDMOS device according to any one of claims 1 to 8, characterized in that: The following steps are involved: Doping the substrate (1), then forming a first oxide layer (2-1), a first gate (2-2) and a second oxide layer (2-3) on the surface of the substrate (1), thereby completing the preparation of the buried gate layer (2); Growing an epitaxial layer on the buried gate layer (2), and forming a drift region and a body region after doping; A shallow trench isolation (5) is etched on the top of the N-type drift region (4); Growing a gate oxide layer (6) on the surface of the epitaxial layer, and then forming a second gate (7) on the surface of the gate oxide layer (6); An isolation oxide layer (8) and a sidewall (9) are formed on both sides of the second gate (7), and ion implantation is performed to form a body electrode (10), a source electrode (11) and a drain electrode (12).

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