Small-pixel-size infrared detector reading circuit with self-adaptive integrating capacitor

Abstract

The invention relates to a small-pixel-size infrared detector reading circuit with a self-adaptive integrating capacitor, and belongs to the technical field of infrared detector reading circuits. According to the circuit, the NMOS variable capacitor is adopted to replace a traditional capacitor, and the characteristic that the capacitance value of the NMOS variable capacitor is adaptively adjusted along with the change of light intensity is utilized, so that the condition of supersaturation or underexposure of integral charge quantity is effectively avoided, and the dynamic range of the reading circuit is enlarged. Besides, the circuit adopts a folding cascode operational amplifier, good injection efficiency and linearity are guaranteed, the scheme that four pixels share one CTIA structure in a time-sharing mode is adopted, the layout area of the reading circuit is optimized, and the reading circuit can adapt to infrared detectors with smaller pixels and larger arrays. The circuit is simple in structure and easy to realize, has the advantages of low power consumption, wide dynamic range and the like, and is suitable for the design of an intelligent infrared detector reading circuit with high integration, low power consumption and wide dynamic range.

Description

Technical Field

[0001] The invention belongs to the technical field of infrared detector readout circuits, and relates to an infrared detector readout circuit with a small pixel size and adaptive integral capacitance. Background Art

[0002] Infrared image sensing technology has attracted widespread attention due to its advantages such as being unaffected by the environment, good target recognition effect, and strong anti-interference. It was first widely used in the military field. With the rapid growth of civilian demand and the continuous development of infrared physics and technology, infrared detection technology has been widely used in various industries and departments, and has developed into a dual-use technology. In order to meet the needs of future market applications, the infrared detector readout circuit is developing in the direction of high integration, low power consumption, wide dynamic range and intelligence. With the improvement of the integration of the infrared focal plane, the dynamic range of the detector is difficult to improve, and it is difficult to balance the number of noise electrons and the full well charge capacity. Therefore, it is necessary to improve the circuit structure so that the integral capacitor can adapt to the changes in light intensity and increase the dynamic range.

[0003] As one of the commonly used input structures in the infrared detector readout circuit, the CTIA circuit has many advantages: In the CTIA structure, the detector is connected to the input end of the op amp. Since the input impedance of the op amp is very large, the input efficiency drop caused by the input impedance is very small and can be basically ignored; the op amp has the characteristics of virtual short and virtual break. The two ends of the detector are respectively connected to the positive and negative ends of the op amp, and the voltage difference between the two ends is almost 0, so that the voltage at both ends of the detector can be maintained in a stable state; the injection efficiency is related to the gain of the op amp. The greater the gain, the higher the injection efficiency. The injection efficiency can be improved by increasing the gain of the amplifier; due to the Miller effect, the equivalent capacitance of Cint at the input end is (1+A)Cint, where A is the open-loop gain of the op amp. It is realized that when Cint is designed to be small, the equivalent capacitance of the input end can still be large, reducing the input noise of the op amp.

[0004] Highly integrated focal plane arrays require smaller pixel sizes. CTIA structure op amps have many advantages, but they consume more area at the layout level. Sharing one CTIA input stage for multiple pixels can save layout area. The choice of integral capacitors will also affect the layout area. The capacitance per unit area of ​​MIM, MOM and PIP capacitors is very small, and MOS variable capacitors can be a good substitute.

[0005] As an important indicator of the readout circuit, high dynamic range can improve the accuracy of imaging and the sensitivity of the detector; the size of the dynamic range directly represents the range of light intensity changes that can be detected by the infrared image. When the light intensity is weak, the photocurrent detected by the detector is small, and the required integral capacitor is small; when the light intensity is strong, the photocurrent detected by the detector is large, and a too small integral capacitor will cause the integral voltage to be oversaturated and the dynamic range to be reduced. Therefore, it is necessary to design an integral capacitor readout circuit that can adapt to the light intensity. Summary of the invention

[0006] In view of this, an object of the present invention is to provide a small pixel size infrared detector readout circuit with adaptive integral capacitance.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] An integrated capacitance adaptive small pixel size infrared detector readout circuit, the readout circuit comprises an infrared detector, a CTIA input stage circuit, a capacitance switch sampling circuit, a row selection column selection switch, a unit output buffer, a column level buffer and an output buffer;

[0009] The CTIA circuit includes an operational amplifier AMP, a reset switch RET, an NMOS variable capacitor, a detector input current, and a bandgap reference voltage. The anode of the infrared detector, the first terminal of the reset switch, and the source and drain terminals of the NMOS variable capacitor are connected to the inverting input terminal of the operational amplifier; the bandgap reference voltage is connected to the positive input terminal of the operational amplifier; the second terminal of the reset switch RET, the gate of the NMOS variable capacitor, and the first terminal of the sampling switch are connected to the output terminal of the operational amplifier; the output terminal of the operational amplifier is connected to the switch capacitor sampling circuit;

[0010] The switch capacitor sampling circuit is composed of a sampling switch and a sampling capacitor, wherein the sampling capacitor uses an NMOS variable capacitor; the second terminal of the sampling switch and the upper plate of the sampling capacitor are connected to the first terminal of the row selection switch; the second terminal of the row selection switch is connected to the positive input terminal of the unit buffer; the output terminal of the unit output buffer is connected to the positive input terminal of the column buffer; the output terminal of the column buffer is connected to the first terminal of the row selection switch; and the second terminal of the row selection switch is connected to the output buffer.

[0011] The CTIA structure is shared by four pixels, and the inputs of the four pixels are controlled by switches INT1, INT2, INT3, and INT4 respectively. The current signals are sequentially input into the NMOS variable capacitor of the CTIA for integration through timing control.

[0012] NMOS variable capacitor is improved from MOS capacitor. The drain, source and substrate of NMOS variable capacitor are connected together. When the gate voltage changes from negative to positive, the MOS capacitor enters three working states in sequence, namely accumulation, depletion and inversion. The capacitance of NMOS is roughly in the shape of a "V". The capacitance value changes rapidly and does not change monotonically with the gate voltage. NMOS variable capacitor places NMOS in N-well. When the gate voltage is negative, there is no inversion zone. The MOS tube only works in accumulation and depletion states. The capacitance value changes monotonically with the gate voltage and the change curve is smoother.

[0013] The integrated capacitor adaptive small pixel size infrared detector readout circuit designed by the present invention adopts the working mode of integration first and then readout, integrates the input photocurrent signal, converts it into a voltage signal, and then reads it out through the output buffer in sequence to complete the output of a frame of image. The circuit structure is as follows Figure 1 As shown, it includes four modules: integral input, sampling, row selection and column selection control, and buffer output.

[0014] The CTIA input stage circuit comprises four NMOS switches, four detector diodes, a transmission switch, a folded common source and common gate operational amplifier with a PMOS differential pair tube and an NMOS variable capacitor; four pixel input signals are respectively controlled by four control signals INT1, INT2, INT3 and INT4, and the pixels are integrated and read out in turn; the input current signal is connected to the reverse input terminal of the operational amplifier, and the positive input terminal of the operational amplifier is connected to the bandgap reference voltage; after the reset switch RET is turned on, the voltage across the integral capacitor is reset, and after it is turned off, the capacitor is integrated. The integral capacitor here adopts an NMOS variable capacitor. During the integration process, the source and drain voltages of the NMOS variable capacitor are clamped at the bandgap reference voltage, and the gate voltage is the integral voltage. The larger the current, the larger the integral voltage, the larger the voltage difference across the capacitor, and the larger the capacitance value; on the contrary, the smaller the current, the smaller the integral voltage, the smaller the voltage difference across the capacitor, and the smaller the capacitance value, so that the integral capacitor is self-adaptive.

[0015] The switch capacitor sampling circuit includes four sampling switches and four sampling capacitors; the sampling switches are controlled by SH1, SH2, SH3, and SH4 respectively, and the sampling capacitors use NMOS variable capacitors to save layout area; after the SH switch is closed for a period of time, the sampling capacitor completes the sampling of the integrated voltage and enters the row selection and column selection control module.

[0016] The row-select and column-select control modules contain ten transmission gate switches, of which ROW1 controls the first and third pixels, and ROW2 controls the second and fourth pixels. ROW1 represents odd rows, and all first and third pixels are located in odd rows; ROW2 represents even rows, and all second and fourth pixels are located in even rows; the column-select module contains two switches, COL1 controls the first and second pixels, and COL2 controls the third and fourth pixels. COL1 represents odd columns, and all first and second pixels are located on odd columns; COL2 represents even columns, and all third and fourth pixels are located on even columns. In this way, odd-even alternating readout can be achieved, and all first pixels are in odd rows and odd columns; all second pixels are in even rows and odd columns; all third pixels are in odd rows and even columns; all fourth pixels are in even rows and even columns, achieving one-to-one correspondence.

[0017] The output buffer module is composed of an output buffer, wherein the unit gain buffer inside the unit is used to drive the row bus, the column-level unit gain buffer outside the unit is used to drive the column bus, and the output buffer is used to drive the output load.

[0018] The beneficial effects of the present invention are:

[0019] (1) By using NMOS variable capacitors instead of traditional capacitors, the integral capacitance value can be adaptively adjusted as the light intensity changes, effectively avoiding the over-saturation or under-exposure of the integral charge, thereby increasing the dynamic range of the readout circuit.

[0020] (2) The use of a folded common-source common-gate operational amplifier ensures good injection efficiency and linearity, and improves the circuit's sensitivity and imaging quality.

[0021] (3) By using four pixels to share a CTIA structure in a time-sharing manner, the layout area of ​​the readout circuit is optimized, making it adaptable to infrared detectors with smaller pixels and larger arrays, thereby reducing circuit cost and power consumption.

[0022] (4) The integration-first-readout working mode can effectively convert the input photocurrent signal into a voltage signal and realize the sequential output of the signal, thereby improving the output efficiency of the circuit.

[0023] In summary, the present invention realizes a small pixel size infrared detector readout circuit with adaptive integral capacitance by adopting technical means such as NMOS variable capacitors, folded common source and common gate operational amplifiers, four-pixel time-sharing shared CTIA structure, and an integration-first-then-readout working mode. The circuit has the advantages of wide dynamic range, small layout area, high injection efficiency, low power consumption, etc., and provides a new solution for the design of infrared detector readout circuits with high integration, low power consumption, wide dynamic range and intelligence.

[0024] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 It is a structural schematic diagram of a readout circuit of a small pixel size infrared detector with adaptive integral capacitance according to the present invention;

[0027] Figure 2 The NMOS variable capacitor of the present invention and the schematic diagram of the structure and capacitance of the NMOS variable capacitor changing with Vgs;

[0028] Figure 3 It is a schematic diagram of the structure of the folded cascode operational amplifier of the present invention;

[0029] Figure 4 Schematic diagram of integration results of different integration capacitors of the present invention;

[0030] Figure 5 This is a timing diagram of the signal integration and sampling switch operation of the readout circuit of the present invention;

[0031] Figure 6 This is the working timing diagram of the odd and even row selection and column selection switches of the readout circuit of the present invention. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0033] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0034] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the accompanying drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and should not be construed as limitations on the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0035] Reference Figure 1 , which is a schematic structural diagram of a readout circuit for a small pixel size infrared detector with integral capacitance self - adaptation. The circuit uses an NMOS variable capacitor to replace the traditional capacitor and the capacitor - variable CTIA input - stage structure with multiple capacitors in parallel and controlled by switches. At the same time, a structure where four pixels share one CTIA input - stage is adopted, and TG transmission gates are used as switches to achieve time - division integration and readout of the four pixels by controlling the row - selection and column - selection timing.

[0036] The readout circuit to complete the acquisition and output of the input signal is mainly divided into three stages, namely the integration stage, the sampling stage, and the output buffer stage; among them, the integration stage includes four NMOS switches, four detector diodes, one transmission - gate switch, one folded cascode operational amplifier with a PMOS differential pair transistor, and an NMOS variable capacitor; the input signals of the four pixels are respectively controlled by four control signals INT1, INT2, INT3, and INT4 to sequentially integrate and read out the pixel input current signals.

[0037] Reference Figure 2 , which is a schematic diagram for comparing the structure and capacitance value of the NMOS variable capacitor and the NMOS variable capacitor with the change of Vgs. The NMOS variable capacitor sequentially enters three states of accumulation, depletion, and inversion as the gate - source voltage increases as shown in Figure 2 (a); when a reverse voltage is applied to Vgs, a large number of holes appear under the oxide layer, and at this time, the NMOS capacitance value is approximately the gate oxide capacitance Cox; when a positive voltage is applied to Vgs, a depletion region appears under the oxide layer. When Vgs < Vth, the width of the depletion region increases with the increase of Vgs, and at this time, the NMOS capacitance is the series of the gate oxide capacitance and the depletion - region capacitance Cdet, and the capacitance value decreases with the increase of Vgs; when a positive voltage is applied to Vgs and Vgs > Vth, an inversion layer appears, and the capacitance value is approximately the gate oxide capacitance Cox, showing a V - shape on the curve, as shown in Figure 2(b) The NMOS variable capacitor is a variable capacitor whose substrate is changed to N-well. As the gate-source voltage increases, it enters the depletion and accumulation states in sequence. When Vgs is applied with a reverse voltage, since the substrate is N-well and the majority carriers are electrons, a depletion region is formed when a negative voltage is applied to the gate, and the capacitance value is approximately Cox series Cdet; when Vgs is applied with a forward voltage, since the substrate is N-well and the majority carriers are electrons, when the gate is a positive voltage, a large number of electrons gather under the insulating plate to form a channel, and the capacitance value is approximately Cox, such as Figure 2 (c) Compared with NMOS variable capacitors, the capacitance value of NMOS variable capacitors changes monotonically with Vgs and the capacitance value changes more smoothly, such as Figure 2 (d) As shown. Therefore, when the NMOS variable capacitor is used as a sampling capacitor, the voltage of the upper plate of the sampling capacitor is stable above the bandgap reference voltage, and the capacitance value is stable; when the NMOS variable capacitor is used as an integrating capacitor, the capacitance value changes monotonically with Vgs and the capacitance value changes slowly.

[0038] refer to Figure 3 , which is a folded cascode operational amplifier. The use of a folded cascode structure can obtain high gain and thus improve injection efficiency; it can increase the output voltage swing and increase the dynamic range; it can save area. The two-stage operational amplifier requires Miller compensation. The reverse input of the op amp is connected to the input current signal, and the positive input of the op amp is connected to the bandgap reference voltage; after the reset switch RET is turned on, the voltage across the integral capacitor is reset, and after it is turned off, the capacitor is integrated. The integral capacitor here uses an NMOS variable capacitor. A 4um long and 15um wide NMOS variable capacitor has a depletion state capacitance of 665fF and a stacked state capacitance of 2.63pF; a 30um long and 30um wide mim capacitor has a capacitance of 900fF, which is much lower than the unit nominal area capacitance of the NMOS variable capacitor. During the integration process, the source and drain voltages of the NMOS variable capacitor are clamped at the bandgap reference voltage, and the gate voltage is the integral voltage. The larger the current, the larger the integral voltage, the larger the pressure difference across the capacitor, and the larger the capacitance value; on the contrary, the smaller the current, the smaller the integral voltage, the smaller the pressure difference across the capacitor, and the smaller the capacitance value, achieving the integration capacitor self-adaptation.

[0039] refer to Figure 4 , which is the result of integrating the 665fF ideal capacitor, the NMOS variable capacitor and the 2.63pF ideal capacitor. The small capacitor of 0.665 quickly reaches saturation and the integrated voltage no longer increases. The integrated voltage of the NMOS variable capacitor is between 0.665pF and 2.63pF, with excellent linearity and a higher dynamic range than a single capacitor.

[0040] refer to Figure 5, is the input integration stage and sampling stage switch timing diagram, the four pixels are integrated and sampled in turn; the CTIA reset switch RET is first opened to clear the integrated charge at both ends of the NMOS variable capacitor, and then RET is closed, INT1 is turned on, and integration begins. After the integration is completed, INT1 is closed and the sampling switch SH1 is turned on. After the sampling is completed, SH1 is closed, and the integration sampling of the first pixel is completed; the second pixel, the third pixel, and the fourth pixel have the same timing, and the time-sharing multiplexing of the CTIA structure is completed through the RET reset switch.

[0041] refer to Figure 6 , is an odd-even switch timing diagram, the present invention selects the working mode of integration before reading, integration is performed first and then the signal is read in one frame of image; first, the column control switch COL1 is turned on, and the row selection switch ROW1 is turned on at the same time to complete the readout of pixel 1; after ROW1 is turned off, ROW2 is turned on to complete the readout of pixel 2, COL1 and ROW2 are turned off at the same time, and output is completed through the column buffer; then COL2 is turned on, and ROW1 is turned on at the same time to complete the readout of pixel 3; after ROW1 is turned off, ROW2 is turned on to complete the readout of pixel 4, COL2 and ROW2 are turned off at the same time, and output is completed through the column buffer, and the sequential readout of four pixels is completed.

[0042] The integrated voltage, sampling voltage and output voltage waveforms of the entire readout circuit are collected under 200nA, 400nA, 600nA and 800nA photocurrents, with the integration time set to 5us. In this example, the parasitic resistance value of the detector is 500KΩ, the parasitic capacitance value is 1pF, and the power supply voltage is 5V. It can be observed that the voltage is step-shaped and has high linearity, which can well convert the input current signal into a voltage signal.

[0043] The present invention provides an integrated capacitor adaptive small pixel size infrared detector readout circuit, which can realize a capacitor adaptive CTIA structure with a small layout area and a wide dynamic range by replacing the traditional integrated capacitor structure. At the same time, four pixels share one CTIA structure in a time-sharing manner, saving the layout area of ​​the operational amplifier. The problems of too large capacitor layout area, complex switch control timing, insufficient dynamic range, and layout area and injection efficiency are solved, and an infrared detector readout circuit with smaller pixels, larger size, and wider dynamic range can be made.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. An integrated capacitor adaptive small pixel size infrared detector readout circuit, characterized in that: include: Infrared detectors; A CTIA input stage circuit, wherein the CTIA input stage circuit comprises an operational amplifier AMP, a reset switch RET, an NMOS variable capacitor, a detector input current and a bandgap reference voltage, wherein an anode of the infrared detector, a first terminal of the reset switch and a source-drain terminal of the NMOS variable capacitor are connected to an inverting input terminal of the operational amplifier, the bandgap reference voltage is connected to a positive input terminal of the operational amplifier, a second terminal of the reset switch RET, a gate of the NMOS variable capacitor and a first terminal of the sampling switch are connected to an output terminal of the operational amplifier, and an output terminal of the operational amplifier is connected to a switch capacitor sampling circuit; A switch capacitor sampling circuit, wherein the switch capacitor sampling circuit is composed of a sampling switch and a sampling capacitor, wherein the sampling capacitor uses an NMOS variable capacitor, wherein the second terminal of the sampling switch and the upper plate of the sampling capacitor are connected to the first terminal of the row selection switch, wherein the second terminal of the row selection switch is connected to the positive input terminal of the unit buffer, wherein the output terminal of the unit output buffer is connected to the positive input terminal of the column buffer, wherein the output terminal of the column buffer is connected to the first terminal of the row selection switch, and the second terminal of the row selection switch is connected to the output buffer; A row-select column-select switch, the row-select column-select switch is used to control the selection and transmission of the infrared detector signal, and the row-select column-select switch is connected to the CTIA input stage circuit, the switched capacitor sampling circuit, the unit output buffer, the column-level buffer and the output buffer; a unit output buffer connected to the second terminal of the row select switch for driving the row bus; A column level buffer connected to an output terminal of the unit output buffer for driving a column bus; The output buffer is connected to the second terminal of the row selection switch and is used to drive an output load.

2. The small pixel size infrared detector readout circuit with adaptive integral capacitance according to claim 1, characterized in that: The CTIA input stage circuit is shared by four pixels, which are the first pixel, the second pixel, the third pixel and the fourth pixel, respectively controlled by switches INT1, INT2, INT3 and INT4. The current signal is sequentially entered into the NMOS variable capacitor of the CTIA for integration through timing control.

3. The small pixel size infrared detector readout circuit with adaptive integral capacitance according to claim 1, characterized in that: The NMOS variable capacitor places NMOS in an N-well. When the gate voltage is negative, there is no inversion region, and the MOS tube only works in the accumulation and depletion states. The capacitance value changes monotonically with the gate voltage and the change curve is more gentle.

4. The small pixel size infrared detector readout circuit with adaptive integral capacitance according to claim 1, characterized in that: The switch capacitor sampling circuit is composed of four sampling switches and four sampling capacitors, and the sampling capacitors are NMOS variable capacitors.

5. The small pixel size infrared detector readout circuit with adaptive integral capacitance according to claim 1, characterized in that: The row-select and column-select switches include ten transmission gate switches, wherein ROW1 controls the first pixel and the third pixel, and ROW2 controls the second pixel and the fourth pixel.

6. The small pixel size infrared detector readout circuit with adaptive integral capacitance according to claim 1, characterized in that: In the output buffer module, the unit gain buffer inside the unit is used to drive the row bus, the column-level unit gain buffer outside the unit is used to drive the column bus, and the output buffer is used to drive the output load.

7. The small pixel size infrared detector readout circuit according to any one of claims 1 to 6, characterized in that: The working mode of the integrated capacitor adaptive small pixel size infrared detector readout circuit is to integrate first and then read out, and the input photocurrent signal is integrated and then converted into a voltage signal which is then read out in sequence through the output buffer to complete the output of one frame of image.

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