Printed circuit board

Abstract

The present disclosure relates to a printed circuit board comprising: a glass layer; a first wiring layer disposed on an upper surface of the glass layer; the blind holes penetrate into the glass layer from the upper surface of the glass layer and do not extend to the lower surface of the glass layer; and a capacitor including a first electrode layer disposed on the upper surface of the glass layer and extending into each of the plurality of blind holes, a second electrode layer disposed on the first electrode layer and disposed in each of the plurality of blind holes, and a first dielectric layer disposed on the second electrode layer and extending into each of the plurality of blind holes, the first dielectric layer is disposed between the first electrode layer and the second electrode layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0084666 filed on June 30, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Packaging technology continues to develop, specifically, attempts are made to use glass materials to get rid of the use of organic materials in traditional substrate manufacturing methods. In addition, in order to improve power characteristics, recent packaging substrates have adopted the following structure: in this structure, passive components (such as chip capacitors and silicon capacitors) are mounted on the outside of the substrate, or, passive components (such as chip capacitors and silicon capacitors) are embedded after forming a through cavity or a blind cavity in the core of the substrate. However, in this case, it is necessary to add a process for installing or embedding passive components, and it is necessary to form a cavity according to the size of the passive components, which may lead to design limitations. In addition, when multiple passive components are installed, the process difficulty may increase. In addition, when the substrate is thicker, the difficulty of cavity processing or the difficulty of embedding process may increase. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board capable of forming a capacitor having a desired size and capacitance without design limitations.

[0005] Another aspect of the present disclosure is to provide a printed circuit board capable of omitting cavity processing and embedding processes.

[0006] Another aspect of the present disclosure is to provide a printed circuit board having a more excellent effect in terms of dispersion of insulation thickness.

[0007] One of the various solutions proposed through the present disclosure is to form wiring layers, through vias and capacitors directly in the glass core.

[0008] According to one aspect of the present disclosure, a printed circuit board may include: a glass layer; a first wiring layer disposed on an upper surface of the glass layer; a plurality of blind holes respectively penetrating the glass layer from the upper surface of the glass layer and not extending to a lower surface of the glass layer; and a capacitor including a first electrode layer, a second electrode layer, and a first dielectric layer, the first electrode layer being disposed on the upper surface of the glass layer and extending into each of the plurality of blind holes, the second electrode layer being disposed on the first electrode layer and disposed in each of the plurality of blind holes, and the first dielectric layer being disposed between the first electrode layer and the second electrode layer.

[0009] According to another aspect of the present disclosure, a printed circuit board may include: a glass layer; a through hole penetrating the glass layer from an upper surface to a lower surface of the glass layer; a plurality of blind holes penetrating the glass layer from the upper surface of the glass layer and not extending to the lower surface; a first conductor layer disposed on the upper surface and the lower surface of the glass layer and extending to a wall surface of the through hole and a wall surface and a bottom surface of each of the plurality of blind holes; a third conductor layer disposed on the first conductor layer and disposed in the through hole and each of the plurality of blind holes; and a dielectric layer disposed between the first conductor layer and the third conductor layer and located on the upper surface of the glass layer, the wall surface of the through hole, and the wall surface and the bottom surface of each of the plurality of blind holes.

[0010] One of various effects of the present disclosure is to provide a printed circuit board capable of forming a capacitor having a desired size and capacitance without design restrictions.

[0011] Another effect of the present disclosure is to provide a printed circuit board capable of omitting cavity processing and embedding processes.

[0012] Another effect of the present disclosure is to provide a printed circuit board having a more excellent effect in dispersion of insulation thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a block diagram schematically illustrating an example of an electronic device system;

[0015] Figure 2 is a perspective view schematically showing an example of an electronic device;

[0016] Figure 3 is a perspective view schematically showing an example of a printed circuit board;

[0017] Figure 4 It is schematically shown Figure 3 A plan view of a top view of a printed circuit board;

[0018] FIG. 5A to FIG. 5N is a schematic diagram showing the manufacturing Figure 3 A process cross-sectional view of an example of a printed circuit board; and

[0019] Figure 6 is a cross-sectional view schematically showing another example of a printed circuit board. DETAILED DESCRIPTION

[0020] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of elements may be exaggerated or reduced for clarity of description.

[0021] Electronic Devices

[0022] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0023] Reference Figure 1 , the electronic device 1000 accommodates a main board 1010 therein. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also connected to other electronic components to be described below through various signal lines 1090.

[0024] The chip-related components 1020 may include memory chips (such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.), application processor chips (such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.) and logic chips (such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc.). However, the chip-related components 1020 are not limited thereto and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0025] The network-related components 1030 may include components that are compatible with or communicate using the following protocols: wireless local area network (WLAN), wireless fidelity (Wi-Fi) (such as, IEEE 802.11 series), world-wide interoperability for microwave access (WiMAX) (such as, IEEE 802.16 series), IEEE 802.20, long-term evolution (LTE), evolution-data optimized (Ev-DO), enhanced high-speed packet access (HSPA+), enhanced high-speed downlink packet access (HSDPA+), enhanced high-speed uplink packet access (HSUPA+), enhanced data rates for GSM evolution (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), enhanced digital cordless telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols and fifth generation mobile communication technology (5G) protocols, and any other wireless and wired standards or protocols specified hereafter. However, the network-related component 1030 is not limited thereto, and may also include any one of a number of other wireless or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 .

[0026] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components are not limited thereto, and may also include passive components in the form of chip components for various other purposes. In addition, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0027] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. For example, these other electronic components may include a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, but may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, these other electronic components may also be other electronic components for various purposes.

[0028] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet personal computer (tablet PC), a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data other than the above-mentioned electronic devices.

[0029] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0030] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. The mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that may be physically and / or electrically connected to the mainboard 1110 or may not be physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components (e.g., component packages 1121), but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0031] Printed Circuit Board

[0032] Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.

[0033] Figure 4 It is schematically shown Figure 3 A plan view of a printed circuit board from a top view.

[0034] 1. Referring to the drawings, a printed circuit board 100A according to an example embodiment may include a glass layer 110, a first wiring layer 120, a second wiring layer 130, a through via 140, and a capacitor 150, wherein the first wiring layer 120 is disposed on an upper surface of the glass layer 110, the second wiring layer 130 is disposed on a lower surface of the glass layer 110, the through via 140 penetrates the glass layer 110 and connects at least a portion of each of the first wiring layer 120 and the second wiring layer 130, and the capacitor 150 is disposed on the upper surface of the glass layer 110 and penetrates at least a portion of the glass layer 110.

[0035] The first wiring layer 120 may include a first seed layer 121 and a first metal layer 122, the first seed layer 121 being disposed on the upper surface of the glass layer 110, and the first metal layer 122 being disposed on the upper surface of the first seed layer 121. The second wiring layer 130 may include a second seed layer 131 and a second metal layer 132, the second seed layer 131 being disposed on the lower surface of the glass layer 110, and the second metal layer 132 being disposed on the lower surface of the second seed layer 131. A through hole TH penetrating the glass layer 110 from the upper surface to the lower surface may be formed in the printed circuit board 100A, and the through via 140 may include a third seed layer 141, a second dielectric layer 143, a fourth seed layer 145, and a third metal layer 142, the third seed layer 141 being disposed on the wall surface of the through hole TH, the second dielectric layer 143 being disposed on the third seed layer 141, the fourth seed layer 145 being disposed on the second dielectric layer 143, and the third metal layer 142 being disposed on the fourth seed layer 145 and filling the through hole TH. The printed circuit board 100A may include a plurality of blind vias VH, each of which penetrates the glass layer 100 from the upper surface of the glass layer 110 and does not extend to the lower surface of the glass layer 100. The capacitor 150 may include a first electrode layer 151, a second electrode layer 152, and a first dielectric layer 153, the first electrode layer 151 being disposed on the upper surface of the glass layer 110 and extending into each of the plurality of blind vias VH, the second electrode layer 152 being disposed on the first electrode layer 151 and filling each of the plurality of blind vias VH, and the first dielectric layer 153 being disposed between the first electrode layer 151 and the second electrode layer 152. The second electrode layer 152 may include a fifth seed layer 152-1 and a fourth metal layer 152-2, the fifth seed layer 152-1 being disposed on the first dielectric layer 153, and the fourth metal layer 152-2 being disposed on the fifth seed layer 152-1 and filling each of the plurality of blind vias VH. As an example, the fourth metal layer 152 - 2 may be thicker than the fifth seed layer 152 - 1 on the upper surface of the glass layer 110 . As an example, the first electrode layer 151 may contact the glass layer 110 .

[0036] The first seed layer 121, the second seed layer 131 and the third seed layer 141 may include the same metal as the metal of the first electrode layer 151. For example, the first seed layer 121, the second seed layer 131 and the third seed layer 141 and the first electrode layer 151 may be formed by electroless plating (such as chemical copper plating). For example, the first seed layer 121, the second seed layer 131 and the third seed layer 141 and the first electrode layer 151 may constitute the first conductor layer M1. Since the first seed layer 121, the second seed layer 131 and the third seed layer 141 may be formed in a single plating process, there may be no boundary at the connection portion between each of the first seed layer 121 and the second seed layer 131 and the third seed layer 141. That is, the first seed layer 121, the second seed layer 131 and the third seed layer 141 may be formed integrally with each other. The fourth seed layer 145 and the fifth seed layer 152-1 may include the same metal. For example, the fourth seed layer 145 and the fifth seed layer 152-1 may be formed by electroless plating (such as chemical copper plating). The fourth seed layer 145 and the fifth seed layer 152-1 may be formed in a single plating process. For example, the fourth seed layer 145 and the fifth seed layer 152-1 may constitute the second conductor layer M2. As an example, the first conductor layer M1 may contact the glass layer 110.

[0037] The first metal layer 122, the second metal layer 132, the third metal layer 142, and the fourth metal layer 152-2 may include the same metal. For example, the first metal layer 122, the second metal layer 132, the third metal layer 142, and the fourth metal layer 152-2 may be formed by electroplating (such as copper electroplating). For example, the first metal layer 122, the second metal layer 132, the third metal layer 142, and the fourth metal layer 152-2 may constitute the third conductor layer M3. Since the first metal layer 122, the second metal layer 132, and the third metal layer 142 may be formed in two plating processes, there may be a boundary at the connection portion between each of the first metal layer 122 and the second metal layer 132 and the third metal layer 142. For example, the third metal layer 142 and the fourth metal layer 152-2 may constitute a third-first conductor layer M3-1, and the third-first conductor layer M3-1 may be disposed on at least a portion of the first conductor layer M1 and may fill each of the through hole TH and the plurality of blind holes VH. In addition, the first metal layer 122 and the second metal layer 132 may constitute a third-second conductor layer M3-2, and the third-second conductor layer M3-2 may be disposed on at least another portion of the first conductor layer M1 and may cover a portion of the third-first conductor layer M3-1 that fills the through hole TH. The third-first conductor layer M3-1 and the third-second conductor layer M3-2 may have a boundary at their connection portion. Therefore, the third conductor layer M3 may include the third-first conductor layer M3-1 and the third-second conductor layer M3-2. As an example, the third conductor layer M3 may be disposed on the first conductor layer M1 and disposed in each of the through hole TH and the plurality of blind holes VH.

[0038] The first dielectric layer 153 and the second dielectric layer 143 may include the same insulating material. For example, the first dielectric layer 153 and the second dielectric layer 143 may be formed in the same coating process. For example, the first dielectric layer 153 and the second dielectric layer 143 may be formed simultaneously by a single coating process. For example, the dielectric layer D (e.g., as will be described later, such as Figure 5C The first dielectric layer 153 and the second dielectric layer 143 may include a first dielectric layer 153 and a second dielectric layer 143. Therefore, the first dielectric layer 153 and the second dielectric layer 143 may have substantially the same thickness. In addition, as an example, in the case where the first dielectric layer 153 and the second dielectric layer 143 are collectively referred to as a dielectric layer, the dielectric layer may be disposed between the first conductor layer M1 and the third conductor layer M3, and may be located on the upper surface of the glass layer 100, the wall surface of the through hole TH, and the wall surface and the bottom surface of each of the plurality of blind holes VH.

[0039] At least a portion of each of the fourth seed layer 145 and the third metal layer 142 may protrude further upward than each of the third seed layer 141 and the second dielectric layer 143 relative to the upper surface of the glass layer 110. At least another portion of each of the fourth seed layer 145 and the third metal layer 142 may protrude further downward than each of the third seed layer 141 and the second dielectric layer 143 relative to the lower surface of the glass layer 110. The thickness of the further protrusion of each of the fourth seed layer 145 and the third metal layer 142 (i.e., the vertical height of the portion of each of the fourth seed layer 145 and the third metal layer 142 protruding from each of the third seed layer 141 and the second dielectric layer 143) may be substantially the same as the thickness of each of the first dielectric layer 153 and the second dielectric layer 143.

[0040] On the upper surface of the glass layer 110, the thicknesses of the first wiring layer 120, the first electrode layer 151, and the second electrode layer 152 may be different. More specifically, on the upper surface of the glass layer 110, the first wiring layer 120 may be thicker than each of the first electrode layer 151 and the second electrode layer 152, and the second electrode layer 152 may be thicker than the first electrode layer 151. For example, on the upper surface of the glass layer 110, the thickness of the first seed layer 121 may be substantially the same as the thickness of the first electrode layer 151, and the first metal layer 122 may be thicker than the second electrode layer 152. For example, on the upper surface of the glass layer 110, the third-second conductor layer M3-2 may be thicker than the third-first conductor layer M3-1. For example, the upper surface of the first wiring layer 120 may be disposed at a different height from the upper surface of the second electrode layer 152. For example, the upper surface of the first wiring layer 120 may be disposed at a position higher than the upper surface of the second electrode layer 152.

[0041] In the present disclosure, the description "On the Y surface, X1 is thicker than X2" used when comparing the thickness of each part may mean "the thickness of X1 on the Y surface (i.e., the thickness of the part of X1 located on the Y surface) is greater than the thickness of X2 on the Y surface (i.e., the thickness of the part of X2 located on the Y surface)", and similar descriptions in the full text are not repeated.

[0042] At least a portion of the first electrode layer 151 on the upper surface of the glass layer 110 may extend in the horizontal direction so as not to be covered by the second electrode layer 152. For example, at least another portion of the first conductor layer M1 on the upper surface of the glass layer 110 may extend in the horizontal direction so as not to be covered by the third-first conductor layer M3-1. The first electrode layer 151, the second electrode layer 152, and the first dielectric layer 153 may have a step structure on the upper surface of the glass layer 110.

[0043] Since the printed circuit board 100A having this structure includes the glass layer 110 as the core layer, the printed circuit board 100A can have various advantages of using a glass material to get rid of the use of an organic material. In addition, in the case of a substrate including a silicon core layer, even if the substrate has a structure in which a capacitor is embedded, a circuit can be formed only on one side of the substrate structure, and in the case where the capacitor is embedded in the core layer, an insulating material must be added between silicon and metal, and the printed circuit board 100A including a glass core layer according to the example embodiment can form a double-sided circuit (that is, a circuit can be formed on both sides of the printed circuit board 100A), and since glass itself can be used as an insulator, the formation of an additional insulating material can be omitted in the case where the capacitor is embedded in the core layer. That is, the number of layers can be reduced.

[0044] In addition, the printed circuit board 100A having this structure may have a first wiring layer 120, a second wiring layer 130, a through-hole 140 and a capacitor 150 formed directly on the glass layer 110, thereby forming a capacitor of a desired size and capacitance without design restrictions, and more easily forming a microcircuit. In addition, the cavity processing and embedding process for capacitor embedding can be omitted, and in this case, there may be no cavity that occupies a volume asymmetrically when embedded, thereby having a more excellent effect in terms of the dispersion of insulation thickness. In addition, the printed circuit board 100A according to the example embodiment may include a microcircuit and a capacitor, and may be used as a glass interposer mounted and arranged on a flip chip bonding (FCB) substrate or a ball grid array (BGA) substrate, and in this case, a plurality of semiconductor chips may be mounted and arranged on the printed circuit board 100A according to the example embodiment.

[0045] Hereinafter, components of a printed circuit board 100A according to example embodiments will be described in more detail with reference to the accompanying drawings.

[0046] The glass layer 110 may include glass (which is an amorphous solid). For example, the glass may include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, the present disclosure is not limited thereto, and alternative glass materials such as fluorine glass, phosphate glass, chalcogenide glass, etc. may also be used as the material of the glass layer 110. Other additives may also be included to form glass with specific physical properties. These additives may include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony as well as calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda).

[0047] The glass layer 110 may be a layer different from an organic insulating material including glass fiber (glass fabric such as glass cloth) such as copper clad laminate (CCL) and prepreg (PPG). For example, the glass layer 110 may include flat glass. The glass layer 110 may be a core layer. For example, the glass layer 110 may be a glass core.

[0048] The through hole TH may penetrate the glass layer 110 in the thickness direction. For example, the through hole TH may penetrate between the upper surface and the lower surface of the glass layer 110. The through hole TH may have one or more holes. The through hole TH may be in the form of an elliptical column or a circular column, but the present disclosure is not limited thereto, and the through hole TH may be in the form of an hourglass column.

[0049] The blind hole VH may partially penetrate the glass layer 110 in the thickness direction. For example, the blind hole VH may penetrate the glass layer 110 from the upper surface of the glass layer 110 without extending to the lower surface of the glass layer 110. There may be a plurality of blind holes VH. The blind hole VH may be in the form of an elliptical column or a circular column, but is not limited thereto, and may be in the form of an hourglass column, etc. In addition, the edge of the bottom surface of the blind hole VH may be rounded.

[0050] Each of the first wiring layer 120 and the second wiring layer 130 may perform various functions according to the design. For example, the first wiring layer 120 and the second wiring layer 130 may include a signal pattern, a power pattern, and a ground pattern, and each of these patterns may have various forms, such as a line (or trace), a plane (or plate), a pad (or pad). Each of the first wiring layer 120 and the second wiring layer 130 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). If necessary, the first wiring layer 120 and the second wiring layer 130 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer.

[0051] The through via 140 may perform various functions according to the design. For example, the through via 140 may include a ground via, a power via, and a signal via. The through via 140 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). If necessary, the through via 140 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer.

[0052] The capacitor 150 can store capacitance as electric potential energy through the first electrode layer 151, the second electrode layer 152 and the first dielectric layer 153. For example, the capacitor 150 can be used as an electronic device configured to output current by charging a voltage using the characteristics of repeated charging and discharging. Therefore, unstable power can be controlled and noise can be removed. In addition, the capacitor 150 can block direct current and allow alternating current to pass. In addition, the capacitor 150 can be used for stable operation of a semiconductor chip.

[0053] The first seed layer 121, the second seed layer 131, the third seed layer 141, the fourth seed layer 145 and the fifth seed layer 152-1 and the first electrode layer 151 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and may preferably include copper (Cu), but the present disclosure is not limited thereto. The first seed layer 121, the second seed layer 131 and the third seed layer 141 may be an integrated layer without a boundary at the connection portion of each other. Each of the first seed layer 121, the second seed layer 131, the third seed layer 141, the fourth seed layer 145 and the fifth seed layer 152-1 and the first electrode layer 151 may be formed by electroless plating (e.g., chemical copper plating) and / or a sputtering process.

[0054] The first metal layer 122, the second metal layer 132, the third metal layer 142 and the fourth metal layer 152-2 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first metal layer 122, the second metal layer 132, the third metal layer 142 and the fourth metal layer 152-2 may be formed by an electroplating (e.g., copper electroplating) process. Each of the first seed layer 121, the second seed layer 131, the third seed layer 141, the fourth seed layer 145 and the fifth seed layer 152-1 and the first electrode layer 151 may have a thickness thinner than each of the first metal layer 122, the second metal layer 132, the third metal layer 142 and the fourth metal layer 152-2.

[0055] From the perspective of insulation or relative dielectric constant, the first dielectric layer 153 and the second dielectric layer 143 may include at least one of aluminum oxide, silicon dioxide, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate. However, the present disclosure is not limited thereto, and the first dielectric layer 153 and the second dielectric layer 143 may include an organic polymer insulating material.

[0056] FIG. 5A to FIG. 5N is a schematic diagram showing the manufacturing Figure 3 FIG. 1 is a process cross-sectional view of an example of a printed circuit board.

[0057] Reference Figure 5A , a glass layer 110 is prepared, and a through hole TH and a plurality of blind holes VH are formed in the glass layer 110. The through hole TH and the plurality of blind holes VH may be formed in various methods such as laser processing, mechanical processing, and chemical processing.

[0058] Reference Figure 5B The first conductor layer M1 is formed on the upper and lower surfaces of the glass layer 110, the wall surface of the through hole TH, and the wall surface and bottom surface of each of the plurality of blind holes VH. The first conductor layer M1 may be formed by an electroless plating process (e.g., a chemical copper plating process). If necessary, the first conductor layer M1 may be formed by a sputtering process.

[0059] Reference Figure 5C , a dielectric layer D is formed on the first conductor layer M1. The dielectric layer D may be formed in the form of a thin film by a known coating process.

[0060] Reference Figure 5D , a second conductor layer M2 is formed on the dielectric layer D. The second conductor layer M2 may be formed by an electroless plating process (eg, a chemical copper plating process). If necessary, the second conductor layer M2 may be formed by a sputtering process.

[0061] Reference Figure 5E , a third-first conductor layer M3-1 is formed on the second conductor layer M2. The third-first conductor layer M3-1 may fill the through hole TH and the plurality of blind vias VH. The third-first conductor layer M3-1 may be formed by an electroplating process (eg, a copper electroplating process).

[0062] Reference Fig. 5F , a first dry film 210 is formed on a portion of the third-first conductor layer M3-1. The first dry film 210 may be formed by attaching an uncured insulating film and then curing the insulating film, but the present disclosure is not limited thereto, and the first dry film 210 may be formed by a coating process.

[0063] Reference Figure 5G Through the etching process, the portions of the second conductor layer M2 and the third conductor layer M3-1 other than the portions covered by the first dry film 210 may be removed.

[0064] Reference Figure 5H , the exposed portion of the dielectric layer D (i.e., the portion of the dielectric layer D disposed on the upper and lower surfaces of the glass layer 110 and not covered by the first dry film 210) is removed by an etching process, and the first dry film 210 is peeled off. When the exposed portion of the dielectric layer D is removed, the first conductor layer M1 may be exposed.

[0065] Reference Fig.5I, a second dry film 220 and a third dry film 230 having patterned openings for forming a circuit are formed on the upper and lower surfaces of the glass layer 110, respectively. Each of the second dry film 220 and the third dry film 230 may be formed by attaching an uncured insulating film and then curing the insulating film, but the present disclosure is not limited thereto, and each of the second dry film 220 and the third dry film 230 may be formed by a coating process.

[0066] Reference Figure 5J The patterned openings of each of the second dry film 220 and the third dry film 230 are filled by an electroplating process (eg, copper electroplating process), thereby forming a third-second conductor layer M3-2.

[0067] Reference Figure 5K , peel off the second dry film 220 and the third dry film 230 .

[0068] Reference Figure 5L , a fourth dry film 240 is formed on a portion of the first conductor layer M1. The fourth dry film 240 may be formed by attaching an uncured insulating film and then curing the insulating film, but the present disclosure is not limited thereto and the fourth dry film 240 may be formed by a coating process.

[0069] Reference Figure 5M , performing an etching process. Through the etching process, the portion of the first conductor layer M1 other than the portion covered by the fourth dry film 240 may be removed.

[0070] Reference Figure 5N , the fourth dry film 240 is peeled off. Therefore, the first wiring layer 120 and the second wiring layer 130, the through via 140 and the capacitor 150 may be formed, specifically, the first seed layer 121, the second seed layer 131, the third seed layer 141 and the fourth seed layer 145, the first metal layer 122, the second metal layer 132 and the third metal layer 142, the first electrode layer 151 and the second electrode layer 152, and the first dielectric layer 153 and the second dielectric layer 143 may be formed. That is, the printed circuit board 100A according to the above-described example embodiment may be manufactured.

[0071] The other contents are substantially the same as those described in the printed circuit board 100A according to the above exemplary embodiment, and thus a repeated description thereof is omitted.

[0072] Figure 6 is a cross-sectional view schematically showing another example of a printed circuit board.

[0073] Reference Figure 6, a printed circuit board 100B according to another example embodiment may further include buildup layers disposed above and below the printed circuit board 100A according to the above example embodiment. For example, in addition to the printed circuit board 100A according to the above example embodiment, a printed circuit board 100B according to another example embodiment may further include one or more first buildup insulating layers 161, one or more first buildup wiring layers 162, one or more first buildup via layers 163, one or more second buildup insulating layers 171, one or more second buildup wiring layers 172, one or more second buildup via layers 173, a first resist layer 181, and a second resist layer 182, wherein the one or more first buildup insulating layers 161 are disposed on the upper surface of the glass layer 110, and the one or more first buildup wiring layers 162 are disposed on or inside the one or more first buildup insulating layers 161, respectively. , one or more first stacking via layers 163 penetrate one or more first stacking insulating layers 161, respectively, one or more second stacking insulating layers 171 are disposed on the lower surface of the glass layer 110, one or more second stacking wiring layers 172 are disposed on or inside the one or more second stacking insulating layers 171, respectively, one or more second stacking via layers 173 penetrate one or more second stacking insulating layers 171, respectively, a first resist layer 181 is disposed on the first stacking insulating layer 161 disposed on the uppermost side among the one or more first stacking insulating layers 161, and a second resist layer 182 is disposed on the second stacking insulating layer 171 disposed on the lowermost side among the one or more second stacking insulating layers 171. For example, the printed circuit board 100B according to another example embodiment may be a flip chip bonding (FCB) substrate or a ball grid array (BGA) substrate including the glass layer 110 as a core layer.

[0074] Hereinafter, components of a printed circuit board 100B according to another example embodiment will be described in more detail with reference to the accompanying drawings.

[0075] Each of the first stacked insulating layer 161 and the second stacked insulating layer 171 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide), or a material including an inorganic filler, an organic filler and / or glass fiber (such as a glass fabric of a glass cloth) and a thermosetting resin or a thermoplastic resin. For example, the insulating material may be a non-photosensitive insulating material, such as an Ajinomoto build-up film (ABF) or a prepreg (PPG), but the present disclosure is not limited thereto, and other polymer materials may be used as the insulating material. In addition, the insulating material may be a photosensitive insulating material, such as a photosensitive dielectric (PID) resin. One or more first stacked insulating layers 161 and one or more second stacked insulating layers 171 may include substantially the same insulating material, or may include different insulating materials.

[0076] Each of the first buildup wiring layer 162 and the second buildup wiring layer 172 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The first buildup wiring layer 162 and the second buildup wiring layer 172 may preferably include copper (Cu), but the present disclosure is not limited thereto. One or more first buildup wiring layers 162 and one or more second buildup wiring layers 172 may perform various functions according to the design. For example, the first buildup wiring layer 162 and the second buildup wiring layer 172 may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may have various shapes, such as a line, a plane, and a pad. Each of the one or more first buildup wiring layers 162 and the one or more second buildup wiring layers 172 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Optionally, one or more first buildup wiring layers 162 and one or more second buildup wiring layers 172 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Optionally, one or more first buildup wiring layers 162 and one or more second buildup wiring layers 172 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). One or more first buildup wiring layers 162 and one or more second buildup wiring layers 172 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) if desired.

[0077] Each of the one or more first stacked via layers 163 and the one or more second stacked via layers 173 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The first stacked via layer 163 and the second stacked via layer 173 may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first stacked via layer 163 and the second stacked via layer 173 may include a filled via that fills the via hole, but may also include a conformal via disposed along the wall surface of the via hole. The one or more first stacked via layers 163 and the one or more second stacked via layers 173 may perform various functions according to the design. For example, the first stacked via layer 163 and the second stacked via layer 173 may include a ground via, a power via, and a signal via. The first stacked via layer 163 and the second stacked via layer 173 may have a tapered shape tapering in opposite directions in cross section. Each of the one or more first stacked via layers 163 and the one or more second stacked via layers 173 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). The one or more first stacked via layers 163 and the one or more second stacked via layers 173 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) if necessary.

[0078] The first resist layer 181 and the second resist layer 182 may include a liquid solder resist or a film solder resist, but the present disclosure is not limited thereto, and other types of insulating materials may be used as the materials of the first resist layer 181 and the second resist layer 182. The first resist layer 181 and the second resist layer 182 may have a first opening and a second opening for exposing a pattern, respectively. If necessary, a surface treatment layer may be formed on the pattern exposed by the first opening and / or the second opening. Alternatively, a metal bump may be formed on the pattern exposed by the first opening and / or the second opening.

[0079] The other contents are substantially the same as those described in the printed circuit board 100A according to the above exemplary embodiment, and thus a repeated description thereof is omitted.

[0080] In the present disclosure, the depth, thickness, width, and length can be measured based on a cross section obtained by polishing or cutting each printed circuit board by a scanning microscope or an optical microscope. The cut section may be a vertical section or a horizontal section, and each value can be measured based on a desired cut section. If the value is not constant, the value can be determined as the average of the values ​​measured at any five random points.

[0081] In the present disclosure, the expression "covering" may include the case of covering at least a part as well as the case of covering the whole, and may also include the case of direct covering as well as the case of indirect covering. In addition, the expression "filling" may include not only the case of complete filling but also the case of approximate filling, for example, including the case of the presence of some holes or gaps.

[0082] In the present disclosure, "substantially..." may be determined by including process errors or positional deviations occurring in the manufacturing process and errors during measurement. For example, substantially the same line width, gap, thickness, and height may include not only line widths, gaps, thicknesses, and heights that are exactly the same in value, but also line widths, gaps, thicknesses, and heights that have approximately similar values. Furthermore, substantially coplanar may include not only a case where components exist on exactly the same plane, but also a case where components exist on approximately the same plane.

[0083] In the present disclosure, the same insulating material may not only mean the case of completely the same insulating material, but also include the case of the same type of insulating material. Therefore, the composition of the insulating material may be substantially the same, but its specific composition ratio may be slightly different.

[0084] In the present disclosure, "shape on a cross section" may refer to a cross-sectional shape when an object is cut vertically, or a cross-sectional shape when the object is viewed in a side view. In addition, "shape on a plane" may refer to a plane shape when an object is cut horizontally, or a plane shape when the object is viewed in a top view or a bottom view.

[0085] In the present disclosure, the lower side, the lower part, and the lower surface are used to refer to the downward direction relative to the cross section of the drawings, and the upper side, the upper part, and the upper surface are used to refer to the opposite direction. However, this is to define the direction for the convenience of explanation, but the scope of the claims is not specifically limited by the description of such directions, and the concepts of upper and lower can be changed at any time.

[0086] In the present disclosure, "connection" includes concepts of direct connection as well as indirect connection including through an adhesive layer or the like. In addition, "electrical connection" includes concepts of physical connection and non-physical connection. In addition, expressions such as "first" and "second" are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component without departing from the scope of the rights.

[0087] The expression "example embodiments used in the present disclosure" does not mean the same embodiment, and is provided for explaining different unique features. However, the example embodiments presented above do not exclude being implemented in combination with features of other example embodiments. For example, even if matters described in a specific example embodiment are not described in other example embodiments, they can be understood as explanations related to other example embodiments unless there is an opposite or contradictory explanation to matters in other example embodiments.

[0088] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless they are clearly indicated as different in the context, the singular expression includes the plural expression.

[0089] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Glass layer; A first wiring layer, disposed on the upper surface of the glass layer; a plurality of blind holes, respectively penetrating the glass layer from the upper surface of the glass layer and not extending to the lower surface of the glass layer; as well as A capacitor, comprising a first electrode layer, a second electrode layer and a first dielectric layer, wherein the first electrode layer is arranged on the upper surface of the glass layer and extends into each of the plurality of blind holes, the second electrode layer is arranged on the first electrode layer and arranged in each of the plurality of blind holes, and the first dielectric layer is arranged between the first electrode layer and the second electrode layer.

2. The printed circuit board according to claim 1, wherein: On the upper surface of the glass layer, thicknesses of the first wiring layer, the first electrode layer, and the second electrode layer are different from each other.

3. The printed circuit board according to claim 2, wherein: On the upper surface of the glass layer, The first wiring layer is thicker than the second electrode layer, and The second electrode layer is thicker than the first electrode layer.

4. The printed circuit board according to claim 1, wherein: At least a portion of the first electrode layer extends along the upper surface of the glass layer so as not to be covered by the second electrode layer.

5. The printed circuit board according to claim 1, wherein The first wiring layer comprises: A first seed layer disposed on the upper surface of the glass layer; and A first metal layer is disposed on an upper surface of the first seed layer.

6. The printed circuit board according to claim 5, wherein: On the upper surface of the glass layer, The thickness of the first seed layer is the same as the thickness of the first electrode layer, and The first metal layer is thicker than the second electrode layer.

7. The printed circuit board according to claim 5, further comprising: a second wiring layer disposed on the lower surface of the glass layer, The second wiring layer includes a second seed layer and a second metal layer, the second seed layer is disposed on the lower surface of the glass layer, and the second metal layer is disposed on the lower surface of the second seed layer.

8. The printed circuit board according to claim 7, further comprising: a through via that penetrates the glass layer and connects at least a portion of the first wiring layer and at least a portion of the second wiring layer to each other, The printed circuit board has a through hole formed therein that penetrates the glass layer from the upper surface to the lower surface of the glass layer, and The through via includes: a third seed layer, a second dielectric layer, a fourth seed layer and a third metal layer, the third seed layer is arranged on the wall surface of the through hole, the second dielectric layer is arranged on the third seed layer, the fourth seed layer is arranged on the second dielectric layer, and the third metal layer is arranged on the fourth seed layer and in the through hole.

9. The printed circuit board according to claim 8, wherein: The first dielectric layer and the second dielectric layer include the same insulating material.

10. The printed circuit board according to claim 8, wherein There is no boundary at a connection portion between each of the first seed layer and the second seed layer and the third seed layer, and A boundary exists at a connection portion between each of the first metal layer and the second metal layer and the third metal layer.

11. The printed circuit board according to claim 8, wherein: At least a portion of each of the fourth seed layer and the third metal layer protrudes further upward than each of the third seed layer and the second dielectric layer relative to the upper surface of the glass layer, and With respect to the lower surface of the glass layer, at least another portion of each of the fourth seed layer and the third metal layer protrudes further downward than each of the third seed layer and the second dielectric layer.

12. The printed circuit board according to claim 11, wherein The further protrusion thickness of the at least one portion and the at least another portion of each of the fourth seed layer and the third metal layer is the same as the thickness of each of the first dielectric layer and the second dielectric layer.

13. The printed circuit board according to claim 8, further comprising: One or more first build-up insulating layers disposed on the upper surface of the glass layer; One or more first build-up wiring layers, respectively disposed on or inside the one or more first build-up insulating layers; One or more first stacked via layers, respectively penetrating the one or more first stacked insulating layers; One or more second build-up insulating layers disposed on the lower surface of the glass layer; One or more second build-up wiring layers, respectively disposed on or inside the one or more second build-up insulating layers; One or more second stacked via layers, respectively penetrating the one or more second stacked insulating layers; a first resist layer disposed on a first stacked insulating layer disposed on an uppermost side among the one or more first stacked insulating layers; as well as A second resist layer is disposed on a second stacked insulating layer disposed on a lowermost side among the one or more second stacked insulating layers.

14. The printed circuit board according to claim 1, wherein: The second electrode layer comprises: a fifth seed layer, disposed on the first dielectric layer; and a fourth metal layer disposed on the fifth seed layer and disposed in each of the plurality of blind holes, and On the upper surface of the glass layer, the fourth metal layer is thicker than the fifth seed layer.

15. The printed circuit board according to claim 1, wherein The glass layer includes flat glass.

16. The printed circuit board according to claim 1, wherein An upper surface of the first wiring layer and an upper surface of the second electrode layer are arranged at different heights.

17. The printed circuit board according to claim 1, wherein: The first electrode layer contacts the glass layer.

18. A printed circuit board, comprising: Glass layer; a through hole penetrating the glass layer from the upper surface to the lower surface of the glass layer; a plurality of blind holes, respectively penetrating the glass layer from the upper surface of the glass layer and not extending to the lower surface; a first conductor layer disposed on the upper surface and the lower surface of the glass layer and extending to the wall surface of the through hole and the wall surface and the bottom surface of each of the plurality of blind holes; a third conductor layer disposed on the first conductor layer and disposed in the through hole and each of the plurality of blind holes; as well as A dielectric layer is disposed between the first conductor layer and the third conductor layer and is located on the upper surface of the glass layer, the wall surface of the through hole, and the wall surface and the bottom surface of each of the plurality of blind holes.

19. The printed circuit board according to claim 18, wherein The third conductor layer comprises: A third-first conductor layer disposed on at least a portion of the first conductor layer and disposed in the through hole and each of the plurality of blind holes; and a third-second conductor layer disposed on at least another portion of the first conductor layer and covering a portion of the third-first conductor layer disposed in the through hole, and On the upper surface of the glass layer, the third-second conductor layer is thicker than the third-first conductor layer.

20. The printed circuit board according to claim 19, wherein At least another portion of the first conductor layer extends along the upper surface of the glass layer so as not to be covered by the third-first conductor layer.

21. The printed circuit board according to claim 19, further comprising: The second conductor layer is arranged between the dielectric layer and the third-first conductor layer.

22. The printed circuit board according to claim 18, wherein The first conductor layer is in contact with the glass layer.

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