Manufacturing method of SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory
By forming a 1.5T type memory cell structure in SONOS memory, the problem of large leakage in GIDL in the 2T structure is solved, device performance improvement and size reduction are achieved, manufacturing process is simplified, production capacity is increased and costs are reduced.
Patent Information
- Application Number
- CN202411622738.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2024-12-31
AI Technical Summary
The 2T structure of the existing SONOS NOR memory has a large source and drain interval spacing between the selection tube and the storage tube, resulting in large leakage of GIDL of the selection tube, which affects device performance and causes disturbance failure. The manufacturing process is complex and it is difficult to achieve miniaturization. .
Using the control gate structure on the semiconductor substrate and the select gate structure is formed on its side, the 1.5T type memory cell structure is formed through unblocked etching and heavily doped self-alignment technology to ensure that there is no overlap between the drain region and the select gate structure. , thereby reducing GIDL leakage and simplifying the process flow.
It effectively reduces GIDL leakage in SONOS memory, improves device performance, realizes memory size miniaturization, simplifies manufacturing processes, improves production capacity and reduces costs.
Smart Images
Figure CN119233639A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a SONOS memory. Background Art
[0002] The existing conventional SONOS NOR memory is generally a 2T structure. The storage unit of the 2T structure includes two transistors, namely, a storage tube and a selection tube. The storage tube includes a control gate (CG) and a source region and a drain region formed on both sides of the control gate by self-alignment. The selection tube includes a selection gate (SG) and a source region and a drain region formed on both sides of the selection gate by self-alignment. Both CG and SG use polysilicon gates and directly form the graphic structures of CG and SG through exposure and etching using a mask. The spacing (space) between CG and SG is large, which is not conducive to further miniaturization. Moreover, since the source region (source) and drain region (drain) of the storage tube and the selection tube of the existing 2T structure storage unit will be ion implanted (IMP), when the SONOS device is operated, due to the injection of IMP into the drain end of the selection tube, the gate induced drain leakage current (GIDL) of the selection tube is relatively large, which will seriously affect the SONOS device and cause disturbance failure, thereby resulting in low wafer test (CP).
[0003] like Figure 1 , which is a schematic diagram of the device structure of an existing SONOS memory; Figure 1 The structure shown is a structure of a memory cell, where a select gate structure 102 and a control gate structure 103 are formed on a semiconductor substrate 101, the select gate structure 102 includes a gate dielectric layer 104 and a select gate polysilicon layer 105 stacked in sequence; the control gate structure 103 includes an ONO layer 106 and a control gate polysilicon layer 107. The ONO layer 106 includes an oxide layer 106a, a nitride layer 106b and an oxide layer 106c stacked in sequence, the oxide layer 106a serves as a tunneling layer, the nitride layer 106b serves as a storage layer, and the oxide layer 106c serves as a control layer.
[0004] The selection tube is composed of a selection gate structure 102 and N+ regions 108a and 108b on both sides. The N+ region 108a serves as a source region of the selection tube, and the N+ region 108b serves as a drain region of the selection tube.
[0005] The storage tube is composed of a control gate structure 103 and N+ regions 108b and 108c on both sides, wherein the N+ region 108b is used as the source region of the storage tube and the N+ region 108c is used as the drain region of the storage tube. The N+ region 108b is also used as the drain region of the selection tube and the source region of the storage tube.
[0006] As can be seen from the dotted circle 109, the N+ region 108b overlaps with the select gate structure 102, thereby causing the GIDL leakage of the device to be relatively large.
[0007] GIDL leakage is very important in SONOS devices. The mechanism of GIDL generation of SG, i.e., the selector, is as follows: Figure 1 As shown, the pressure applied at each end of the 2T-type SONOS structure in the inhibit state is as follows:
[0008] A high voltage, such as 7.5V, is applied to the control gate polysilicon layer 107, so that the CG transistor, i.e., the storage transistor, is in an open state.
[0009] The drain region of the storage tube, namely the N+ region 108c, will also be added with a high voltage such as 4.2V. At the same time, since the storage tube is in an open state, the high voltage of the N+ region 108c will be transmitted to the N+ region 108b, so the drain region of the selection tube, namely the N+ region 108b, will also be added with a high voltage.
[0010] Due to the high voltage applied to the N+ region 108b, the overlapping area between the gate and drain of the selection tube corresponding to the dotted circle 109 will cause the separation of electrons and holes in the depletion region, and the electrons will flow to the drain area of the storage tube, thereby causing the inhibit disturb to fail. Summary of the invention
[0011] The technical problem to be solved by the present invention is to provide a method for manufacturing a SONOS memory, which can reduce the GIDL leakage of the device, and the process manufacturing flow is simple and easy to control, thereby achieving the goal of increasing production capacity and reducing costs, and further miniaturizing the size of the device.
[0012] In order to solve the above technical problems, the manufacturing method of the SONOS memory provided by the present invention comprises the following steps:
[0013] A control gate structure is formed on a semiconductor substrate, and a hard mask layer is formed on a top surface of the control gate structure.
[0014] A first spacer is formed on the side of the control gate structure.
[0015] A selection gate dielectric layer is formed and a selection gate conductive material layer is deposited in sequence.
[0016] Blanket etching is performed on the selection gate conductive material layer so that the selection gate conductive material layer is only retained on the side of the control gate structure; the highest position of the top surface of the retained selection gate conductive material layer is flush with the top surface of the hard mask layer.
[0017] The selection gate conductive material layer retained at the first side of the control gate structure is removed, and a selection gate structure is formed by stacking the selection gate conductive material layer retained at the second side of the control gate structure and the selection gate dielectric layer at the bottom, wherein the first side of the selection gate structure and the second side of the control gate structure are separated by the first side wall.
[0018] A source region and a drain region are formed by self-alignment of heavily doped source and drain implantation of a first conductivity type; the source region and the second side of the select gate structure are self-aligned, the drain region and the side of the first side wall at the first side of the control gate structure are self-aligned, the drain region and the select gate structure have no overlap, and thus the GIDL leakage of the device is reduced.
[0019] A further improvement is that the material of the semiconductor substrate includes silicon.
[0020] A further improvement is that the material of the selection gate conductive material layer includes polysilicon.
[0021] A further improvement is that the material of the selection gate dielectric layer includes silicon oxide.
[0022] A further improvement is that the control gate structure includes a first ONO layer and a control gate conductive material layer stacked in sequence.
[0023] A further improvement is that the material of the control gate conductive material layer includes polysilicon.
[0024] Further improvements include:
[0025] The hard mask layer is removed.
[0026] Metal silicide is formed on the top surface of the control gate conductive material layer and the top surface of the select gate conductive material layer.
[0027] A further improvement is that the hard mask layer includes a first silicon oxide layer and a second silicon nitride layer stacked in sequence.
[0028] A further improvement is that two adjacent control gate structures form a gate combination structure.
[0029] In the gate combination structure, the first side surfaces of the two control gate structures are adjacent to each other; after the deposition of the selection gate conductive material layer is completed, the selection gate conductive material layer completely fills the spacing area between the first side surfaces of the two control gate structures in the gate combination structure.
[0030] A further improvement is that the material of the first sidewall spacer includes silicon oxide, silicon nitride, or silicon oxynitride.
[0031] The present invention forms a patterned control gate structure by selection, and then forms a selection gate structure at the second side of the control gate structure by deposition plus barrier-free etching self-alignment, the selection gate conductive material layer at the first side of the control gate structure is removed, and then source and drain injection is performed to form a source region and a drain region, the drain region is self-aligned with the first side of the control gate, so there is a gap between the drain region and the first side of the selection gate structure, so the drain region and the selection gate structure do not overlap, thereby reducing the GIDL leakage of the device; in the present invention, the selection gate structure is self-aligned and formed on the side of the control gate structure and constitutes a storage unit structure of a SONOS memory, the storage unit structure is a 1.5T structure, so the GIDL leakage of each storage unit structure of the present invention is reduced, and the total GIDL leakage of the entire SONOS memory is also reduced.
[0032] In the present invention, the selection gate structure does not need to be additionally defined by a photolithography process, and can be realized by only a deposition process plus a barrier-free etching process. Therefore, the process manufacturing flow is simple and easy to control, and ultimately the production capacity can be improved and the cost can be reduced.
[0033] In the present invention, since the selection gate structure is self-aligned and formed on the side of the control gate structure, the distance between the selection gate structure and the control gate structure can be minimized, so the size of the storage cell structure can be reduced and the size of the entire memory can be reduced. Therefore, the present invention can further shrink the size of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0035] Figure 1 It is a schematic diagram of the device structure of the existing SONOS memory;
[0036] Figure 2 is a flow chart of a method for manufacturing a SONOS memory according to an embodiment of the present invention;
[0037] Figure 3A-Figure 3F It is a schematic diagram of the device structure in each step of the manufacturing method of the SONOS memory according to an embodiment of the present invention. DETAILED DESCRIPTION
[0038] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing a SONOS memory according to an embodiment of the present invention; FIG. 3A to FIG. 3F FIG. 1 is a schematic diagram of the device structure in each step of the method for manufacturing a SONOS memory according to an embodiment of the present invention. The method for manufacturing a SONOS memory according to an embodiment of the present invention comprises the following steps:
[0039] Step S101: Figure 3BAs shown, a control gate structure 301 is formed on a semiconductor substrate 201 , and a hard mask layer is formed on the top surface of the control gate structure 301 .
[0040] In the embodiment of the present invention, the material of the semiconductor substrate 201 includes silicon.
[0041] The control gate structure 301 includes a first ONO layer 202 and a control gate conductive material layer 203 stacked in sequence. The first ONO layer 202 is formed by stacking an oxide layer (O), a nitride layer (N) and an oxide layer (O), wherein the oxide layer at the bottom of the first ONO layer 202 is used as a tunneling layer, the middle nitride layer is used as a storage layer, and the top oxide layer is used as a control layer.
[0042] The material of the control gate conductive material layer 203 includes polysilicon.
[0043] The hard mask layer includes a first silicon oxide layer 204 and a second silicon nitride layer 205 stacked in sequence.
[0044] The control gate structure 301 is formed by deposition and patterning etching, and the steps include:
[0045] like Figure 3A As shown, a first ONO layer 202 , a control gate conductive material layer 203 , a first silicon oxide layer 204 and a second silicon nitride layer 205 are sequentially formed on the surface of the semiconductor substrate 201 .
[0046] like Figure 3B As shown, photolithography definition is performed, and the second silicon nitride layer 205 and the first silicon oxide layer 204 are first etched, that is, the hard mask layer is patterned and etched.
[0047] Afterwards, the control gate conductive material layer 203 and the first ONO layer 202 at the bottom are etched using the hard mask layer as a mask, thereby forming a control gate structure 301 .
[0048] In the embodiment of the present invention, two adjacent control gate structures 301 form a gate combination structure.
[0049] In the gate assembly structure, first side surfaces of two control gate structures 301 are adjacent to each other.
[0050] Step S102: Figure 3C As shown, a first spacer 206 is formed on the side of the control gate structure 301 .
[0051] In the embodiment of the present invention, the material of the first spacer 206 includes silicon oxide, silicon nitride, or silicon oxynitride.
[0052] Step S103: Figure 3CAs shown, a select gate dielectric layer 207 is formed and a select gate conductive material layer 208 is deposited in sequence.
[0053] In the embodiment of the present invention, the material of the select gate conductive material layer 208 includes polysilicon.
[0054] The material of the select gate dielectric layer 207 includes silicon oxide.
[0055] After the deposition of the selection gate conductive material layer 208 is completed, the selection gate conductive material layer 208 completely fills the spacer between the first side surfaces of the two control gate structures 301 in the gate assembly structure.
[0056] Step S104: Figure 3D As shown, the selection gate conductive material layer 208 is etched without blocking so that the selection gate conductive material layer 208 is only retained on the side of the control gate structure 301; the highest position of the top surface of the retained selection gate conductive material layer 208 is flush with the top surface of the hard mask layer.
[0057] Step S105: Figure 3E As shown, the selection gate conductive material layer 208 retained at the first side of the control gate structure 301 is removed, and the selection gate conductive material layer 208 retained at the second side of the control gate structure 301 and the selection gate dielectric layer 207 at the bottom are stacked to form a selection gate structure 302, and the first side of the selection gate structure 302 and the second side of the control gate structure 301 are separated by the first side wall 206.
[0058] Step S106: Figure 3E As shown, a source region (not shown) and a drain region (not shown) are formed by self-alignment of heavily doped source and drain implantation of the first conductive type, and both the source region and the drain region are formed in the semiconductor substrate 201; the source region and the second side of the selection gate structure 302 are self-aligned, the drain region and the side of the first side wall 206 at the first side of the control gate structure 301 are self-aligned, the drain region and the selection gate structure 302 have no overlap, and thus the GIDL leakage of the device is reduced.
[0059] Also includes:
[0060] like Figure 3F As shown, the hard mask layer is removed.
[0061] A metal silicide 209 is formed on the top surface of the control gate conductive material layer 203 and the top surface of the select gate conductive material layer 208 .
[0062] In the embodiment of the present invention, a patterned control gate structure 301 is formed by selection, and then a selection gate structure 302 is formed at the second side of the control gate structure 301 by self-alignment by deposition plus barrier-free etching. The selection gate conductive material layer 208 at the first side of the control gate structure 301 is removed, and then source and drain implantation is performed to form a source region and a drain region. The drain region is self-aligned with the first side of the control gate, so there is a gap between the drain region and the first side of the selection gate structure 302. Therefore, the drain region and the selection gate structure 302 do not overlap, thereby reducing the GIDL leakage of the device. In the embodiment of the present invention, the selection gate structure 302 is self-aligned and formed on the side of the control gate structure 301 and constitutes a storage unit structure of the SONOS memory. The storage unit structure is a 1.5T structure. Therefore, the GIDL leakage of each storage unit structure in the embodiment of the present invention is reduced, and the total GIDL leakage of the entire SONOS memory is also reduced.
[0063] In the embodiment of the present invention, the select gate structure 302 does not need to be additionally defined by a photolithography process, and can be realized by only a deposition process plus a barrier-free etching process. Therefore, the process manufacturing flow is simple and easy to control, and ultimately the production capacity can be improved and the cost can be reduced.
[0064] In the embodiment of the present invention, since the selection gate structure 302 is self-aligned and formed on the side of the control gate structure 301, the distance between the selection gate structure 302 and the control gate structure 301 can be minimized, so the size of the storage cell structure can be reduced and the size of the entire memory can be reduced. Therefore, the embodiment of the present invention can also further shrink the size of the device.
[0065] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing a SONOS memory, characterized in that: The steps include: forming a control gate structure on a semiconductor substrate, wherein a hard mask layer is formed on a top surface of the control gate structure; forming a first spacer on a side of the control gate structure; sequentially forming a select gate dielectric layer and depositing a select gate conductive material layer; Performing non-blocking etching on the selection gate conductive material layer so that the selection gate conductive material layer is only retained on the side of the control gate structure; the highest position of the top surface of the retained selection gate conductive material layer is flush with the top surface of the hard mask layer; The select gate conductive material layer retained at the first side of the control gate structure is removed, and the select gate conductive material layer retained at the second side of the control gate structure and the select gate dielectric layer at the bottom are stacked to form a select gate structure, wherein the first side of the select gate structure and the second side of the control gate structure are separated by the first sidewall spacer; A source region and a drain region are formed by self-alignment of heavily doped source and drain implantation of a first conductivity type; the source region and the second side of the select gate structure are self-aligned, the drain region and the side of the first side wall at the first side of the control gate structure are self-aligned, the drain region and the select gate structure have no overlap, and thus the GIDL leakage of the device is reduced.
2. The method for manufacturing a SONOS memory according to claim 1, wherein: The material of the semiconductor substrate includes silicon.
3. The method for manufacturing a SONOS memory according to claim 2, wherein: The material of the selection gate conductive material layer includes polysilicon.
4. The method for manufacturing a SONOS memory according to claim 3, wherein: The material of the select gate dielectric layer includes silicon oxide.
5. The method for manufacturing a SONOS memory according to claim 3, wherein: The control gate structure includes a first ONO layer and a control gate conductive material layer stacked in sequence.
6. The method for manufacturing a SONOS memory according to claim 5, wherein: The material of the control gate conductive material layer includes polysilicon.
7. The method for manufacturing a SONOS memory according to claim 6, wherein: Also includes: removing the hard mask layer; Metal silicide is formed on the top surface of the control gate conductive material layer and the top surface of the select gate conductive material layer.
8. The method for manufacturing a SONOS memory according to claim 1, wherein: The hard mask layer includes a first silicon oxide layer and a second silicon nitride layer stacked in sequence.
9. The method for manufacturing a SONOS memory device according to claim 1, wherein: Two adjacent control gate structures form a gate combination structure; In the gate combination structure, the first side surfaces of the two control gate structures are adjacent to each other; after the deposition of the selection gate conductive material layer is completed, the selection gate conductive material layer completely fills the spacing area between the first side surfaces of the two control gate structures in the gate combination structure.
10. The method for manufacturing a SONOS memory according to claim 1, wherein: The material of the first spacer includes silicon oxide, silicon nitride or silicon oxynitride.
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