Layout layout method and structure of unit cell structure driving tube

Abstract

The invention discloses a layout method for a unit cell structure driving tube, and the method comprises the steps: S1, determining the contact type and size of a substrate / well according to LAYOUT DRC RULE and transistor pattern layer information; s2, according to LAYOUT DRC RULE, transistor pattern layer information and substrate / well contact type information, determining a through hole type and a side length of a contact hole; s3, according to the LAYOUT DRC RULE, the unit cell structure driving tube and the substrate / well contact size information, creating a transistor array unit and an array; s4, creating a PICKUP RING contact unit according to the array unit, the substrate / well contact type and the contact size information; and S5, according to the through hole type and side length information of the contact hole, creating a contact through hole on the PICKUP RING contact unit. The invention further discloses a layout structure of the unit cell structure driving tube. The layout structure comprises an array unit, a PICKUP RING contact unit and a contact through hole. According to the invention, the parasitic resistance of the substrate / well of the transistor is effectively reduced, and the latch-up resistance of the unit cell structure driving tube is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor layout design, and in particular to a layout method and structure of a cell structure driving transistor. Background Art

[0002] In the CMOS (Complementary Metal Oxide Semiconductor) process, latch-up effect is one of the parasitic effects that need to be avoided in actual design. The principle of latch-up prevention for CMOS transistors is to ensure good substrate / well contact. The conventional operation method is to add substrate / well contact to CMOS transistors, and connect the N / P type to the power supply / ground. Adding substrate / well contact close to the CMOS transistor can make the parasitic resistance of the substrate / well relatively small, thereby better avoiding the latch-up effect.

[0003] Normally, adding substrate contacts according to design rules can effectively avoid the latch-up effect, but in some cases, even adding substrate / well contacts cannot prevent the circuit from entering the latch-up state. For example, for the large-size driver tube layout required by the design, in order to save area, the substrate / well contacts are usually designed only at the outermost periphery of the cell structure driver tube. When the longitudinal and lateral distances between the center area of ​​the driver tube and the substrate / well are large, the generated substrate / well parasitic resistance will also be relatively large. According to the principle of the latch-up effect, a larger substrate / well resistance will make the circuit more prone to latch-up and enter the latch-up state, thus failing to meet higher anti-latch-up requirements. Summary of the invention

[0004] The present invention provides a layout method and structure of a cell structure driving tube that effectively improves the anti-latch performance of the cell structure driving tube, which can solve at least one of the above technical problems.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A layout method for a cell structure driving tube comprises the following steps:

[0007] S1. Determine the contact type and contact size of the substrate / well according to the LAYOUT DRC RULE and transistor layer information;

[0008] S2. Determine the through hole type and through hole side length of the contact hole according to LAYOUT DRC RULE, transistor layer information and substrate / well contact type information;

[0009] S3, creating array units and arrays of transistors according to LAYOUT DRC RULE, cell structure driver tube and substrate / well contact size information;

[0010] S4, creating a PICKUP RING contact unit according to the array unit, substrate / well contact type and contact size information, wherein the PICKUP RING contact unit is arranged between adjacent array units in the array;

[0011] S5. Create a contact through hole on the PICKUP RING contact unit according to the through hole type and through hole side length information of the contact hole in S2.

[0012] Furthermore, the S1 further comprises:

[0013] S11, according to the transistor layer information, determine that the BASE port of the N-type transistor is connected to the substrate layer, and the BASE port of the P-type transistor is connected to the well layer;

[0014] S12, determining the substrate / well contact type according to the connection relationship in S11 and the type information of the transistor;

[0015] S13. Determine the substrate / well contact size according to the substrate / well contact type and LAYOUT DRC RULE.

[0016] Furthermore, in S1, the transistor layer information is used to determine the relationship between various layers, and the transistor layer information at least includes a layer number and a layer position.

[0017] Furthermore, the S2 further comprises:

[0018] S21, determining, according to substrate / well contact type information, that the power port layer is connected to the well layer, and the ground port layer is connected to the substrate layer;

[0019] S22, determining the through hole type of the contact hole according to the connection relationship in S11;

[0020] S23. Determine the side length of the contact hole according to the through hole type and LAYOUT DRC RULE of the contact hole.

[0021] Furthermore, in S3, the array unit needs to be determined according to the specific size of the cell structure driving tube and the array layout selected in the actual layout, further comprising:

[0022] S31, determining the side length L of the array unit according to LAYOUT DRC RULE;

[0023] S32, obtaining a determined square area according to the side length L of the array unit obtained in S31, and placing a transistor unit with a maximum size of W in the square area;

[0024] S33. Create an array layout based on the transistor unit in S32 as a basic unit.

[0025] Furthermore, the S4 further comprises:

[0026] S41, according to the contact type and contact size information of the substrate / well, the N-type transistor creates a P-type PICKUP RING contact unit, and the P-type transistor creates an N-type PICKUP RING contact unit;

[0027] S42. According to the array unit system, the PICKUP RING contact unit is placed on the gap between two adjacent array units in the array.

[0028] Furthermore, the S5 further comprises:

[0029] S51, according to the through hole type information of the contact hole in S2, determine that the power port layer is connected to the N-type PICKUP RING contact unit, and the N-type PICKUP RING contact unit is connected to the well through hole, and the ground port layer is connected to the P-type PICKUP RING contact unit, and the P-type PICKUP RING contact unit is connected to the substrate through hole;

[0030] S52, determining the number of the contact through holes placed on each of the PICKUP RING contact units according to the through hole side length information of the contact holes in S2;

[0031] S53 . Create contact through holes on the PICKUP RING contact unit according to the number of the contact through holes and the LAYOUT DRC RULE.

[0032] Furthermore, in S5, before creating the contact through-holes on the PICKUP RING contact unit, the number of the contact through-holes is determined according to the area of ​​the PICKUP RING contact unit.

[0033] Further, in S5, when the contact through-holes are created on the PICKUP RING contact unit, it is prohibited to set any of the contact through-holes on the four corner regions of any of the PICKUP RING contact units.

[0034] A layout structure of a cell structure driving tube, applicable to a layout method of the cell structure driving tube, comprising:

[0035] An array, wherein the array comprises a plurality of array units uniformly distributed in a matrix structure, wherein the array units are transistor units;

[0036] A PICKUP RING contact unit, wherein the PICKUP RING contact unit is a ring-shaped substrate / well contact layer, each side of which is equally wide, and is fitted to surround the outer side of the array unit, and is fitted to be embedded in the gap between two adjacent array units;

[0037] There are a plurality of contact through holes, which are spaced and distributed on each side of the PICKUP RING contact unit.

[0038] The beneficial effects of the present invention are embodied in:

[0039] 1. In the present invention, the distribution form of the transistor array determines the array distribution of the substrate / well contact, and the existing entire large-size transistor only has one PICKUP RING to achieve the substrate / well contact. Therefore, the implementation method of the present invention enables the cell structure driver transistor to have a better substrate / well contact, thereby reducing the transistor substrate / well parasitic resistance, and further improving the anti-latch performance of the cell structure driver transistor.

[0040] 2. In the present invention, since the internal structure of the transistor is not modified, it has good versatility and can be applied to transistors of different processes and types. At the same time, the present invention is based on the existing layout process, so it has good adaptability and can be gradually embedded in the existing layout process, with little impact on the progress of layout design. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0042] Figure 1 It is a schematic diagram of the overall process of the layout method of the embodiment of the present invention.

[0043] Figure 2 It is a schematic diagram of the array unit distribution of the layout structure of an embodiment of the present invention.

[0044] Figure 3 It is a schematic diagram of creating a PICKUP RING contact unit according to a layout structure of an embodiment of the present invention.

[0045] Figure 4 It is a schematic diagram of creating contact holes according to the layout structure of an embodiment of the present invention.

[0046] The components in the drawings are marked as follows: 201, array unit; 202, PICKUP RING contact unit; 203, contact through hole. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. In the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0048] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, outside, inside...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the meaning of "and / or" appearing in the full text includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or schemes that satisfy both A and B. In addition, "multiple" refers to more than two. In addition, in the present invention, LAYOUT DRCRULE means: layout design rules, and PICKUP RING means: substrate contact ring.

[0049] See also Figure 1 The embodiment of the present invention provides a layout method of a cell structure driving tube, comprising the following steps:

[0050] S1. Determine the contact type and contact size of the substrate / well according to the LAYOUT DRC RULE and transistor layer information;

[0051] S2. Determine the through hole type and through hole side length of the contact hole according to LAYOUT DRC RULE, transistor layer information and substrate / well contact type information;

[0052] S3, creating an array unit 201 and an array of transistors according to the LAYOUT DRC RULE, the cell structure driver tube and the substrate / well contact size information;

[0053] S4, creating a PICKUP RING contact unit 202 according to the array unit 201, substrate / well contact type and contact size information, wherein the PICKUP RING contact unit 202 is arranged between adjacent array units 201 in the array;

[0054] S5. Create a contact through hole 203 on the PICKUP RING contact unit 202 according to the through hole type and through hole side length information of the contact hole in S2.

[0055] In the present invention, the distribution form of the transistor array determines the array distribution of the substrate / well contact, and the existing entire large-size transistor only has one PICKUP RING to achieve substrate / well contact. Therefore, the implementation method of the present invention enables the cell structure driver transistor to have a better substrate / well contact, thereby reducing the transistor substrate / well parasitic resistance, and further improving the anti-latch performance of the cell structure driver transistor.

[0056] In this embodiment, the S1 further includes:

[0057] S11, according to the transistor layer information, determine that the BASE port of the N-type transistor is connected to the substrate layer, and the BASE port of the P-type transistor is connected to the well layer;

[0058] S12, determining the substrate / well contact type according to the connection relationship in S11 and the type information of the transistor;

[0059] Specifically, the substrate layer connected to the N-type transistor is a P-type substrate layer, and the well layer connected to the P-type transistor is an N-type well layer;

[0060] S13. Determine the substrate / well contact size according to the substrate / well contact type and LAYOUT DRC RULE.

[0061] Specifically, the minimum area and width and length of the substrate / well contact are specified in the LAYOUT DRC RULE. Therefore, it can be determined whether to use the substrate / well of the minimum size based on actual conditions. Selecting the substrate / well of the minimum size can achieve higher area utilization.

[0062] In this embodiment, in S1, the transistor layer information is used to determine the relationship between various layers, and the transistor layer information at least includes a layer number and a layer position.

[0063] For example, for an N-type transistor, it can be determined that its BASE port is connected to the ground port, the layer number corresponding to the ground port is GND, and the layer position corresponding to the ground port can be described as a list of coordinates of each corner of the layer; for a P-type transistor, it can be determined that its BASE port is connected to the power port, the layer number corresponding to the power port is VDD, and the layer position corresponding to the power port can be described as a list of coordinates of each corner of the layer. Each layer can be determined according to the layer number, and then the relationship between the layers can be determined according to the layer position of each layer. After determining the relationship between each layer, the type of substrate / well contact can be determined according to the relationship between each layer, such as an N-type transistor is connected to a P-type substrate contact, and a P-type transistor is connected to an N-type well contact. Since the minimum area and width and length of the substrate / well contact are specified in the LAYOUT DRC RULE, the specific size of the substrate / well contact can be determined according to the LAYOUT DRC RULE.

[0064] It should be noted that the transistor layer information may also include layer style, layer color, etc., which is not limited in detail in the embodiment of the present invention and can be set according to actual conditions.

[0065] In this embodiment, the S2 further includes:

[0066] S21, determining, according to substrate / well contact type information, that the power port layer is connected to the well layer, and the ground port layer is connected to the substrate layer;

[0067] S22, determining the through hole type of the contact hole according to the connection relationship in S11;

[0068] For example, an N-type transistor is connected to a P-type substrate contact, and a substrate contact via is used to connect a P-type substrate layer; a P-type transistor is connected to an N-type well contact, and a well contact via is used to connect an N-type well layer;

[0069] S23. Determine the side length of the contact hole according to the through hole type and LAYOUT DRC RULE of the contact hole.

[0070] Specifically, the minimum spacing between the contact hole and other layers and the minimum OVERLAP size are specified in the LAYOUT DRC RULE, and the specific size of the contact hole can be determined according to the LAYOUT DRC RULE. For example, the minimum substrate / well contact size is selected in S1, and the contact hole determined in S2 can only be the minimum size.

[0071] See also Figure 2 In this embodiment, in S3, the array unit 201 needs to be determined according to the specific size of the cell structure driving tube and the array layout selected in the actual layout, further including:

[0072] S31, determining the side length L of the array unit 201 according to LAYOUT DRC RULE;

[0073] Specifically, different process LAYOUT DRC RULEs have a maximum value S for the maximum distance between the center of the transistor and the substrate / well contact. The side length L of the array unit 201 can be determined based on the maximum value S. Generally, L=1.5S can be selected.

[0074] S32, obtaining a determined square area according to the side length L of the array unit 201 obtained in S31, and placing a transistor unit with a maximum size of W in the square area;

[0075] Specifically, the total size of the cell structure driving tube can be divided by the transistor unit size W;

[0076] S33. Create an array layout based on the transistor unit in S32 as a basic unit.

[0077] Specifically, the transistor unit in S32 is the array unit 201. Since substrate / well contacts need to be embedded between the array units 201, and LAYOUT DRC RULE specifies the minimum spacing Sa between the transistor unit and the substrate / well contact, the minimum spacing value of each array unit 201 is the substrate / well contact size in S1 plus twice Sa.

[0078] After determining the spacing of the array units 201, the specific array layout is determined according to the array layout mode to be formed by the design, for example, a 2X 2, 3X 3 or 4X 8 array layout to be created, such as Figure 2 As shown, this embodiment adopts a 2X 2 layout.

[0079] See also Figure 2-Figure 3 In this embodiment, S4 further includes:

[0080] S41, according to the contact type and contact size information of the substrate / well, the N-type transistor creates a P-type PICKUP RING contact unit, and the P-type transistor creates an N-type PICKUP RING contact unit;

[0081] S42, according to the arrangement of the array units 201, the PICKUP RING contact unit 202 is placed on the gap between two adjacent array units 201 in the array.

[0082] In this embodiment, Figure 2The array layout in is based on the specific size of the substrate / well contact in S1 and the LAYOUT DRC RULE to determine the spacing of the array unit 201, so the PICKUP RING contact unit 202 in S3 can be directly created according to the substrate / well contact size selected in S1.

[0083] Specifically, the PICKUP RING contact unit 202 is a ring-shaped substrate / well contact layer, such as Figure 3 As shown, since the present embodiment adopts a 2X 2 array layout, it can be determined that four PICKUP RING contact units 202 need to be added in the present embodiment.

[0084] See also Figure 2-Figure 4 In this embodiment, S5 further includes:

[0085] S51, according to the through hole type information of the contact hole in S2, determine that the power port layer is connected to the N-type PICKUP RING contact unit, and the N-type PICKUP RING contact unit is connected to the well through hole, and the ground port layer is connected to the P-type PICKUP RING contact unit, and the P-type PICKUP RING contact unit is connected to the substrate through hole;

[0086] S52, determining the number of the contact through holes 203 placed on each of the PICKUP RING contact units 202 according to the through hole side length information of the contact holes in S2;

[0087] S53 , creating contact through holes 203 on the PICKUP RING contact unit 202 according to the number of the contact through holes 203 and the LAYOUT DRC RULE.

[0088] For example, a substrate contact via is created on a P-type substrate layer, and a well contact via is created on an N-type well layer. The size of the contact via 203 is determined according to the side length of the contact hole in S2, and the spacing of the contact via 203 is determined by LAYOUT DRC RULE.

[0089] See also Figure 2-Figure 4 In this embodiment, in S5 , before creating the contact through-holes 203 on the PICKUP RING contact unit 202 , the number of the contact through-holes 203 is determined according to the area of ​​the PICKUP RING contact unit 202 .

[0090] Specifically, when the pick-up ring contact unit 202 has a large area, multiple rows of contact holes 203 may be created. It should be noted that the number of the contact holes 203 is not specifically limited in the embodiment of the present invention and may be set according to actual conditions.

[0091] See also Figure 2-Figure 4 In this embodiment, in S5 , when the contact through hole 203 is created on the PICKUP RING contact unit 202 , it is prohibited to set any of the contact through holes 203 on the four corner areas of any of the PICKUP RING contact units 202 .

[0092] See also Figure 2-Figure 4 The embodiment of the present invention further provides a layout structure of a cell structure driving tube, which is applicable to a layout method of the cell structure driving tube, including:

[0093] An array, wherein the array comprises a plurality of array units 201 uniformly distributed in a matrix structure, wherein the array units 201 are transistor units;

[0094] The PICKUP RING contact unit 202 is a ring-shaped substrate / well contact layer, each side of which is equally wide, and is fitted around the outer side of the array unit 201 and is embedded in the gap between two adjacent array units 201;

[0095] There are a plurality of contact through holes 203 , which are spaced apart and distributed on each side of the PICKUP RING contact unit 202 .

[0096] It should be noted that in the above embodiment of the layout method, the settings of various components, such as the contact type and size of the transistor (N-type / P-type transistor) and the substrate / well, the spacing of the array unit 201, the type and size of the contact through hole 203 connected to the PICKUP RING contact unit 202 (N-type / P-type), etc., have been clearly described in detail, so they are not elaborated in the embodiment of this layout structure. For specific settings, please refer to the above embodiment part.

[0097] To sum up, in the present invention, firstly, the contact type and size of the substrate / well and the through-hole type and side length of the contact hole are determined according to the LAYOUT DRC RULE and the transistor layer information, so that the transistor array unit and the array can be created according to the LAYOUT DRC RULE, the cell driver tube and the contact size information of the substrate / well, and then the PICKUP RING contact unit is added between the array units, and finally, the contact through-hole is created on the PICKUP RING contact unit according to the type and side length information of the contact hole.

[0098] Since the distribution form of the transistor array in the present invention determines the array distribution of the substrate / well contact, and the existing entire large-size transistor only uses one PICKUP RING to achieve substrate / well contact, the implementation method of the embodiment of the present invention enables the cell structure driver transistor to have a better substrate / well contact, thereby reducing the transistor substrate / well parasitic resistance, and further improving the anti-latch performance of the cell structure driver transistor.

[0099] Furthermore, since the embodiment of the present invention does not modify the internal structure of the transistor, it has good versatility and can be applied to transistors of different processes and types; at the same time, the embodiment of the present invention is based on the existing layout process, so it has good adaptability and can be gradually embedded in the existing layout process, with little impact on the progress of layout design.

[0100] It should be understood that the examples and implementation modes described herein are for illustrative purposes only and are not intended to limit the present invention. Those skilled in the art may make various modifications or changes based on the examples and implementation modes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A layout method for a cell structure driving tube, characterized in that: The following steps are involved: S1. Determine the contact type and contact size of the substrate / well according to the LAYOUT DRC RULE and transistor layer information; S2. Determine the through hole type and through hole side length of the contact hole according to LAYOUT DRC RULE, transistor layer information and substrate / well contact type information; S3, creating an array unit (201) and an array of transistors according to the LAYOUT DRC RULE, the cell structure drive tube and the substrate / well contact size information; S4, creating a PICKUP RING contact unit (202) according to the array unit (201), substrate / well contact type and contact size information, wherein the PICKUP RING contact unit (202) is arranged between adjacent array units (201) in the array; S5. Create a contact through hole (203) on the PICKUP RING contact unit (202) according to the through hole type and through hole side length information of the contact hole in S2.

2. The layout method of the cell structure driving tube according to claim 1, characterized in that: The S1 further comprises: S11, according to the transistor layer information, determine that the BASE port of the N-type transistor is connected to the substrate layer, and the BASE port of the P-type transistor is connected to the well layer; S12, determining the substrate / well contact type according to the connection relationship in S11 and the type information of the transistor; S13. Determine the substrate / well contact size according to the substrate / well contact type and LAYOUT DRC RULE.

3. The layout method of the cell structure driving tube according to claim 1, characterized in that: In S1, the transistor layer information is used to determine the relationship between various layers, and the transistor layer information at least includes a layer number and a layer position.

4. The layout method of the unit cell structure driving tube according to claim 2, characterized in that: The S2 further comprises: S21, determining, according to substrate / well contact type information, that the power port layer is connected to the well layer, and the ground port layer is connected to the substrate layer; S22, determining the through hole type of the contact hole according to the connection relationship in S11; S23. Determine the side length of the contact hole according to the through hole type and LAYOUT DRC RULE of the contact hole.

5. The layout method of the cell structure driving tube according to claim 1, characterized in that: In S3, the array unit (201) needs to be determined according to the specific size of the unit cell structure driving tube and the array layout selected in the actual layout, further comprising: S31, determining the side length L of the array unit (201) according to LAYOUT DRC RULE; S32, obtaining a certain square area according to the side length L of the array unit (201) obtained in S31, and placing a transistor unit with a maximum size of W in the square area; S33, creating an array layout based on the transistor unit in S32 as a basic unit.

6. The layout method of the cell structure driving tube according to claim 1, characterized in that: The S4 further comprises: S41, according to the contact type and contact size information of the substrate / well, the N-type transistor creates a P-type PICKUP RING contact unit, and the P-type transistor creates an N-type PICKUP RING contact unit; S42: According to the arrangement of the array units (201), the PICKUP RING contact unit (202) is placed on the gap between two adjacent array units (201) in the array.

7. The layout method of the cell structure driving tube according to claim 6, characterized in that: The S5 further comprises: S51, according to the through hole type information of the contact hole in S2, determine that the power port layer is connected to the N-type PICKUP RING contact unit, and the N-type PICKUP RING contact unit is connected to the well through hole, and the ground port layer is connected to the P-type PICKUP RING contact unit, and the P-type PICKUP RING contact unit is connected to the substrate through hole; S52, determining the number of the contact through holes (203) placed on each of the PICKUP RING contact units (202) according to the through hole side length information of the contact holes in S2; S53: Create contact through holes (203) on the PICKUP RING contact unit (202) according to the number of the contact through holes (203) and the LAYOUT DRC RULE.

8. The layout method of the cell structure driving tube according to claim 1, characterized in that: In the step S5, before creating the contact through-holes (203) on the PICKUP RING contact unit (202), the number of the contact through-holes (203) is determined according to the area of ​​the PICKUP RING contact unit (202).

9. The layout method of the cell structure driving tube according to claim 1, characterized in that: In the step S5, when the contact through hole (203) is created on the PICKUP RING contact unit (202), it is prohibited to set any of the contact through holes (203) on the four corner regions of any of the PICKUP RING contact units (202).

10. A layout structure of a cell structure driving tube, applicable to the layout method of a cell structure driving tube as claimed in any one of claims 1 to 9, characterized in that: include: An array, the array comprising a plurality of array units (201) uniformly distributed in a matrix structure, the array units (201) being transistor units; A PICKUP RING contact unit (202), the PICKUP RING contact unit (202) is a ring-shaped substrate / well contact layer, each side of which is equally wide, and is fitted around the outer side of the array unit (201), and is fitted into the gap between two adjacent array units (201); A plurality of contact through holes (203) are provided, and are distributed at intervals on each side of the PICKUP RING contact unit (202).

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