Cleavage method

Abstract

The invention belongs to the technical field of semiconductors, and provides a cleavage method, which adopts non-mechanical means such as etching, corrosion and the like to avoid the action of mechanical stress on a slice wafer, thereby greatly reducing the possibility of cracks on the end face of the slice wafer. Specifically, the cleavage method is implemented according to the following steps: growing silicon oxide on the back surface of a thin wafer to form a mask layer; coating photoresist on the surface of one side, deviating from the sheet wafer, of the mask layer to form a second glue layer; photoetching the second adhesive layer to construct a second cleavage region which is overlapped with the first cleavage region on the front surface of the thin wafer; removing silicon oxide on the mask layer relative to the position of the second cleavage region; coating at least two layers of photoresist on the front surface of the thin wafer to form a first adhesive layer; photoetching the first adhesive layer, and displaying a first cleavage area through a developing step; performing dry etching on the front surface of the sheet wafer; and performing wet etching on the back surface of the sheet wafer.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a cleavage method. Background Art

[0002] In the field of semiconductor chip manufacturing, wafer cleavage is a key step in dividing the wafer into individual chips. With the rapid development of electronic technology, the performance and reliability requirements of chips are getting higher and higher. The traditional cleavage method is mainly mechanical cleavage, which has been widely used in the industry.

[0003] In the early development of the semiconductor industry, mechanical cleavage became a more common choice due to the limitations of technology and equipment. Mechanical cleavage usually uses mechanical tools such as diamond blades to cut wafers. The principle is to separate the wafers by sliding the tool across the surface of the wafer at a certain pressure and speed. This method has certain advantages, such as relatively simple equipment and low cost, and is more suitable for some thicker wafers or in specific production environments.

[0004] However, with the continuous advancement of chip technology, the disadvantages of mechanical cleavage have become increasingly prominent. During the mechanical cleavage process, large mechanical stress is easily generated. When this stress acts on the wafer, especially the thin wafer, it often causes cracks on the end face of the thin wafer. Once cracks appear on the end face of the thin wafer, it will have many adverse effects on the performance of the chip. Among them, the most significant is the deterioration of heat dissipation on the end face of the chip. During the operation of the chip, good heat dissipation performance is one of the key factors to ensure stable operation of the chip and extend its service life. When cracks appear on the end face, the heat dissipation channel is damaged and the heat cannot be effectively dissipated, which will cause the temperature inside the chip to rise. Excessive temperature will affect the performance of the electronic components inside the chip, reduce the working efficiency of the chip, and may even cause chip failure, which greatly affects the reliability of the product. Therefore, finding a better thin wafer cleavage method to avoid the generation of end face cracks and improve the heat dissipation performance of the chip and the reliability of the product has become an urgent problem to be solved in the current semiconductor industry. Summary of the invention

[0005] Therefore, the technical problem to be solved by the present application is to provide a cleavage method to overcome the problem that traditional mechanical cleavage methods are prone to cracks during the cleavage process of thin wafers, resulting in poor chip heat dissipation performance and reduced product reliability.

[0006] In order to solve the above problems, the present application provides a cleavage method, comprising:

[0007] Growing silicon oxide on the back of the thin wafer to form a mask layer;

[0008] Coating photoresist on the surface of the mask layer facing away from the thin wafer to form a second adhesive layer;

[0009] Photolithography is performed on the second adhesive layer to construct a second cleavage region that overlaps with the first cleavage region on the front side of the thin wafer;

[0010] removing silicon oxide at a position on the mask layer relative to the second cleavage region;

[0011] Coating at least two layers of photoresist on the front side of the thin wafer to form a first photoresist layer;

[0012] Photolithography is performed on the first glue layer, and a first cleavage region is displayed through a development step;

[0013] Dry etching of the front side of the thin wafer;

[0014] Wet etching of the back side of the thin wafer.

[0015] Optionally, the step of removing silicon oxide at a position on the mask layer relative to the second cleavage region includes:

[0016] Place the wafer in the BOE solution.

[0017] Optionally, the step of dry etching the front side of the thin wafer comprises:

[0018] Place the wafer in the plasma etching machine.

[0019] Optionally, the step of wet etching the back side of the thin wafer includes:

[0020] Placing the wafer in a mixed solution of hydrochloric acid and phosphoric acid;

[0021] Among them, the volume ratio of hydrochloric acid to phosphoric acid is 2:3.

[0022] Optionally, before the step of growing silicon oxide on the back side of the thin wafer to form a mask layer, the cleavage method further comprises:

[0023] forming a first dissociation zone on the front side of the wafer;

[0024] The wafer is prepared into a thin wafer by thinning.

[0025] Optionally, the thickness of the thin wafer is 100um to 140um.

[0026] Optionally, the dry etching depth of the front side of the thin wafer is 10um to 20um.

[0027] Optionally, the wet etching time of the back side of the thin wafer is 15 minutes to 20 minutes.

[0028] Optionally, the thickness of the mask layer is

[0029] Optionally, the thickness of at least two layers of photoresist coated on the front side of the thin wafer is 2 um to 3 um.

[0030] Beneficial Effects

[0031] The cleavage method provided in the embodiment of the present invention adopts non-mechanical means such as etching and corrosion to avoid the effect of mechanical stress on the thin wafer, thereby greatly reducing the possibility of cracks on the end surface of the thin wafer. As a result, the end surface heat dissipation channel of the chip can be kept intact, the heat dissipation performance is guaranteed, the heat can be effectively dissipated, the internal temperature of the chip is reduced, the working efficiency of the chip is improved, the service life of the chip is extended, and the risk of chip failure due to excessive temperature is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A flowchart of a cleavage method according to an optional embodiment of the present application;

[0033] Figure 2 This is a schematic diagram of the structure of placing a thin wafer in a mixed solution of hydrochloric acid and phosphoric acid according to an optional embodiment of the present application.

[0034] The reference numerals are:

[0035] 1. Thin wafer; 2. Mask layer; 3. First adhesive layer. DETAILED DESCRIPTION

[0036] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0038] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0040] See also Figure 1 and Figure 2 As shown, according to the embodiment of the present application, a cleavage method is provided, which adopts non-mechanical means such as etching and corrosion to avoid the effect of mechanical stress on the thin wafer 1, thereby greatly reducing the possibility of cracks on the end face of the thin wafer 1. As a result, the end face heat dissipation channel of the chip can be kept intact, the heat dissipation performance is guaranteed, the heat can be effectively dissipated, the internal temperature of the chip is reduced, the working efficiency of the chip is improved, the service life of the chip is extended, and the risk of chip failure due to excessive temperature is reduced.

[0041] Please follow the steps below to implement:

[0042] Step S101 : growing silicon oxide on the back side of the thin wafer 1 to form a mask layer 2 .

[0043] The thin wafer 1 is a wafer that has been processed specifically and is usually thinner to meet the needs of specific chip manufacturing. The back side is relative to the front side (the side where key manufacturing steps such as chip circuits are usually performed).

[0044] The growth of silicon oxide is to deposit a layer of silicon oxide material on the back of the thin wafer 1 by specific chemical vapor deposition (CVD) or other suitable process methods. Silicon oxide (SiO2) is a commonly used material in semiconductor manufacturing and has many excellent properties.

[0045] Specifically, this layer of silicon oxide will play a role similar to a "protective film" and a "positioning template" in the subsequent manufacturing process. As a protective film, it can prevent the back of the thin wafer 1 from unnecessary chemical corrosion or physical damage in the subsequent process steps. For example, in the subsequent wet etching step, if there is no mask layer 2, the back of the thin wafer 1 may be accidentally corroded, affecting the performance and quality of the chip. At the same time, as a positioning template, it can provide accurate positioning references for subsequent lithography and other steps. During the lithography process, precise exposure and development are required on the thin wafer 1 according to a pre-designed cleavage pattern. The silicon oxide on the mask layer 2 can be matched with the cleavage area on the front through a specific photoresist and exposure process to ensure the accuracy and consistency of the cleavage area. In this embodiment, the thickness of the mask layer 2 is It can provide good protection for the back of the thin wafer 1 in the subsequent process. It is neither too thin to effectively prevent chemical corrosion and physical damage, nor too thick to affect the subsequent processing steps. For example, in the wet etching process, the mask layer 2 in this thickness range can prevent the etching liquid from excessively corroding the back of the thin wafer 1, ensuring that the chip performance and quality are not affected.

[0046] Step S102: coating photoresist on a surface of the mask layer 2 facing away from the thin wafer 1 to form a second adhesive layer.

[0047] The mask layer 2 is a silicon oxide layer grown on the back side of the thin wafer 1 in step S101 , and it provides protection and positioning for subsequent process steps.

[0048] The outer surface of the mask layer 2, that is, the side opposite to the thin wafer 1, is coated with photoresist. Photoresist is a material that can undergo chemical or physical changes under certain conditions and is usually used in photolithography to achieve pattern transfer and definition.

[0049] Specifically, step S102 is to form a second glue layer by coating a photoresist on the surface of the mask layer 2 facing away from the thin wafer 1, which provides a pattern bearing basis and process control means for the subsequent cleavage process. It can be understood that in the photolithography step, by exposing and developing the second glue layer, a second cleavage area pattern that coincides with the first cleavage area on the front side of the thin wafer 1 can be formed on the photoresist. This pattern will serve as a guide for subsequent processes, used to remove silicon oxide at corresponding positions on the mask layer 2, and to perform cleavage operations on the thin wafer 1. In other words, the second glue layer formed in step S102 provides a medium for constructing a second cleavage area that coincides with the first cleavage area on the front side of the thin wafer 1, so that the pattern transfer and definition of the cleavage area can be performed accurately later.

[0050] Step S103 : photolithography on the second adhesive layer to construct a second cleavage region that overlaps with the first cleavage region on the front side of the thin wafer 1 .

[0051] The second glue layer is a photoresist layer coated on the outer surface of the mask layer 2 in step S102 , and has the characteristic of being sensitive to light of a specific wavelength.

[0052] Among them, photolithography is a precise pattern transfer technology. It uses specific photolithography equipment to project a pre-designed pattern corresponding to the first cleavage area on the front side of the thin wafer 1 onto the second glue layer by exposure. During the exposure process, light of a specific wavelength passes through a mask with a pattern (also called a photomask) and irradiates the photoresist, causing chemical changes in the photoresist. By controlling parameters such as exposure time, intensity, and wavelength, a specific pattern can be accurately formed on the second glue layer. This pattern is the second cleavage area to be constructed.

[0053] Specifically, the second cleavage area formed on the second adhesive layer completely corresponds in position and shape to the first cleavage area already existing on the front side of the thin wafer 1. This ensures that the subsequent cleavage operation can be accurately performed along the predetermined path, thereby achieving accurate cleavage of the thin wafer 1 and ensuring the quality and performance of the chip. It is understandable that in the subsequent steps of removing silicon oxide and etching, corrosion, etc., the second cleavage area can serve as a clear mark to guide the process. This helps to avoid misoperation and improve the efficiency and reliability of the process.

[0054] Step S104: removing silicon oxide on the mask layer 2 at a position corresponding to the second cleavage region.

[0055] It can be understood that, based on the above steps, a mask layer 2 (silicon oxide layer) has been formed on the back side of the thin wafer 1, and a second glue layer has been formed on the surface of the mask layer 2 facing away from the thin wafer 1, and a second cleavage area that overlaps with the first cleavage area on the front side of the thin wafer 1 is constructed on the second glue layer through photolithography.

[0056] The silicon oxide at the position of the mask layer 2 corresponding to the second cleavage region is removed, that is, the mask layer 2 is selectively removed locally. Specifically, the silicon oxide at the corresponding position in the mask layer 2 is accurately removed according to the position of the second cleavage region.

[0057] Specifically, it can be achieved through a specific chemical etching method. For example, the thin wafer 1 can be placed in a specific chemical solution that can selectively corrode silicon oxide while having little effect on the photoresist and other parts of the thin wafer 1. In this process, the parameters such as the etching time, temperature and solution concentration must be strictly controlled to ensure that only the silicon oxide at the predetermined position is removed without causing excessive corrosion to the surrounding area. It should be noted that after the silicon oxide at these positions is removed, a channel is opened for subsequent process steps. In the subsequent process, whether it is dry etching the front side of the thin wafer 1 or wet etching the back side of the thin wafer 1, the thin wafer 1 can be accurately acted on through these areas where the silicon oxide is removed to achieve accurate cleavage of the thin wafer 1.

[0058] Step S105 : coating at least two layers of photoresist on the front side of the thin wafer 1 to form a first photoresist layer 3 .

[0059] The coating of at least two layers of photoresist on the front side of the thin wafer 1 can be performed by spin coating.

[0060] Specifically, two or more layers of photoresist materials can be sequentially coated on the front of the thin wafer 1. On the one hand, multi-layer photoresist can provide better protection. In the subsequent process, the front of the thin wafer 1 may be affected by corrosion of various chemical substances, mechanical forces, and high-energy radiation. The multi-layer photoresist can serve as a solid barrier to reduce the damage of these adverse factors to the thin wafer 1; on the other hand, the multi-layer photoresist can improve the precision and accuracy of cleavage. Different layers of photoresist can play different roles in the photolithography process. For example, the bottom layer of photoresist can provide better adhesion and stability, and the upper layer of photoresist can be used to accurately define the pattern of the cleavage area. Through the synergistic effect of the multi-layer photoresist, the size and shape of the cleavage area can be more accurately controlled to ensure the high quality of the cleavage process.

[0061] It should be noted that, in the present embodiment, the thickness of at least two layers of photoresist is 2um to 3um. The multilayer photoresist in this thickness range can provide effective protection for the front side of the thin wafer 1 in the subsequent process to prevent it from being corroded by chemical substances, mechanical forces, and high-energy radiation. For example, during the etching and corrosion process, the thicker photoresist layer can prevent the etching gas and the corrosive liquid from damaging the key parts such as the front circuit structure of the wafer. At the same time, it helps to accurately control the cleavage area, better define the cleavage pattern, and improve the precision and accuracy of the cleavage area.

[0062] Step S106: photolithography is performed on the first glue layer 3, and a development step is performed to reveal the first cleavage region.

[0063] Among them, photolithography on the first glue layer 3 is used to form a specific pattern on the first glue layer 3. It can be understood that by performing patterning operation on the first glue layer 3 through photolithography, the designed cleavage pattern can be accurately transferred to the first glue layer 3. This makes the boundary of the cleavage area clearer and more accurate, which helps to achieve precise cleavage operation and improve the quality and performance of the chip.

[0064] Specifically, a specific mask plate can be placed above the first adhesive layer 3, and the mask plate has a pattern corresponding to the first cleavage area on the front side of the thin wafer 1. Then, light of a specific wavelength is used to illuminate the mask plate and the first adhesive layer 3. The photoresist will undergo chemical changes under the action of light. Depending on the type of photoresist and the lighting conditions, the irradiated part or the unirradiated part will react differently in the subsequent process. Then the development step is performed. Development is to use a specific chemical solution to treat the first adhesive layer 3 after photolithography. The part of the photoresist that has changed after illumination will dissolve or remain under the action of the developer, thereby showing a clear pattern on the first adhesive layer 3. The area corresponding to this pattern is the first cleavage area, which provides a clear target area and operation guidance for the subsequent dry etching of the front side of the thin wafer 1 and other process steps. In this embodiment, the first adhesive layer 3 is a positive photoresist, and the part of the photoresist that has changed after illumination will dissolve under the action of the developer.

[0065] Step S107: dry-etching the front side of the thin wafer 1.

[0066] Among them, dry etching is a technology that uses gas plasma to etch materials. For dry etching of the front side of the thin wafer 1, the thin wafer 1 processed by the above steps is first placed in a specific etching device. In this embodiment, the thin wafer 1 processed by the above steps is placed in a plasma etching machine.

[0067] Specifically, the etching equipment generates plasma, usually by exciting the etching gas (such as fluoride, chloride, etc.) into a plasma state under a low pressure environment. The active ions and free radicals in the plasma are highly chemically active and can react chemically with the material on the front of the thin wafer 1. These active particles will impact the front of the thin wafer 1 and react physically and chemically with the material on the surface of the wafer, thereby removing the material in a specific area. The etching process is highly controllable, and the etching rate, depth and shape can be precisely controlled by adjusting parameters such as the type of etching gas, flow rate, pressure, plasma power and etching time.

[0068] It should be noted that in this embodiment, the dry etching depth of the front side of the thin wafer 1 is 10um to 20um, which creates conditions for subsequent process steps (such as wet etching, etc.) to achieve accurate cleavage of the thin wafer 1 and divide it into individual chips.

[0069] Step S108: wet-etching the back side of the thin wafer 1.

[0070] Among them, wet etching is a technology that uses chemical solutions to corrode materials. For wet etching of the back of the thin wafer 1, a specific etching solution must first be prepared. This etching solution is carefully selected based on the material properties of the thin wafer 1 and the requirements of cleavage, and can usually react chemically with a specific substance on the back of the thin wafer 1, thereby achieving corrosion of the area.

[0071] Specifically, in this embodiment, the thin wafer 1 is placed in the etching solution for 15 minutes to 20 minutes, and the etching solution is a mixed solution of hydrochloric acid and phosphoric acid, and the volume ratio of hydrochloric acid to phosphoric acid is 2:3. The back of the thin wafer 1 treated in the previous steps is immersed in the etching solution. During the etching process, the chemical substances in the etching solution will react with the material on the back of the thin wafer 1, gradually dissolving or removing a specific part.

[0072] In the present application, wet etching is combined with dry etching to achieve more accurate cleavage. Dry etching mainly acts on the front side of the thin wafer 1, while wet etching of the back side of the thin wafer 1 can be processed from the other side, making the cleavage more thorough and accurate. The combination of the two can better control the depth and shape of the cleavage and improve the quality and performance of the chip.

[0073] In some possible implementation embodiments provided in the present application, before step S101, the cleavage method further includes:

[0074] Step S99: forming a first dissociation zone on the front side of the wafer.

[0075] The first dissociation zone can be manufactured by photolithography, etching and other process methods.

[0076] Specifically, a specific photolithography device and photoresist can be used to perform photolithography exposure on the front side of the wafer, and a pre-designed dissociation zone pattern can be transferred to the photoresist. Then, the material outside the area defined by the photoresist is removed through an etching process, thereby forming a clear first dissociation zone on the front side of the wafer. It should be noted that the position, shape and size of the first dissociation zone need to be accurately planned according to the chip design and cleavage requirements. It will provide clear target areas and operating instructions for subsequent thin wafer 1 thinning and other cleavage steps, ensuring that the cleavage process can be accurately carried out along a predetermined path, and ultimately achieving the wafer being divided into individual chips.

[0077] Step S100: preparing a wafer into a thin wafer 1 by thinning.

[0078] The thinning process usually uses mechanical grinding, chemical mechanical polishing (CMP) and other technical means. Mechanical grinding uses rotating grinding discs and abrasives to gradually remove materials from the wafer surface and reduce the thickness of the wafer. Chemical mechanical polishing combines the effects of chemical corrosion and mechanical friction to further smooth the wafer surface and accurately control the degree of thinning.

[0079] Specifically, in this embodiment, the thickness of the thin wafer 1 formed after wafer thinning is 100um-140um.

[0080] In some possible implementation embodiments provided in this application, step S104 includes:

[0081] Step S1041: placing the thin wafer 1 in the BOE solution.

[0082] The thin wafer 1 is placed in a BOE solution to remove silicon oxide on the mask layer 2 at a position corresponding to the second cleavage region.

[0083] Specifically, the thin wafer 1 is placed in the BOE solution, and the chemical components in the solution will react chemically with the silicon oxide at the position corresponding to the second cleavage area in the mask layer 2 on the thin wafer 1. This reaction process is highly selective, and the BOE solution mainly corrodes the silicon oxide, while having little effect on the photoresist and other parts of the thin wafer 1.

[0084] It should be noted that by placing the thin wafer 1 in the BOE solution, the silicon oxide at a specific position on the mask layer 2 can be accurately removed, opening a channel for subsequent process steps (such as dry etching the front side of the thin wafer 1 and wet etching the back side of the thin wafer 1), ensuring that the cleavage process can be carried out accurately according to the predetermined plan, and ultimately achieving accurate cleavage of the thin wafer 1 and chip segmentation.

[0085] The following is an example of the values ​​of various parameters in the cleavage method:

[0086] Example: The thickness of mask layer 2 is In practical applications, the mask layer 2 of this thickness acts like a solid and precise protective film. For example, in the subsequent wet etching step, when the back of the thin wafer 1 is immersed in the etching solution, The thick silicon oxide mask layer 2 can effectively block the erosion of the corrosive liquid, ensuring that the circuit structure and other key parts on the back of the chip are not damaged. At the same time, during the photolithography process, the mask layer 2 of this thickness can provide a stable positioning reference for the photoresist, making the exposure and development process more accurate, thereby ensuring the accuracy and consistency of the cleavage area.

[0087] For example: the total thickness of at least two layers of photoresist coated on the front of the thin wafer 1 is 2.5um. Taking the etching process as an example, when the etching gas impacts the front of the thin wafer 1, the 2.5um thick photoresist layer can effectively prevent the etching gas from damaging the circuit structure on the front of the wafer. The bottom layer of photoresist can provide good adhesion to ensure that the photoresist layer is firmly attached to the thin wafer 1. The upper layer of photoresist can accurately define the pattern of the cleavage area, making the boundary of the cleavage area clearer and improving the precision and accuracy of cleavage.

[0088] For example, the thickness of the thin wafer 1 is 120um. This thickness of the thin wafer 1 has many advantages in the chip manufacturing process. On the one hand, it is thin enough to meet the needs of modern electronic products for miniaturization and high performance. On the other hand, during the cleavage process, the thickness of 120um makes the thin wafer 1 easier to process and handle accurately. For example, in the dry etching and wet etching steps, the thin wafer 1 of this thickness can better control the depth and shape of the cleavage, ensuring the quality and performance of the chip.

[0089] For example: The wet etching time of the back of the thin wafer 1 is 18 minutes. During this time, the etching solution can fully react with the material on the back of the thin wafer 1, remove specific parts, and achieve precise cleavage. For example, when the back of the thin wafer 1 is immersed in a mixed etching solution with a volume ratio of hydrochloric acid and phosphoric acid of 2:3, the etching time of 18 minutes can ensure that the etching depth is moderate, and the cleavage effect will not be affected by insufficient etching, nor will the structure and performance of the thin wafer 1 be damaged by excessive etching. At the same time, this time can also be coordinated with other process steps such as dry etching to achieve precise cleavage of the thin wafer 1.

[0090] It is easy for those skilled in the art to understand that, under the premise of no conflict, the above-mentioned advantageous methods can be freely combined and superimposed.

[0091] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application. The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and variations can be made without departing from the technical principles of the present application, and these improvements and variations should also be regarded as the protection scope of the present application.

Claims

1. A cleavage method, characterized in that: include: Growing silicon oxide on the back side of the thin wafer (1) to form a mask layer (2); Coating photoresist on a surface of the mask layer (2) facing away from the thin wafer (1) to form a second adhesive layer; Photolithography is performed on the second adhesive layer to construct a second cleavage region that overlaps with the first cleavage region on the front side of the thin wafer (1); removing silicon oxide at a position on the mask layer (2) relative to the second cleavage region; At least two layers of photoresist are coated on the front side of the thin wafer (1) to form a first photoresist layer (3); Photolithography is performed on the first glue layer (3), and a first cleavage region is displayed through a development step; Dry etching the front side of the thin wafer (1); The back side of the thin wafer (1) is wet etched.

2. The cleavage method according to claim 1, characterized in that: The step of removing silicon oxide at a position on the mask layer (2) relative to the second cleavage region comprises: Place the thin wafer (1) in the BOE solution.

3. The cleavage method according to claim 1, characterized in that: The step of dry etching the front side of a thin wafer (1) comprises: A thin wafer (1) is placed in a plasma etching machine.

4. The cleavage method according to claim 1, characterized in that: The step of wet etching the back side of the thin wafer (1) comprises: Placing a thin wafer (1) in a mixed solution of hydrochloric acid and phosphoric acid; Among them, the volume ratio of hydrochloric acid to phosphoric acid is 2:

3.

5. The cleavage method according to claim 1, characterized in that: Before the step of growing silicon oxide on the back side of the thin wafer (1) to form a mask layer (2), the cleavage method further comprises: forming a first dissociation zone on the front side of the wafer; The wafer is prepared into a thin wafer (1) by thinning.

6. The cleavage method according to claim 1, characterized in that: The thickness of the thin wafer (1) is 100um to 140um.

7. The cleavage method according to claim 1, characterized in that: The dry etching depth of the front side of the thin wafer (1) is 10um to 20um.

8. The cleavage method according to claim 1, characterized in that: The wet etching time of the back side of the thin wafer (1) is 15 minutes to 20 minutes.

9. The cleavage method according to claim 1, characterized in that: The thickness of the mask layer (2) is 10. The cleavage method according to claim 1, characterized in that: The thickness of at least two layers of photoresist coated on the front side of the thin wafer (1) is 2um to 3um.

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