Semiconductor packaging structure
By introducing barrier structure and multi-layer TIM design into the semiconductor packaging structure, the layering problem caused by thermal expansion of the packaging structure during temperature cycle is solved, and the reliability and TIM material failure efficiency in the packaging process is improved.
Patent Information
- Application Number
- CN202310802861.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-30
- Publication Date
- 2025-01-07
AI Technical Summary
The deformation of the existing semiconductor packaging structures due to different thermal expansion coefficients and Young's modulus during the temperature cycle leads to large tensile stress at the interface between the TIM and the chip, resulting in high stratification and cavitation rates.
A semiconductor packaging structure is designed. By providing a barrier structure inside the Lid structure, the barrier layer extends from the side wall of the chip to the inner side of the Lid structure to form a space and fills a second TIM. The barrier structure includes a barrier layer and a sealing gasket, and the barrier layer The structure forms an acute angle or perpendicular relationship with the Lid structure and the chip sidewall, and the support structure enhances the bonding strength, ensuring that the TIM flows and surrounds the chip sidewall when the temperature changes, reducing interface layering and hollow generation.
It effectively reduces the layering of the interface between the TIM and the chip, improves the reliability and reliability of the packaging, reduces the hollow rate, and enhances the overall reliability of the packaging.
Smart Images
Figure CN119275184A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor chip packaging and testing, and in particular, to a semiconductor packaging structure. Background Art
[0002] With the continuous evolution of chip manufacturing processes, advanced packaging technologies such as 2D, 2.5D, and 3D have increased the functionality and speed of chip packaging, while consuming more and more power and volume, and the heat dissipation problem has become more and more significant. In order to solve the heat dissipation problem, many projects currently use Indium thermal interface materials TIM and its alloy TIM with higher thermal conductivity. Although the heat dissipation problem has been solved, stratification, high void rate, and poor coverage have appeared in the reliability process, which seriously affects the use of the product. Figure 1 is a schematic diagram of a semiconductor packaging result in the related art, such as Figure 1 As shown in the figure, during the high and low temperature cycle, due to the different material properties such as thermal expansion coefficient (CTE) and Young's modulus between the metal cover lid, metal TIM, chip, substrate and other structures, the entire packaging structure is deformed during the temperature cycle, thereby generating stress at the connection interface between TIM and chip. According to the actual production slice analysis, the shrinkage of TIM during the cooling process will form the following Figure 1 As shown in the figure, a large tensile stress will be generated at the interface between TIM and chip, resulting in delamination.
[0003] Regarding the problem that the packaging structure in the related art will deform during the temperature cycle, and a large tensile stress will be generated at the connection interface between the TIM and the chip, resulting in delamination, no solution has been proposed yet. Summary of the invention
[0004] The embodiment of the present application provides a semiconductor packaging structure to at least solve the problem in the related art that the packaging structure is deformed during temperature cycling, and a large tensile stress is generated at the connection interface between the TIM and the chip, resulting in delamination.
[0005] According to an embodiment of the present application, a semiconductor package structure is provided, the semiconductor package structure comprising: a substrate 206, an integrated circuit chip 203 disposed on the substrate 206, and a lid structure 201 covering the integrated circuit chip 203, wherein a first TIM 202 is filled between the inner side of the lid structure 201 and the integrated circuit chip 203, wherein:
[0006] A blocking structure 207 for blocking the first TIM 202 is provided on the inner side of the lid structure 201, and the blocking structure 207 includes a blocking layer 207a, wherein the blocking layer 207a extends from the side wall of the integrated circuit chip 203 to the inner side of the lid structure 201, wherein a first space is formed between the inner wall of the blocking layer 207a and the side wall of the integrated circuit chip 203.
[0007] In one embodiment, a first end of the barrier layer 207 a is fixed on an inner side of the lid structure 201 .
[0008] In one embodiment, the barrier structure 207 further includes a sealing gasket 207 b , wherein the second end of the barrier layer 207 a is coupled to the sidewall of the integrated circuit chip 203 through the sealing gasket 207 b .
[0009] In one embodiment, the barrier layer 207 a is perpendicular to the sidewall of the integrated circuit chip 203 at the second end.
[0010] In one embodiment, an outer wall of the barrier layer 207 a forms an acute angle with an inner side of the lid structure 201 at a first end.
[0011] In one embodiment, the barrier layer 207 a is parallel to the sidewall of the integrated circuit chip 203 at the second end.
[0012] In one embodiment, the blocking layer 207a includes a first blocking sublayer and a second blocking sublayer, one end of the first blocking sublayer is the first end of the blocking layer 207a, the other end of the first blocking sublayer is connected to one end of the second blocking sublayer, and the other end of the second blocking sublayer is the second end of the blocking layer 207a, wherein the first blocking sublayer and the second blocking sublayer are perpendicular, and the first blocking sublayer is perpendicular to the lid structure 201, and the second blocking sublayer is perpendicular to the side wall of the integrated circuit chip 203.
[0013] In one embodiment, the first space is filled with a second TIM 207 c , and the second TIM 207 c surrounds the contact surface between the integrated circuit chip 203 and the first TIM 202 .
[0014] In one embodiment, the distance from the second end of the barrier layer 207 a to the inner side of the lid structure is greater than or equal to one third of the total thickness of the integrated circuit chip 203 .
[0015] In one embodiment, the blocking structure 207 further includes a supporting structure 207d disposed between the outer wall of the blocking layer 207a and the inner side of the lid structure 201, wherein:
[0016] One end of the support structure 207d is connected to the inner side of the lid structure 201, and the other end is connected to the outer wall of the barrier layer.
[0017] In one embodiment, the barrier layer 207a and the support structure 207d are an integral structure or a separate structure.
[0018] In one embodiment, the width of the sealing gasket 207 b is equal to the distance from the second end of the barrier layer 207 a to the sidewall of the integrated circuit chip 203 .
[0019] In one embodiment, the lid structure 201 is formed by stamping.
[0020] The semiconductor package structure of the embodiment of the present application includes: a substrate 206, an integrated circuit chip 203 arranged on the substrate 206, and a lid structure 201 covering the integrated circuit chip 203, wherein a first TIM 202 is filled between the inner side of the lid structure 201 and the integrated circuit chip 203, and a blocking structure 207 for blocking the first TIM 202 is arranged on the inner side of the lid structure 201, and the blocking structure 207 includes a blocking layer 207a, and the blocking layer 207a extends from the side wall of the integrated circuit chip 203 to the inner side of the lid structure 201, and is used to surround the first TIM 202, and the inner wall of the blocking layer 207a is connected to the integrated circuit chip 203. A first space is formed between the side walls of the circuit chip 203, which can solve the problem that the packaging structure in the related art is deformed during the temperature cycle, and a large tensile stress is generated at the connection interface between the TIM and the chip, thereby causing delamination. Through the lid structure with a blocking structure that blocks the TIM, during the temperature cycle, after reaching the melting point of the TIM, the metal TIM will flow along the inner wall of the dam to the side wall of the chip, completely surrounding the interface between the chip and the TIM to reduce the possibility of interface delamination. At the same time, during the packaging process, the bubbles in the TIM can also enter the side wall dam area along the flowing TIM, providing a path for the discharge of bubbles, thereby reducing the generation of voids and improving the packaging reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is a schematic diagram of a semiconductor packaging structure in the related art;
[0022] Figure 2 is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present application;
[0023] Figure 3 is a three-dimensional schematic diagram of a semiconductor packaging structure according to an embodiment of the present application;
[0024] Figure 4 is a schematic diagram of a semiconductor package structure according to an embodiment of the present application, wherein the barrier layer is a hook type;
[0025] Figure 5 According to the embodiment of the present application Figure 4 A horizontal cross-sectional view of the package structure along line AA';
[0026] Figure 6 According to the embodiment of the present application Figure 4 A horizontal cross-sectional view of the package structure along line BB';
[0027] Figure 7 is a schematic diagram of a semiconductor package structure according to an embodiment of the present application, wherein the barrier layer is a vertical sidewall;
[0028] Figure 8 is a schematic diagram of a semiconductor package structure according to an embodiment of the present application, wherein the barrier layer has a right-angled sidewall. DETAILED DESCRIPTION
[0029] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0031] In this embodiment, a semiconductor packaging structure is provided. Figure 2 is a schematic diagram of a semiconductor packaging result according to an embodiment of the present application, such as Figure 2 As shown, the semiconductor package structure includes: a substrate 206, an integrated circuit chip 203 arranged on the substrate 206, and a lid structure 201 covering the integrated circuit chip 203, the first TIM 202 is filled between the inner side of the lid structure 201 and the integrated circuit chip 203, and a blocking structure 207 for blocking the first TIM 202 is arranged on the inner side of the lid structure 201. The blocking structure 207 includes a blocking layer 207a, and the blocking layer 207a extends from the side wall of the integrated circuit chip 203 to the inner side of the lid structure 201, and is used to surround the first TIM 202. A first space is formed between the inner wall of the blocking layer 207a and the side wall of the integrated circuit chip 203, and the first TIM 202 can be blocked from overflowing and the overflow height of the first TIM 202 can be controlled by the blocking layer 207a.
[0032] According to the semiconductor packaging structure of the above and following embodiments of the present disclosure, the failure of TIM materials in the reliability process can be effectively reduced. Compared with the semiconductor packaging structure in the related art, the semiconductor packaging structure adds a blocking structure that can block TIM overflow. The blocking structure that blocks TIM can effectively solve the problem of TIM and die interface delamination, thereby achieving the purpose of reducing TIM thickness and improving reliability.
[0033] Figure 3 FIG. 2 shows a schematic diagram of the effect of the semiconductor package structure blocking the TIM according to an embodiment of the present disclosure. Figure 3 As shown, the blocking structure can effectively prevent TIM from overflowing.
[0034] exist Figure 2 and Figure 3 Examples of other components of the semiconductor package structure are also shown. In this example, the semiconductor package structure includes a substrate stacking structure that transmits functional signals to the PCB board, and the substrate has many stacking layers. The integrated circuit chip 203 can be interconnected with the substrate 206 through micro-bumps, and the bottom filling glue (underfill) 204 is filled between the micro-bumps. The substrate 206 can be formed by pressing the intermediate core layer, the dielectric layer and the metal wiring. Specifically, one or more dielectric layers and metal wiring layers can be arranged above and below the intermediate core layer. One or more integrated circuit chips 203 placed thereon by, for example, flip-chip are arranged on the package substrate 206. The integrated circuit chip 203 can include a logic control chip, a memory chip and a dummy chip, and this part can also be a 2.5D packaged COWoS (Chip on Waferon Substrate) and InFO_OS (Integrated Fan Out Wafer Level Package On OrganicSubstrate) chip structure.
[0035] In one embodiment, the lid structure 201 is a cover plate structure, and the edge of the lid structure 201 has a protruding portion, which is covered on the top of the integrated circuit chip 203 through the protruding portion, and a cavity is formed between the protruding portion and the side wall of the integrated circuit chip 203. The protruding portion of the lid structure 201 can be bonded to the substrate 206 through an adhesive material 205, which plays a role in controlling the warping of the package substrate, protecting the chip and dissipating heat. The lid structure 201 contacts the chip 203 through a thermal interface material 202, and the chip 203 is interconnected with the substrate 206 through micro-bumps. Underfill material 204 is filled between the micro-bumps to absorb the stress generated during high and low temperature processes. The lid structure 201 and the barrier structure 207 can be formed by stamping, and the material can be metal.
[0036] In one embodiment, a second TIM may be filled in the first space, and the second TIM surrounds the contact surface between the integrated circuit chip 203 and the first TIM 202. The second TIM and the first TIM 202 may be the same or different TIMs.
[0037] In one embodiment, the distance from the second end of the barrier layer 207a to the inner side of the lid structure 201 (or the surface of the first TIM 202 adjacent to the lid structure 201) is greater than or equal to one third of the total thickness of the integrated circuit chip 203. This allows the depth of the TIM filled in the first space to be greater than or equal to one third of the total thickness of the integrated circuit chip 203.
[0038] In some embodiments, Figure 2 and 3 As shown, the first end of the barrier layer 207a is fixed to the inner side of the lid structure 201. For example, the first end of the barrier layer 207a can be fixed to the inner side of the lid structure 201 by welding. The second end of the barrier layer 207a can be directly connected / coupled to the side wall of the integrated circuit chip 203, or indirectly connected / coupled to the side wall of the integrated circuit chip 203 through other objects. For example, in one embodiment, the barrier structure 207 can also include a sealing gasket 207b (see Figure 4-5 and Figure 7-8 ), wherein the second end of the barrier layer 207a is coupled to the side wall of the integrated circuit chip 203 through the sealing gasket 207b. That is, the second end of the barrier layer 207a is a certain distance away from the side wall of the integrated circuit chip 203, and the sealing gasket 207b fills this distance, thereby surrounding the TIM to prevent it from overflowing. The sealing gasket 207b can be made of a rubber material with good elasticity.
[0039] In one embodiment, the sealing gasket 207b extends along the barrier layer to surround the chip. Figure 6 As shown in . The two structures of the sealing gasket and the barrier layer can fix the TIM material in a certain space. During the reliability process, when the TIM becomes a flowing state, it is not easy to flow out of the specified area, and the thickness and uniformity of the TIM material are guaranteed.
[0040] In various embodiments of the present disclosure, the barrier layer 207 a may extend from the first end to the second end along any trajectory, that is, the barrier layer 207 a may be in any shape. Figure 4-8 An enlarged schematic diagram of a barrier structure 207 according to an embodiment of the present disclosure is shown, wherein the barrier layer 207a is shown as three specific examples 207a1, 207a2 and 207a3.
[0041] exist Figure 4-6In the example of FIG. 1 , the barrier layer 207a1 is substantially perpendicular to the sidewall of the integrated circuit chip 203 at the second end. Substantially perpendicular means that the angle is within the allowable error range and does not necessarily have to meet 90 degrees. Figure 4 In the example, the outer wall of the barrier layer 207a forms an acute angle with the inner side of the lid structure 201 at the first end, that is, the barrier layer 207a1 is hook-shaped. The second end of the barrier layer 207a1 contacts the side wall of the integrated circuit chip 203 through the sealing gasket 207b; a first space is formed between the inner wall of the barrier layer 207a1 and the first TIM 202 and the integrated circuit chip 203, and the second TIM 207c is filled therein.
[0042] exist Figure 4 In the example of FIG. 2 , the sealing gasket 207b fills up the gap between the second end of the barrier layer 207a1 and the side wall of the integrated circuit chip 203. That is, the width H1-a of the sealing gasket 207b should fill up the gap between the second end of the barrier layer 207a1 and the side wall of the chip 203 after assembly. The TIM 207c surrounds the contact surface between the integrated circuit chip 203 and the TIM 202, and extends downward along the contact surface to form a filling height H3 between the first end and the second end of the barrier layer, and H3 is greater than or equal to one third of the total thickness of the integrated circuit chip 203.
[0043] exist Figure 4 In the example of , the barrier structure 207 further includes a support structure 207d disposed between the outer wall of the barrier layer 207a and the inner side of the lid structure 201, wherein one end of the support structure 207d is connected to the inner side of the lid structure 201, and the other end is connected to the outer wall of the barrier layer 207a. That is, the support structure 207d is disposed around the barrier layer 207a1 to enhance the bonding strength between the barrier layer 207a and the lid structure 201. The barrier layer 207a1 and the support structure 207d may be an integral structure or a separate structure.
[0044] The barrier layer 207a1 and the lid structure 201 can be fused together by welding. Figure 5 According to the embodiment of the present application Figure 4 The horizontal cross-sectional view of the package structure along the line A-A' in FIG. Figure 5 As shown, the second end of the barrier layer 207a1 contacts the side wall of the chip 203 through the sealing gasket 207b. Figure 6 According to the embodiment of the present application Figure 4 A horizontal cross-sectional view of the package structure along the line BB' in FIG. Figure 6 As shown, the space between the inner wall of the barrier layer 207 a and the sidewalls of the TIM 202 and the chip 203 is filled with the TIM 207 c .
[0045] In another example, the barrier layer 207a2 may be substantially parallel to the sidewall of the integrated circuit chip 203 at the second end. Substantially parallel means parallel within an allowable error range. Figure 7 As shown, the barrier layer 207a2 is a vertical sidewall, and the vertical sidewall 207a2 surrounds the chip area. Figure 7 In the example of FIG. 2 , the barrier structure 207 further includes a sealing gasket 207b, wherein the second end of the barrier layer / vertical sidewall 207a2 contacts the sidewall of the integrated circuit chip 203 through the sealing gasket 207b. The sealing gasket 207b fills the distance between the lower extension of the vertical sidewall 207a2 and the integrated circuit chip 203. That is, the width H1-b of the sealing gasket should fill the distance between the vertical sidewall 207a2 and the integrated circuit chip 203 after assembly. The first space formed between the inner wall of the vertical sidewall 207a2 and the TIM 202 and the sidewall of the integrated circuit chip 203 is filled with a second TIM 207c. The material of the second TIM 207c and the first TIM 202 may be the same or different. Similarly, a first end of the vertical sidewall 207a2 is fixed on the inner side of the lid structure 201, and a distance from a second end of the vertical sidewall 207a2 to the inner side of the lid structure 201 is greater than or equal to one third of the total thickness of the integrated circuit chip 203, so that a filling height H3 of the second TIM 207c is greater than or equal to one third of the total thickness of the integrated circuit chip 203.
[0046] In another example, if Figure 8 As shown, the barrier layer 207a3 includes a first barrier sublayer and a second barrier sublayer, one end of the first barrier sublayer is the first end of the barrier layer 207a3, the other end of the first barrier sublayer is connected to one end of the second barrier sublayer, and the other end of the second barrier sublayer is the second end of the barrier layer 207a3, wherein the first barrier sublayer and the second barrier sublayer are perpendicular, and the first barrier sublayer is perpendicular to the lid structure 201, and the second barrier sublayer is perpendicular to the side wall of the integrated circuit chip 203. That is, the barrier layer 207a3 has a right-angled side wall. Figure 8 As shown, the barrier structure 207 further includes a sealing gasket 207b, wherein the second end of the barrier layer 207a3 contacts the side wall of the integrated circuit chip 203 through the sealing gasket 207b. That is, the width H1-c of the sealing gasket 207b should fill the distance between the second end of the right-angle side wall 207a3 and the side wall of the integrated circuit chip 203 after assembly. The first space formed between the inner wall of the right-angle side wall 207a3 and the TIM 202 and the side wall of the integrated circuit chip 203 is filled with a second TIM 207c. The TIM 207c surrounds the contact surface between the integrated circuit chip 203 and the TIM 202, and extends downward along the contact surface to form a filling height H3, which is greater than or equal to about one third of the total thickness of the integrated circuit chip 203.
[0047] It should be noted that the blocking layer 207a can extend from the first end to the second end along any trajectory. The above-mentioned hook-type blocking layer 207a1, vertical side wall 207a2, and right-angled side wall 207a3 are only three typical embodiments of the blocking layer. The specific structure of the blocking layer 207a is not limited to the above three methods.
[0048] The semiconductor packaging structure in each embodiment of the present disclosure needs to take into account the design tolerance during the design process so that it can be implemented during the equipment process. In each embodiment, the width of the sealing gasket 207b is equal to or greater than the distance from the second end of the barrier layer 207a to the side wall of the chip. In addition, the span H2 of the barrier layer on the inner side of the lid structure is greater than or equal to the width of the chip, which is conducive to mounting the lid structure on the substrate.
[0049] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.
[0050] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.
[0051] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.
Claims
1. A semiconductor packaging structure, characterized in that: The semiconductor packaging structure comprises: a substrate (206), an integrated circuit chip (203) arranged on the substrate (206), and a lid structure (201) covering the integrated circuit chip (203), wherein a first thermal interface material TIM (202) is filled between the inner side of the lid structure (201) and the integrated circuit chip (203), wherein: A blocking structure (207) for blocking the first TIM (202) is arranged on the inner side of the lid structure (201), and the blocking structure (207) comprises a blocking layer (207a), wherein the blocking layer (207a) extends from the side wall of the integrated circuit chip (203) to the inner side of the lid structure (201), wherein a first space is formed between the inner wall of the blocking layer (207a) and the side wall of the integrated circuit chip (203).
2. The semiconductor package structure according to claim 1, wherein: A first end of the barrier layer (207a) is fixed on the inner side of the lid structure (201).
3. The semiconductor package structure according to claim 1 or 2, characterized in that: The barrier structure (207) further comprises a sealing gasket (207b), wherein the second end of the barrier layer (207a) is coupled to the side wall of the integrated circuit chip (203) through the sealing gasket (207b).
4. The semiconductor package structure according to claim 3, characterized in that: The barrier layer (207a) is perpendicular to the sidewall of the integrated circuit chip (203) at the second end.
5. The semiconductor package structure according to claim 4, characterized in that: The outer wall of the barrier layer (207a) forms an acute angle with the inner side of the lid structure (201) at the first end.
6. The semiconductor package structure according to claim 3, characterized in that: The barrier layer (207a) is parallel to the side wall of the integrated circuit chip (203) at the second end.
7. The semiconductor package structure according to claim 3, characterized in that: The blocking layer (207a) comprises a first blocking sublayer and a second blocking sublayer, wherein one end of the first blocking sublayer is the first end of the blocking layer (207a), the other end of the first blocking sublayer is connected to one end of the second blocking sublayer, and the other end of the second blocking sublayer is the second end of the blocking layer (207a), wherein the first blocking sublayer and the second blocking sublayer are perpendicular, and the first blocking sublayer is perpendicular to the lid structure (201), and the second blocking sublayer is perpendicular to the side wall of the integrated circuit chip (203).
8. The semiconductor package structure according to claim 3, wherein: The first space is filled with a second TIM (207c), and the second TIM (207c) surrounds the contact surface between the integrated circuit chip (203) and the first TIM (202).
9. The semiconductor package structure according to claim 8, characterized in that: The distance from the second end of the barrier layer (207a) to the inner side of the lid structure (201) is greater than or equal to one third of the total thickness of the integrated circuit chip (203).
10. The semiconductor package structure according to claim 1, wherein: The blocking structure (207) further comprises a supporting structure (207d) arranged between the outer wall of the blocking layer (207a) and the inner side of the lid structure (201), wherein: One end of the support structure (207d) is connected to the inner side of the lid structure (201), and the other end is connected to the outer wall of the barrier layer (207a).
11. The semiconductor package structure according to claim 9, wherein: The barrier layer (207a) and the support structure (207d) are an integral structure or a separate structure.
12. The semiconductor package structure according to any one of claims 3 to 11, characterized in that: The width of the sealing gasket (207b) is equal to the distance from the second end of the barrier layer (207a) to the side wall of the integrated circuit chip (203).