Programmable dead time control circuit for high-voltage half-bridge driver

Abstract

The invention belongs to the field of analog integrated circuit design and integrated systems, and particularly relates to a programmable dead time control circuit for a high-voltage half-bridge driver. Comprising a dead zone time selection circuit (100), a multi-selection mode circuit module and a dead zone logic control circuit (105) which are connected in sequence, and the multi-selection mode circuit module comprises an overlapped input mode circuit (101), an equal ratio input mode circuit (102), a fixed mode input circuit (103) and a dead zone forbidden mode circuit (104) which are connected in parallel. According to the invention, the control of four kinds of dead time can be completed on one driving circuit, so that the circuit can freely control the magnitude of the output dead time without other external structures.

Description

Technical Field

[0001] The invention belongs to the field of analog integrated circuit design and integrated system, in particular to a programmable dead time control circuit for a high voltage half-bridge driver. Background Art

[0002] At present, the rapidly growing aerospace power supply, artificial satellite, rail transportation, solar photovoltaic and motor drive markets have greatly promoted the development of power-specific drive circuits, and also brought unprecedented opportunities and challenges to the power semiconductor industry. The dead time control circuit plays a very critical role in the entire drive circuit system. Traditional drive circuits can only generate fixed dead time, which is not conducive to the use of circuits in variable input environments. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a programmable dead time control circuit structure for a high voltage half-bridge driver, which can meet the urgent needs of applications in the fields of automatic control systems and servo motor drives. The development of the present invention can complete the control of four dead times on a drive circuit, so that the circuit can freely control the output dead time size without the need for other external structures.

[0004] The technical solution adopted by the present invention to achieve the above-mentioned purpose is:

[0005] A programmable dead time control circuit for a high voltage half-bridge driver comprises: a dead time selection circuit module, a multi-selection mode circuit module and a dead time logic control circuit connected in sequence, wherein the multi-selection mode circuit module comprises an overlapping input mode circuit, a geometric input mode circuit, a fixed mode input circuit and a dead time disable mode circuit connected in parallel.

[0006] The dead time selection circuit is an input circuit, wherein:

[0007] The input terminal DT is connected to the fixed mode input circuit and the dead zone disabled mode circuit respectively through the resistor R11, the input terminal DT is connected to the overlap mode input circuit through the NMOS tube MN11, and the input terminal DT is connected to the proportional input mode circuit through the NMOS tube MN12.

[0008] The overlap input mode circuit is a comparator circuit, wherein:

[0009] The non-inverting input of the comparator is connected to the dead time selection circuit, the inverting input is connected to the power supply VDD through the resistor R1, the inverting input is also connected to the ground through the resistors R2, R3, and R4 in sequence, and the output is connected to the dead time logic control circuit.

[0010] The geometric ratio input mode circuit is a comparator circuit, wherein:

[0011] The non-inverting input of the comparator is connected to the dead time selection circuit, the inverting input is connected to the power supply VDD through resistors R1 and R2 in sequence, the inverting input is also grounded through resistors R3 and R4 in sequence, and the output is connected to the dead time logic control circuit.

[0012] The fixed mode input circuit is a comparator circuit, wherein:

[0013] The non-inverting input of the comparator is connected to the dead time selection circuit, the inverting input is connected to the power supply VDD through resistors R1, R2, and R3 in sequence, the inverting input is also grounded through resistor R4, and the output is connected to the dead time logic control circuit.

[0014] The dead zone disable mode circuit is a comparator circuit, wherein:

[0015] The comparator's non-inverting input is connected to the dead time selection circuit, the inverting input is connected to the drain of the PMOS tube, and the gate of the PMOS tube is connected to the power supply V bias The source is connected to the power supply VDD, the inverting input is also connected to the drain of the NMOS tube through the resistor R5, the gate of the NMOS tube is connected to the clock signal, the source is grounded, a capacitor C is connected between the drain and the source, and the output is connected to the dead zone logic control circuit.

[0016] The logic control circuit is a logic circuit, wherein:

[0017] The output signal of the fixed mode input circuit is connected to the input end of the NOR gate NOR1 with the square wave signal, the output end of NOR1 is respectively connected to the input end of the inverter INV1 and the CLK end of the D flip-flop 2, the dead zone disable mode circuit is connected to the input end of the D flip-flop 1, the overlapping mode input circuit and the output signal of the geometric input mode circuit are connected to the input end of the NAND gate NAND1, the output end of NAND1 and the output end of the D flip-flop 1 are connected to the input end of the NAND gate NAND2, the output end of NAND2 and the output end of INV1 are connected to the input end of the NAND gate NAND4, the output signal of the fixed mode input circuit is connected to the input end of the NOR gate NOR2 with the square wave signal, the output end of NOR2 is respectively connected to the input end of the inverter INV2 and the CLK end of the D flip-flop 1, the output end of NAND1 and the output end of the D flip-flop 2 are connected to the input end of the NAND gate NAND3, the output end of NAND3 and the output end of INV2 are connected to the input end of the NAND gate NAND5, and the output ends of NAND4 and NAND5 are used as the first output end OUT1 and the second output end OUT2 of the logic control circuit to output the result.

[0018] A method for implementing a programmable dead time control circuit for a high voltage half-bridge driver comprises the following steps:

[0019] When the DT terminal of the dead time selection circuit is grounded, a 0V voltage is obtained, the overlap input mode is started, and a signal is output to the overlap input mode circuit;

[0020] When the DT terminal of the dead time selection circuit is connected to a 30K~300K resistor, a voltage of 0.6V~6V is obtained, and the geometric input mode is entered, and the output signal is given to the geometric input mode circuit;

[0021] When the dead time selection circuit DT is connected to a resistor of 310K or more, a voltage of 6.2V is obtained, and the fixed mode input is entered, and the output signal is given to the fixed mode input circuit;

[0022] When the dead time selection circuit DT is connected to the power supply, it enters the dead time disable mode and outputs a signal to the dead time disable mode circuit;

[0023] The overlapping input mode circuit, the geometric input mode circuit, the fixed mode input circuit or the dead zone disabled mode circuit outputs a control signal, and the dead zone logic control circuit obtains an output voltage through logic transmission.

[0024] The present invention has the following beneficial effects and advantages:

[0025] 1. The present invention improves the influence of the fixed dead time in the high-voltage half-bridge driver on the circuit.

[0026] 2. The present invention can convert the overlapping time of the input signal into the dead time.

[0027] 3. The present invention can allow output signal overlap and is suitable for applications that require simultaneous switching of two driver output stages. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a programmable dead time control circuit structure for a high voltage half-bridge driver according to the present invention;

[0029] Figure 2 is a schematic diagram of the circuit structure of the present invention;

[0030] Figure 3 is the circuit diagram of the comparator in different modes;

[0031] Figure 4 Circuit diagram for dead time selection circuit;

[0032] Figure 5 It is the circuit diagram of the logic control circuit;

[0033] Figure 6 This is the effect diagram of the output of overlapping input mode under dead time control;

[0034] Figure 7This is the effect diagram of the output of the proportional input mode under the dead time control;

[0035] Figure 8 This is the effect diagram of the fixed input mode output under dead time control;

[0036] Fig. 9 This is a diagram showing the effect of disabling mode output under dead time control. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0038] The present invention discloses a programmable dead time control circuit structure for a high voltage half-bridge driver, the structure comprising a dead time selection circuit (100), an overlapping input mode circuit (101), a proportional input mode circuit (102), a fixed input mode circuit (103), a dead time disabling mode circuit (104), and a dead time control logic circuit (105). The dead time selection circuit (100) provides power, ground, and resistors of different resistance values ​​as inputs and transmits them to other modes; when the dead zone pin is grounded, the pin voltage is less than the set value A, and the dead time of the input is fixed. The dead time at this time is the overlap time of the high and low side inputs of the high voltage half-bridge driver; the geometric input mode circuit (102) is used to generate a dead time that varies with the dead zone pin voltage; when the pin voltage of the fixed input mode circuit (103) exceeds the set value B, a fixed dead time is generated; when the pin voltage of the dead zone disable mode circuit (104) exceeds the set value C, the output signal is allowed to overlap; and the dead zone control logic circuit (105) is used to generate a control signal, convert the electrical signals of the four modes into control signals, and complete the adjustment of the four dead time modes.

[0039] like Figure 1 As shown, a programmable dead time control circuit structure for a high voltage half-bridge driver, the main structure of which includes a dead time selection circuit (100), an overlapping input mode circuit (101), a proportional input mode circuit (102), a fixed mode input circuit (103), a dead time disable mode circuit (104), and a dead time control logic circuit (105), wherein:

[0040] Dead time selection circuit (100): when the selection circuit is connected to the ground, a voltage of 0V is obtained, and the overlapping input mode is started; when a resistor of 30K to 300K is connected, a voltage of 0.6V to 6V is obtained, and the geometric input mode is entered; when a resistor of 310K or more is connected, a voltage of 6.2V is obtained, and the fixed mode input is entered; when the power supply is connected, the dead time disabled mode is entered;

[0041] Overlap input mode circuit (101): when the dead zone pin is grounded, the dead zone time selection voltage is less than the set value A, the dead zone time of the fixed input, and the dead zone time at this time is the overlap time of the high and low side inputs of the high voltage half-bridge driver;

[0042] A proportional input mode circuit (102): when the value of the dead time selection voltage is between the set values ​​A and B, it is used to generate a dead time that varies with the dead time selection voltage;

[0043] Fixed mode input circuit (103): When the dead time selection voltage exceeds the set value B, a fixed dead time is generated;

[0044] Dead zone disable mode circuit (104): when the pin voltage exceeds the set value C, the output signal is allowed to overlap;

[0045] Dead zone control logic circuit (105): used to generate control signals, convert the electrical signals of the four modes into control signals, and complete the adjustment of the four dead zone time modes.

[0046] The dead time selection circuit (100) is grounded and inputs the input signal to the comparator for comparison. When the output voltage VDT of the dead time selection circuit (100) is less than the set value A, the programmability of the programmable dead time control circuit structure is disabled and the dead time is fixed. If the high side and the low side overlap by X ns, a dead time of X ns is automatically inserted.

[0047] On the contrary, if the dead time of the high side and the low side is greater than 0ns, the dead time will not be modified but passed to the output stage of the dead time control logic circuit (105).

[0048] The dead time selection circuit (100) is connected to a power supply and sends an input signal to a comparator for comparison. When the output voltage VDT of the dead time selection circuit (100) is greater than a set value C, the output signal is allowed to overlap.

[0049] When the dead time selection circuit (100) is connected to a resistor greater than 310K, the input signal is sent to the comparator for comparison. When the output voltage VDT of the dead time selection circuit (100) exceeds the set value B, a fixed dead time is output.

[0050] When the dead time selection circuit (100) is connected to a 30K-300K resistor, the input signal is sent to the comparator for comparison. When the value of the output voltage VDT of the dead time selection circuit (100) is between the set values ​​A and B, the voltage is compared with the triangle wave formed by RC to generate a narrow pulse signal. The narrow pulse signal is connected to the dead time control logic circuit (105). The dead time control logic circuit (105) completes the dead time control through logic processing.

[0051] like Figure 2 As shown in FIG. 1 , a programmable dead time control circuit for a high voltage half-bridge driver is mainly composed of a comparator, a resistor voltage divider circuit, a dead time selection, a logic control, and a triangle wave generator circuit. The comparator circuit is shown in FIG. Figure 3 When the input signal is grounded, the comparison point at one end of comparator 3 is R4, and the output of comparator 3 is low level, then the comparison output values ​​of the other three modes are all low, and the four signals are transmitted to the logic control module. The input overlap time is made into dead time through the internal gate circuit to complete the overlapping input mode. The overlapping waveform is shown in Figure 6 shown.

[0052] like Figure 4 As shown, in the dead time selection circuit (100), the input terminal DT is respectively connected to the fixed mode input circuit (103) and the dead zone disabled mode circuit (104) through the resistor R11, the input terminal DT is connected to the overlap mode input circuit (101) through the NMOS transistor MN11, and the input terminal DT is connected to the proportional input mode circuit (102) through the NMOS transistor MN12.

[0053] like Figure 5 As shown, the logic control circuit (105) is a logic circuit, wherein the output signal of the fixed mode input circuit (103) is connected to the square wave signal and the input end of the NOR gate NOR1, the output end of NOR1 is respectively connected to the input end of the inverter INV1 and the CLK end of the D flip-flop 2, the dead zone disable mode circuit (104) is connected to the input end of the D flip-flop 1, the output signals of the overlap mode input circuit (101) and the geometric input mode circuit (102) are connected to the input end of the NAND gate NAND1, the output end of NAND1 and the output end of the D flip-flop 1 are connected to the input end of the NAND gate NAND2, and the output end of NAND2 is connected to INV1. The output end of the fixed mode input circuit (103) is connected to the input end of the NAND gate NAND4, the output signal of the fixed mode input circuit (103) and the square wave signal are connected to the input end of the NOR gate NOR2, the output end of NOR2 is respectively connected to the input end of the inverter INV2 and the CLK end of the D flip-flop 1, the output end of NAND1 and the output end of the D flip-flop 2 are connected to the input end of the NAND gate NAND3, the output end of NAND3 and the output end of INV2 are connected to the input end of the NAND gate NAND5, and the output ends of NAND4 and NAND5 are respectively used as the first output end OUT1 and the second output end OUT2 of the logic control circuit (105) to output the result.

[0054] The comparison point at one end of comparator 4 is the generated triangular wave. If the voltage value of the dead time input is greater than R4 and less than the voltage value of R3, the outputs of comparators 1 and 2 are low, and the comparison output value of comparator 3 is high. Comparator 4 will generate a narrow pulse signal, and transmit the narrow pulse signal and other three signals to the logic control module. The resistance value selected by the dead time is made into the dead time through the internal gate circuit, completing the geometric input mode. The waveform of the geometric input is shown as follows: Figure 7 shown.

[0055] The comparison point at one end of comparator 2 is the value of R3. If the voltage value of the dead time input is greater than R3 and less than the voltage value of R2, the output of comparators 1 and 2 is low, and the comparison output value of comparators 3 and 4 is high. The four signals are transmitted to the logic control module, and the dead time is fixed through the internal gate circuit to complete the fixed input mode. The waveform of the fixed input is shown as follows: Figure 8 shown.

[0056] The comparison point at one end of comparator 1 is the value of R2. If the voltage value of the dead time input is greater than R2 and less than the voltage value of R1, the output of comparator 1 is low, and the comparison output values ​​of comparators 2, 3, and 4 are high. The four signals are transmitted to the logic control module, and the dead time is cancelled through the internal gate circuit, allowing signal overlap to complete the dead zone disable mode. The waveform in the disable mode is shown as follows: Fig. 9 shown.

[0057] The above is a specific embodiment of the present invention, and the principle of the present invention has been described in the above description. The protection scope of the present invention is not limited to this. Any simple structural changes made by any designer in this professional field within the scope of the disclosure of the present invention belong to this invention. Therefore, the protection scope of the present invention shall be based on the scope of the claims.

Claims

1. A programmable dead time control circuit for a high voltage half-bridge driver, characterized in that: include: A dead time selection circuit (100) module, a multi-selection mode circuit module and a dead time logic control circuit (105) are connected in sequence, wherein the multi-selection mode circuit module includes an overlap input mode circuit (101), a geometric input mode circuit (102), a fixed mode input circuit (103) and a dead time disable mode circuit (104) connected in parallel.

2. A programmable dead time control circuit for a high voltage half-bridge driver according to claim 1, characterized in that: The dead time selection circuit (100) is an input circuit, wherein: The input terminal DT is respectively connected to the fixed mode input circuit (103) and the dead zone disabled mode circuit (104) through the resistor R11, the input terminal DT is connected to the overlap mode input circuit (101) through the NMOS transistor MN11, and the input terminal DT is connected to the proportional input mode circuit (102) through the NMOS transistor MN12.

3. A programmable dead time control circuit for a high voltage half-bridge driver according to claim 1, characterized in that: The overlap input mode circuit (101) is a comparator circuit, wherein: The comparator's non-inverting input terminal is connected to a dead time selection circuit (100), its inverting input terminal is connected to a power source VDD via a resistor R1, its inverting input terminal is also connected to ground via resistors R2, R3, and R4 in sequence, and its output terminal is connected to a dead time logic control circuit (105).

4. A programmable dead time control circuit for a high voltage half-bridge driver according to claim 1, characterized in that: The geometric ratio input mode circuit (102) is a comparator circuit, wherein: The comparator's non-inverting input terminal is connected to a dead time selection circuit (100), its inverting input terminal is connected to a power source VDD via resistors R1 and R2 in sequence, its inverting input terminal is also connected to ground via resistors R3 and R4 in sequence, and its output terminal is connected to a dead time logic control circuit (105).

5. A programmable dead time control circuit for a high voltage half-bridge driver according to claim 1, characterized in that: The fixed mode input circuit (103) is a comparator circuit, wherein: The comparator's non-inverting input terminal is connected to a dead time selection circuit (100), its inverting input terminal is connected to a power source VDD via resistors R1, R2, and R3 in sequence, its inverting input terminal is also grounded via a resistor R4, and its output terminal is connected to a dead time logic control circuit (105).

6. A programmable dead time control circuit for a high voltage half-bridge driver according to claim 1, characterized in that: The dead zone disable mode circuit (104) is a comparator circuit, wherein: The comparator's non-inverting input terminal is connected to the dead time selection circuit (100), the inverting input terminal is connected to the drain of the PMOS tube, and the gate of the PMOS tube is connected to the power supply V bias The source is connected to the power supply VDD, the inverting input terminal is also connected to the drain of the NMOS tube through a resistor R5, the gate of the NMOS tube is connected to the clock signal, the source is grounded, a capacitor C is connected between the drain and the source, and the output terminal is connected to the dead zone logic control circuit (105).

7. A programmable dead time control circuit for a high voltage half-bridge driver according to claim 1, characterized in that: The logic control circuit (105) is a logic circuit, wherein: The output signal of the fixed mode input circuit (103) is connected to the square wave signal and the input end of the NOR gate NOR1. The output end of NOR1 is respectively connected to the input end of the inverter INV1 and the CLK end of the D flip-flop 2. The dead zone disable mode circuit (104) is connected to the input end of the D flip-flop 1. The output signal of the overlap mode input circuit (101) and the proportional input mode circuit (102) is connected to the input end of the NAND gate NAND1. The output end of NAND1 and the output end of the D flip-flop 1 are connected to the input end of the NAND gate NAND2. The output end of NAND2 and the output end of INV1 are connected to the NAND gate N The input end of AND4, the output signal of the fixed mode input circuit (103) and the square wave signal are connected to the input end of the NOR gate NOR2, the output end of NOR2 is respectively connected to the input end of the inverter INV2 and the CLK end of the D flip-flop 1, the output end of NAND1 and the output end of the D flip-flop 2 are connected to the input end of the NAND gate NAND3, the output end of NAND3 and the output end of INV2 are connected to the input end of the NAND gate NAND5, and the output ends of NAND4 and NAND5 are respectively used as the first output end OUT1 and the second output end OUT2 of the logic control circuit (105) to output the result.

8. A method for implementing a programmable dead time control circuit for a high voltage half-bridge driver, characterized in that: The following steps are involved: When the DT terminal of the dead time selection circuit (100) is grounded, a voltage of 0V is obtained, the overlapping input mode is started, and a signal is output to the overlapping input mode circuit (101); When the DT terminal of the dead time selection circuit (100) is connected to a 30K-300K resistor, a voltage of 0.6V-6V is obtained, and the geometric input mode is entered, and a signal is output to the geometric input mode circuit (102); When the dead time selection circuit (100) DT is connected to a resistor of 310K or more, a voltage of 6.2V is obtained, and a fixed mode input is entered, and a signal is output to the fixed mode input circuit (103); When the dead time selection circuit (100) DT is connected to the power supply, it enters the dead time disable mode and outputs a signal to the dead time disable mode circuit (104); The overlapping input mode circuit (101), the geometric input mode circuit (102), the fixed mode input circuit (103) or the dead zone disabled mode circuit (104) outputs a control signal, and the dead zone logic control circuit (105) obtains an output voltage through logic transmission.

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