Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a bit line contact plug and an insulation structure, the substrate internally comprises a plurality of active regions arranged in an array and isolation structures used for limiting the active regions; the bit line contact plugs are arranged corresponding to the active region, and the adjacent bit line contact plugs are insulated from each other through an insulation structure; wherein the bit line contact plug comprises a conductive contact plug and an interface layer located between the conductive contact plug and the corresponding active region; the resistivity of the conductive contact plug is within a preset range. According to the structure, the contact resistance between the bit line contact plug and the active region can be reduced, and the conductive contact plug can be simultaneously used as a barrier layer between the conductive contact plug and the conductive layer, so that the preparation process of a bit line barrier layer in an original bit line structure is saved, the yield of the semiconductor structure is improved, and the cost of the semiconductor structure is reduced; the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory, which usually includes capacitors and transistors. The memory usually adopts a buried word line structure or a horizontal word line structure, and electrically connects the bit line to the end surface of the transistor.

[0003] With the development of semiconductor technology and the shrinkage of process nodes, the reduction in the area occupied by the bit line contact plug will lead to an increase in the contact resistance between the bit line and the transistor, thereby causing a decrease in the performance of the semiconductor structure. Therefore, how to simplify the semiconductor structure preparation process while improving its overall performance is an urgent problem to be solved. Summary of the invention

[0004] Based on this, the present disclosure provides a semiconductor structure and a method for preparing the same, so as to reduce the contact resistance of the bit line contact plug and simplify the preparation process steps of the semiconductor structure, thereby optimizing the electrical performance of the semiconductor structure.

[0005] According to various embodiments of the present disclosure, on the one hand, a semiconductor structure is provided, including a substrate, a bit line contact plug and an insulating structure; the substrate includes a plurality of active areas arranged in an array and an isolation structure for defining the active areas; the bit line contact plugs are arranged corresponding to the active areas, and adjacent bit line contact plugs are insulated from each other via the insulating structure; wherein the bit line contact plugs include a conductive contact plug and an interface layer located between the conductive contact plug and the corresponding active area; the resistivity of the conductive contact plug is within a preset range.

[0006] In the semiconductor structure in the above embodiment, the bit line contact plug includes a conductive contact plug and an interface layer between the conductive contact plug and the corresponding active area, the interface layer is used as a transition layer between the conductive contact plug and the active area to avoid direct contact between the two and generate a large contact resistance; and the resistivity of the conductive contact plug is within a preset range, and the contact resistance between the bit line contact plug and the active area can be further reduced by reducing the resistivity of the material of the conductive contact plug. In the commonly used memory structure, the bit line plug is usually formed directly on the active layer to electrically connect the bit line to the active layer, but because the resistivity difference between the material of the active layer and the material of the bit line plug is generally large, a large contact resistance will be generated between the active layer and the bit line plug, resulting in current instability, heat generation, etc., and shortening the service life of the memory. By adopting the above-mentioned semiconductor structure provided by the present disclosure, the contact resistance between the bit line contact plug and the active area can be reduced, and the conductive contact plug can be used as a barrier layer between the conductive layer at the same time, so as to save the preparation process of the bit line barrier layer in the original bit line structure, thereby improving the yield of the semiconductor structure and reducing its cost, and also improving the electrical performance of the memory.

[0007] In some embodiments, the predetermined range is less than 25 μΩ·cm.

[0008] In some embodiments, the material of the conductive contact plug includes titanium nitride.

[0009] In some embodiments, the material of the interface layer includes titanium silicon alloy.

[0010] In some embodiments, the thickness of the conductive contact plug is greater than or equal to 35 nm and less than or equal to 45 nm.

[0011] In some of the embodiments, the semiconductor structure further includes a bit line connected to the bit line contact plug, the bit line extending along a first direction and arranged at intervals along a second direction; wherein the first direction is perpendicular to the second direction.

[0012] In some of the embodiments, a top surface of the active region is flush with a top surface of the isolation structure.

[0013] In some of the embodiments, the substrate includes a groove corresponding to the active region, and the bit line contact plug is connected to the active region exposed by the groove.

[0014] In some of the embodiments, the substrate further includes word lines located at opposite sides of the isolation structure along the first direction. The word lines extend along the second direction and are arranged at intervals along the first direction.

[0015] On the other hand, the present disclosure also provides a method for preparing a semiconductor structure, including: providing a substrate, the substrate including a plurality of initial regions arranged in an array and an isolation structure for defining the initial regions; forming an insulating structure on the top surface of the isolation structure; forming a seed layer on the top surface of the initial region, and allowing a portion of the initial region connected to the seed layer to react with the seed layer to form an interface layer, and the remaining initial region forms an active region; forming a conductive contact plug on the interface layer, the resistivity of the conductive contact plug being within a preset range; wherein the conductive contact plug and the interface layer together constitute a bit line contact plug, and adjacent bit line contact plugs are insulated from each other via the insulating structure.

[0016] In the method for preparing the semiconductor structure in the above embodiment, a seed layer is formed on the top surface of the initial region, and a portion of the initial region connected to the seed layer reacts with the seed layer to form an interface layer, and a conductive contact plug is formed on the interface layer. The interface layer is used as a transition layer between the conductive contact plug and the active region to avoid direct contact between the two and generate a large contact resistance; and the resistivity of the conductive contact plug is within a preset range, and the contact resistance between the bit line contact plug and the active region can be further reduced by reducing the resistivity of the material of the conductive contact plug. In the semiconductor structure preparation process used in the related art, the bit line plug is usually formed directly on the active layer, and a barrier layer is formed between the bit line plug and the bit line metal layer to electrically connect the bit line metal layer to the active layer and prevent the diffusion of material molecules in the bit line metal layer. However, since the resistivity difference between the material of the active layer and the material of the bit line plug is generally large, a large contact resistance will be generated between the active layer and the bit line plug, thereby shortening the service life of the memory and increasing the preparation cost. By adopting the above-mentioned preparation method provided by the present disclosure, the interface layer formed by the reaction between the seed layer and the top surface of the initial area can be utilized to reduce the contact resistance between the conductive contact plug and the active area, and the conductive contact plug can also be used as a barrier layer between the plug and the conductive layer at the same time, so as to save the preparation process of the barrier layer in the original bit line structure, thereby improving the yield of the semiconductor structure, improving the preparation efficiency, reducing the preparation cost and improving its electrical performance.

[0017] In some embodiments, forming the seed layer includes: forming the seed layer on the top surface of the initial region using a chemical vapor deposition process.

[0018] In some embodiments, forming a conductive contact plug includes: forming a conductive contact plug on the interface layer using an atomic layer deposition process.

[0019] In some embodiments, the thickness of the seed layer is greater than or equal to 5 nm and less than or equal to 7 nm.

[0020] In some embodiments, the material of the seed layer includes metallic titanium.

[0021] In some embodiments, the material of the conductive contact plug includes titanium nitride.

[0022] In some embodiments, after forming the conductive contact plug, the method further includes: forming a bit line on the top surface of the bit line contact plug, wherein the bit line extends along a first direction and is arranged at intervals along a second direction; wherein the first direction is perpendicular to the second direction.

[0023] In some of the embodiments, a top surface of the active region is flush with a top surface of the isolation structure.

[0024] In some of the embodiments, the substrate includes grooves corresponding to the active regions, and the bit line contact plugs are connected to the active regions exposed by the grooves. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 Shown is a schematic top view of a semiconductor structure in a related art provided by an embodiment of the present disclosure;

[0027] Figure 2 The display is a related technology provided by an embodiment of the present disclosure. Figure 1 Schematic diagram of the partial cross-section structure in the AA' direction;

[0028] Figure 3 It is shown that a related technology provided by an embodiment of the present disclosure Figure 2 A schematic cross-sectional structure diagram of a plug material layer formed on the structure shown;

[0029] Figure 4 It is shown that a related technology provided by an embodiment of the present disclosure Figure 3 A schematic cross-sectional view of a structure in which a bit line plug is formed on the structure shown;

[0030] Figure 5 It is shown that a related technology provided by an embodiment of the present disclosure Figure 4 A schematic cross-sectional structure diagram of a bit line barrier layer formed on the structure shown;

[0031] Figure 6 It is shown that a related technology provided by an embodiment of the present disclosure Figure 5 A schematic cross-sectional structure diagram of a bit line metal layer formed on the structure shown;

[0032] Figure 7 A schematic top view of a semiconductor structure provided by an embodiment of the present disclosure is shown;

[0033] Figure 8 The display is provided along the Figure 7 Schematic diagram of the cross-sectional structure along the AA' direction;

[0034] Fig. 9 A schematic diagram showing a process of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0035] Fig.10 A schematic top view of a semiconductor structure provided by another embodiment of the present disclosure is shown;

[0036] Fig.11 The display is provided along the Fig.10 Schematic diagram of the cross-sectional structure along the AA' direction;

[0037] Fig.12 The display is provided in an embodiment of the present disclosure Fig.11 A schematic diagram of a cross-sectional structure of an interface layer and a contact material layer formed on the structure shown;

[0038] Fig.13 The display is provided in an embodiment of the present disclosure Fig.12 A schematic cross-sectional view of a structure in which a bit line contact plug is formed on the structure shown;

[0039] Fig.14 The display is provided in an embodiment of the present disclosure Fig.13 A schematic cross-sectional structural diagram of a bit line and a bit line capping layer formed on the structure shown.

[0040] Description of reference numerals:

[0041] 10. Active layer; 11. Isolation region; 12. Word line structure; 13. Spacer layer; 14. Bit line plug; 141. Plug material layer; 15. Bit line barrier layer; 16. Bit line metal layer; 20. Substrate; 201. Active region; 2011. Initial region; 202. Isolation structure; 21. Word line; 211. Word line conductive layer; 212. Word line barrier layer; 213. Word line capping layer; 22. Protection layer; 23. Isolation layer; 24. Insulation structure; 25. Bit line contact plug; 251. Interface layer; 252. Conductive contact plug; 2521. Contact material layer; 26. Bit line; 27. Bit line capping layer. DETAILED DESCRIPTION

[0042] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0044] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0045] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0046] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0048] Dynamic random access memory usually includes a storage capacitor and a storage transistor electrically connected to the storage capacitor. The storage capacitor is used to store charges representing the stored information. With the development of semiconductor technology and the shrinking of process nodes, various electronic products have a trend towards miniaturization, and the design of dynamic random access memory cells must also meet the requirements of high integration and high density. Semiconductor structures such as dynamic random access memory usually use buried word line structures or horizontal word line structures, and electrically connect the bit lines to the end faces of the transistors.

[0049] In pursuit of faster response rate, lower power consumption and higher storage density, the size of semiconductor structures such as dynamic random access memory is constantly shrinking, the process difficulty of manufacturing buried word line or horizontal word line structure is increasing, the area occupied by the bit line contact plug (Bit Line Coupling, BLC) connecting the array transistor (Array Transistor) is shrinking, and the resistivity of the two is quite different, resulting in a decrease in the electrical performance of the semiconductor structure.

[0050] It should be noted that, in the embodiments of the present disclosure, the first direction may be the ox direction, the second direction may be the oz direction, and the third direction may be the oy direction.

[0051] As an example, see Figure 1 , Figure 1 It is a top view of a semiconductor structure obtained in the related art, wherein the semiconductor structure includes a substrate, wherein the substrate includes a plurality of active layers 10 arranged in an array along a first direction (e.g., an ox direction) and a second direction (e.g., an oz direction) and an isolation region 11 for defining the active layers 10, wherein the substrate also includes a word line structure 12 extending along the first direction (e.g., an ox direction) and arranged at intervals along the second direction (e.g., an oz direction), wherein a bit line structure 16 extending along the second direction (e.g., an oz direction) and arranged at intervals along the first direction (e.g., an ox direction) is provided above the word line structure 12, wherein the bit line structure 16 also includes structures such as a bit line plug, a bit line barrier layer, and a bit line metal layer.

[0052] Specifically, see Figure 2-Figure 6 , Figure 2-Figure 6 It is a method for preparing a semiconductor structure in the related art. Figure 2First, a substrate and an active layer 10 and an isolation region 11 are provided, a word line structure 12 is located inside the active layer 10 and on both sides of the isolation region 11 along a first direction (eg, ox direction), and a spacer layer 13 is formed on the isolation region 11. Figure 3 , a plug material layer 141 is formed between adjacent spacer layers 13, the plug material layer 141 also covers the top surface of the spacer layer 13, and the plug material layer 141 is electrically connected to the top surface of the active layer 10 exposed between the adjacent spacer layers 13. The plug material layer 141 is usually made of polysilicon material. The resistivity of the polysilicon material and the silicon and other materials in the active layer 10 is quite different, and the contact effect is poor. The contact surface between the two will produce a large contact resistance. Please refer to Figure 4 , the plug material layer 141 is etched to be flush with the spacer layer 13 to form a plurality of bit line plugs 14 separated by the spacer layer 13, and the bit line plugs 14 are electrically connected to the active layer 10. Figure 5 A bit line barrier layer 15 is formed on the top surface of the bit line plug 14. The material of the bit line barrier layer 15 can be a metal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN). Figure 6 , a bit line metal layer 16 is formed on the top surface of the bit line barrier layer 15, and the bit line barrier layer 15 can prevent the metal material in the bit line metal layer 16 from diffusing into the inside of the bit line plug 14. In the above bit line structure, the active layer 10 is connected to the bit line metal layer 16 through the bit line plug 14, and there is also a bit line barrier layer 15 between the bit line metal layer 16 and the bit line plug 14. Due to the miniaturization of the semiconductor structure size and the high resistivity of the bit line plug 14 and the active layer 10 materials, the electrical performance of the semiconductor structure is reduced, thereby reducing the service life of the memory, and the provision of multiple layer structures with different materials and functions in the bit line structure also makes the semiconductor structure preparation process more complicated and the preparation cost higher.

[0053] Based on the above technical problems, the following embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to reduce the contact resistance of the bit line contact plug and simplify the manufacturing process steps of the semiconductor structure, thereby optimizing the electrical performance of the semiconductor structure.

[0054] As an example, see Figure 7 and Figure 8On the one hand, the present disclosure provides a semiconductor structure, including a substrate 20, a bit line contact plug 25 and an insulating structure 24; the substrate 20 includes a plurality of active areas 201 arranged in an array and an isolation structure 202 for defining the active areas 201; the bit line contact plug 25 is arranged corresponding to the active area 201, and adjacent bit line contact plugs 25 are insulated from each other via the insulating structure 24; wherein the bit line contact plug 25 includes a conductive contact plug 252 and an interface layer 251 located between the conductive contact plug 252 and the corresponding active area 201; the resistivity of the conductive contact plug 252 is within a preset range.

[0055] In the semiconductor structure in the above embodiment, the bit line contact plug 25 includes a conductive contact plug 252 and an interface layer 251 between the conductive contact plug 252 and the corresponding active area 201. The interface layer 251 is used as a transition layer between the conductive contact plug 252 and the active area 201 to avoid direct contact between the two and generate a large contact resistance; and the resistivity of the conductive contact plug 252 is within a preset range, and the contact resistance between the bit line contact plug 25 and the active area 201 can be further reduced by reducing the resistivity of the material of the conductive contact plug 252. In the commonly used memory structure, the bit line plug is usually formed directly on the active layer to electrically connect the bit line with the active layer, but since the resistivity difference between the material of the active layer and the material of the bit line plug is generally large, a large contact resistance will be generated between the active layer and the bit line plug, thereby causing current instability, generating heat, etc., and shortening the service life of the memory. By adopting the above-mentioned semiconductor structure provided by the present disclosure, the contact resistance between the bit line contact plug 25 and the active area 201 can be reduced, and the conductive contact plug 252 can be used as a barrier layer between the conductive layer of the bit line at the same time, so as to save the preparation process of the bit line barrier layer in the original bit line structure, thereby improving the yield of the semiconductor structure and reducing its cost, and can also improve the electrical performance of the memory.

[0056] As an example, see Figure 7 and Figure 8 The isolation structure 202 may be a shallow trench isolation structure 202 (STI for short), which is used to isolate the active region 201. The isolation structure 202 may be made of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0057] As an example, see Figure 7 and Figure 8, the preset range is less than 25μΩ·cm. In the related art, the material of the bit line plug is usually polysilicon, and the resistivity of polysilicon is generally above 25μΩ·cm, and is much larger than 25μΩ·cm. Therefore, controlling the resistivity of the conductive contact plug 252 to be less than 25μΩ·cm can reduce its contact resistance with the active area 201. For example, the resistivity of the conductive contact plug 252 is less than or equal to 50% of the resistivity of polysilicon. Specifically, the resistivity of the conductive contact plug 252 can be 25μΩ·cm, 20μΩ·cm, 15μΩ·cm, 10μΩ·cm or 5μΩ·cm, etc.

[0058] As an example, see Figure 7 and Figure 8 , the material of the conductive contact plug 252 includes titanium nitride. The resistivity of titanium nitride is generally in the range of 20μΩ·cm-25μΩ·cm, which is much smaller than the resistivity of polysilicon. Therefore, the conductive contact plug 252 is made of titanium nitride, which can replace polysilicon as the contact structure between the bit line and the active area 201, reduce the resistance of the conductive contact plug 252, and thus improve the performance of the memory. In addition, since titanium nitride itself can be used as a material for the bit line barrier layer, the conductive contact plug 252 is made of titanium nitride. The original bit line barrier layer can be omitted, and it can be used as a barrier layer material for the bit line, saving a layer structure for the bit line structure, thereby reducing the preparation cost of the semiconductor structure, improving the integration of the memory, and improving the electrical performance of the semiconductor structure.

[0059] As an example, see Figure 7 and Figure 8 The material of the interface layer 251 includes titanium silicon alloy (TiSi). Titanium silicon alloy is a high melting point intermetallic compound with many excellent properties such as low resistivity, high thermal stability, low density, good oxidation resistance and chemical stability. As a connection layer and transition layer between the conductive contact plug 252 and the active area 201, it can effectively reduce the contact resistance between the two, thereby improving the connection performance and stability between the bit line and the substrate 20, so as to improve the yield of the semiconductor structure.

[0060] As an example, see Figure 7 and Figure 8, the thickness of the conductive contact plug 252 along the third direction (for example, the oy direction) is greater than or equal to 35nm and less than or equal to 45nm. The conductive contact plug 252 is used as a contact plug between the bit line and the active area 201, and its thickness along the third direction (for example, the oy direction) should be greater than the thickness of the interface layer 251 along the third direction (for example, the oy direction). For example, the thickness of the conductive contact plug 252 along the third direction (for example, the oy direction) is 2-8 times the thickness of the interface layer 251 along the third direction (for example, the oy direction). Specifically, the thickness of the conductive contact plug 252 along the third direction (for example, the oy direction) can be 2 times, 3 times, 4 times, 6 times or 8 times the thickness of the interface layer 251 along the third direction (for example, the oy direction), etc.; the thickness of the conductive contact plug 252 along the third direction (for example, the oy direction) can be 35nm, 37nm, 40nm, 42nm or 45nm, etc.

[0061] As an example, see Figure 7 and Figure 8 The semiconductor structure further includes a bit line 26, which is connected to the bit line contact plug 25, and the bit line 26 extends along a first direction (for example, an ox direction) and is arranged at intervals along a second direction (for example, an oz direction); wherein the first direction (for example, an ox direction) is perpendicular to the second direction (for example, an oz direction). For example, the material of the bit line 26 can be a low-resistance material such as tungsten (W) or ruthenium (Ru) to reduce resistance and increase the operating speed of the device, and other metal materials can also be used, for example, one or more of cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), palladium (Pd), platinum (Pt), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al) can be used.

[0062] As an example, see Figure 7 and Figure 8 The substrate 20 includes a groove corresponding to the active area 201, and the bit line contact plug 25 is connected to the active area 201 exposed by the groove. The interface layer 251 is located on the top surface of the active area 201 exposed by the groove, and the conductive contact plug 252 is located on the top of the interface layer 251 in the groove and between adjacent insulating structures 24 to define the position of the bit line 26.

[0063] In other embodiments, the top surface of the active region 201 may also be flush with the top surface of the isolation structure 202 .

[0064] As an example, see Figure 7 and Figure 8The substrate 20 further includes word lines 21, which are located on opposite sides of the isolation structure 202 along the first direction (e.g., the ox direction). The word lines 21 extend along the second direction (e.g., the oz direction) and are arranged at intervals along the first direction (e.g., the ox direction). The grooves also expose the top surfaces of the word lines 21, and the bit line contact plugs 25 are also connected to the top surfaces of the word lines 21.

[0065] As an example, see Figure 7 and Figure 8 The word line 21 includes a word line conductive layer 211, a word line barrier layer 212 and a word line cap layer 213 stacked in sequence from bottom to top. For example, the material of the word line conductive layer 211 can be one or more of tungsten, ruthenium, cobalt, nickel, titanium, tungsten, tantalum, palladium, platinum, tantalum titanium, tungsten nitride, copper and aluminum; the material of the word line barrier layer 212 can be polysilicon material; the material of the word line cap layer 213 can be one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0066] As an example, see Figure 7 and Figure 8 The substrate 20 further includes a protection layer 22, which is located on the outer surface of the word line 21, the outer surface of the isolation structure 202, and between the word line 21 and the isolation structure 202, and is used to protect the outer surface of the word line 21 and the isolation structure 202. For example, the material of the protection layer 22 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0067] As an example, see Figure 7 and Figure 8 An isolation layer 23 is also included between the bottom surface of the insulating structure 24 and the protective layer 22 on the top surface of the isolation structure 202, and between the bottom surface of the insulating structure 24 and the protective layer 22 on the top surface of the word line 21. The isolation layer 23 is used as the protective layer 22 for the word line 21 and the active area 201.

[0068] As an example, see Fig. 9 On the other hand, the present disclosure also provides a method for preparing a semiconductor structure, comprising:

[0069] Step S2: providing a substrate, wherein the substrate includes a plurality of initial regions arranged in an array and an isolation structure for defining the initial regions;

[0070] Step S4: forming an insulating structure on the top surface of the isolation structure;

[0071] Step S6: forming a seed layer on the top surface of the initial region, and allowing a portion of the initial region connected to the seed layer to react with the seed layer to form an interface layer, and the remaining initial region to form an active region;

[0072] Step S8: forming a conductive contact plug on the interface layer, wherein the resistivity of the conductive contact plug is within a preset range; wherein the conductive contact plug and the interface layer together constitute a bit line contact plug, and adjacent bit line contact plugs are insulated from each other via an insulating structure.

[0073] In the method for preparing the semiconductor structure in the above embodiment, a seed layer is formed on the top surface of the initial region, and a portion of the initial region connected to the seed layer reacts with the seed layer to form an interface layer, and a conductive contact plug is formed on the interface layer. The interface layer is used as a transition layer between the conductive contact plug and the active region to avoid direct contact between the two and generate a large contact resistance; and the resistivity of the conductive contact plug is within a preset range, and the contact resistance between the bit line contact plug and the active region can be further reduced by reducing the resistivity of the material of the conductive contact plug. In the semiconductor structure preparation process used in the related art, the bit line plug is usually formed directly on the active layer, and a barrier layer is formed between the bit line plug and the bit line metal layer to electrically connect the bit line metal layer to the active layer and prevent the diffusion of material molecules in the bit line metal layer. However, since the resistivity difference between the material of the active layer and the material of the bit line plug is generally large, a large contact resistance will be generated between the active layer and the bit line plug, thereby shortening the service life of the memory and increasing the preparation cost. By adopting the above-mentioned preparation method provided by the present disclosure, the interface layer formed by the reaction between the seed layer and the top surface of the initial area can be utilized to reduce the contact resistance between the conductive contact plug and the active area, and the conductive contact plug can also be used as a barrier layer between the plug and the conductive layer at the same time, so as to save the preparation process of the barrier layer in the original bit line structure, thereby improving the yield of the semiconductor structure, improving the preparation efficiency, reducing the preparation cost and improving its electrical performance.

[0074] As an example, in step S2, see Fig. 9 Step S2 in Fig.10 and Fig.11 , providing a substrate, the substrate including a plurality of initial regions 2011 arranged in an array and an isolation structure 202 for defining the initial regions 2011. Specifically, the isolation structure 202 may be a shallow trench isolation structure 202 for isolating the active region 201. The material of the isolation structure 202 may be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0075] The above-mentioned substrate can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a III / V semiconductor substrate or a II / VI semiconductor substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other. Or, for example, the substrate can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Those skilled in the art can select the type of substrate according to the type of transistor formed on the substrate, and therefore, the type of substrate should not limit the scope of protection of the present application.

[0076] As an example, see Fig.11 The substrate includes grooves corresponding to the active regions 201 , and the bit line contact plugs 25 are connected to the active regions 201 exposed by the grooves. In other embodiments, the top surface of the active region 201 may also be flush with the top surface of the isolation structure 202 .

[0077] As an example, in step S4, see Fig. 9 Step S4 in Fig.10 and Fig.11 , an insulating structure 24 is formed on the top surface of the isolation structure 202; wherein the grooves may be formed before forming the insulating structure 24, or may be formed while forming the insulating structure 24, and the grooves and the insulating structure 24 are alternately arranged along a first direction (eg, ox direction).

[0078] As an example, see Fig.10 An isolation layer 23 is further provided between the bottom surface of the insulating structure 24 and the protection layer 22 on the top surface of the isolation structure 202, and between the bottom surface of the insulating structure 24 and the protection layer 22 on the top surface of the word line 21. The isolation layer 23 can be formed after the protection layer 22 is formed and before the insulating structure 24 is formed.

[0079] As an example, forming a seed layer in step S6 includes:

[0080] Step S61: forming a seed layer on the top surface of the initial area using a chemical vapor deposition process.

[0081] In step S61, refer to Fig. 9 Step S6 in Fig.11 and Fig.12, a seed layer is formed on the top surface of the initial region 2011 by a chemical vapor deposition process. Specifically, the seed layer can be gradually formed on the top surface of the initial region 2011, so that the seed layer contacts the initial region 2011 and chemically reacts with the initial region 2011 under preset process conditions to form an interface layer 251 on the top surface of the initial region 2011. The material of the interface layer 251 is composed of the material in the seed layer and the material in the initial region 2011. Since a part of the material on the top of the initial region 2011 reacts with the seed layer to form the interface layer 251, the remaining unreacted material in the initial region 2011 forms the active region 201. The top surface of the active region 201 is covered by the interface layer 251, and the interface layer 251 is exposed at the bottom of the groove. The contact resistance between the interface layer 251 and the active region 201 is reduced, so as to reduce the contact resistance between the active region 201 and the bit line structure and improve the electrical performance of the semiconductor structure.

[0082] As an example, in step S61, see Fig.11 and Fig.12 Specifically, chemical vapor deposition is used to introduce a gaseous reactant containing a thin film-constituting element, i.e., titanium, into a reaction chamber, causing it to undergo a chemical reaction on the surface of the initial region 2011, thereby generating the desired solid thin film of the interface layer 251 and depositing it on the top surface of the initial region 2011, thereby forming a thin film covering the active region 201, so as to reduce the contact resistance between the active region 201 and the conductive contact plug 252.

[0083] As an example, see Fig.12 , the thickness of the seed layer is greater than or equal to 5nm and less than or equal to 7nm. The seed layer is used to react with the material of the initial area 2011 to obtain an interface layer 251 with low resistivity. For example, the thickness of the seed layer can be 5nm, 5.5nm, 6nm, 6.5nm or 7nm, etc.

[0084] As an example, see Fig.12 The material of the seed layer includes metal titanium, the material of the initial region 2011 includes silicon, the seed layer is formed on the top of the initial region 2011, and reacts with the material of the initial region 2011 in contact with it to form an interface layer 251 on the top of the initial region 2011. Therefore, the material of the interface layer 251 is titanium-silicon alloy. The titanium-silicon alloy is used as a conductive contact plug 252 (see Fig.13 ) and the active area 201, can effectively reduce the contact resistance between the two, thereby improving the connection performance and stability between the bit line and the substrate 20, so as to improve the yield of the semiconductor structure and the stability of the electrical performance.

[0085] As an example, forming a conductive contact plug in step S8 includes:

[0086] Step S81: forming a conductive contact plug on the interface layer by using an atomic layer deposition (ALD) process.

[0087] In step S81, refer to Fig. 9 Step S8 in Fig.12 and Fig.13 , firstly, a contact material layer 2521 is formed in the groove, the bottom surface of the contact material layer 2521 contacts the top surface of the interface layer 251, and the contact material layer 2521 also covers the outer side wall and the top surface of the insulating structure 24; then, the contact material layer 2521 located on the top surface of the insulating structure 24 is removed, so that the top surface of the contact material layer 2521 is flush with the top surface of the insulating structure 24, so as to form a plurality of conductive contact plugs 252, and each conductive contact plug 252 is isolated from each other by the insulating structure 24. Specifically, the method of removing the contact material layer 2521 can be through an etch-back process, and the etch-back process can include wet etching, dry etching or chemical mechanical polishing (CMP) and other process means.

[0088] As an example, see Fig.12 The material of the contact material layer 2521 includes titanium nitride. The resistivity of titanium nitride is generally in the range of 20μΩ·cm-25μΩ·cm, which is much smaller than the resistivity of polysilicon. Therefore, the material of the contact material layer 2521 is titanium nitride, so that the material of the conductive contact plug 252 can also be titanium nitride, replacing polysilicon as the contact structure between the bit line and the active area 201, reducing the resistance of the conductive contact plug 252, and thus improving the performance of the memory; it can also be used as the material of the bit line barrier layer, saving a layer structure for the bit line structure, thereby reducing the preparation cost of the semiconductor structure and improving the stability of the bit line.

[0089] As an example, see Fig.13 , the thickness of the conductive contact plug 252 is greater than or equal to 35nm and less than or equal to 45nm. The conductive contact plug 252 is used as a contact plug between the bit line and the active area 201, and its thickness should be greater than the thickness of the interface layer 251. For example, the thickness of the conductive contact plug 252 is 2-8 times the thickness of the interface layer 251. Specifically, the thickness of the conductive contact plug 252 can be 2 times, 3 times, 4 times, 6 times or 8 times the thickness of the interface layer 251, etc.; the thickness of the conductive contact plug 252 can be 35nm, 37nm, 40nm, 42nm or 45nm, etc.

[0090] As an example, atomic layer deposition is a type of chemical vapor deposition (CVD), which is a new type of thin film deposition technology with the advantages of excellent film uniformity, excellent film density, high film purity, excellent step coverage, and low-temperature deposition. The atomic layer deposition system can control the film thickness by controlling the number of reaction cycles, thereby obtaining a film with a preset atomic layer thickness accuracy; and because the precursor is saturated with chemical adsorption, it can ensure the generation of a large area uniform film to form a high-quality conductive contact plug 252. The atomic layer deposition method can make the thickness of the obtained conductive contact plug 252 more uniform.

[0091] As an example, the conductive contact plug 252 may also be manufactured by one or more methods such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0092] As an example, see Fig.13 The word line 21 includes a word line conductive layer 211, a word line barrier layer 212, and a word line capping layer 213 stacked sequentially from bottom to top. The steps of forming the word line 21 may include: forming a word line groove in the initial area 2011 or the active area 201 on both sides of the isolation structure 202 along the first direction (for example, the ox direction); wherein the depth of the word line groove is less than the thickness of the isolation structure 202; then, forming a word line conductive layer 211, a word line barrier layer 212, and a word line capping layer 213 stacked sequentially from bottom to top in the word line groove; when the groove is subsequently formed, the groove exposes the word line capping layer 213. For example, the material of the word line conductive layer 211 can be one or more of tungsten, ruthenium, cobalt, nickel, titanium, tungsten, tantalum, palladium, platinum, tantalum titanium, tungsten nitride, copper and aluminum; the material of the word line blocking layer 212 can be polysilicon material; the material of the word line cap layer 213 can be one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0093] It should be understood that although Fig. 9 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, although Fig. 9At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0094] As an example, after forming the conductive contact plug in step S8, the step further includes:

[0095] Step S9: forming bit lines on the top surfaces of the bit line contact plugs, wherein the bit lines extend along a first direction and are arranged at intervals along a second direction; wherein the first direction is perpendicular to the second direction.

[0096] As an example, in step S9, see Fig.14 , the bit line 26 extending along the first direction (for example, the ox direction) alternately covers the top of the conductive contact plug 252 and the top of the insulating structure 24, and the portion of the bit line 26 covering the top of the conductive contact plug 252 contacts the active area 201 and the word line 21 directly below it through the conductive contact plug 252, and is used to constitute a component of a storage unit in the memory. Since the conductive contact plug 252 can also serve as a bit line barrier layer, the bit line 26 can be directly formed on the conductive contact plug 252 in the present disclosure to simplify the process steps and save process raw materials, thereby improving the electrical performance of the semiconductor structure while also improving the preparation efficiency of the semiconductor structure. Specifically, the material of the bit line 26 can be a low-resistance material such as tungsten or ruthenium to reduce resistance and increase the operating speed of the device, and other metal materials can also be used, for example, one or more of cobalt, nickel, titanium, tantalum, palladium, platinum, tantalum titanium, tungsten nitride, copper and aluminum can be used.

[0097] As an example, after forming the bit line in step S9, the step further includes:

[0098] Step S10: forming a bit line capping layer on the top surface of the bit line, wherein the bit line capping layer at least covers the top surface of the bit line.

[0099] As an example, in step S10, please continue to refer to Fig.14 The bit line capping layer 27 is used to protect the top surface of the bit line 26 , and the material of the bit line capping layer 27 includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0100] As an example, see Fig.14 A capacitor plug may be formed between adjacent bit lines 26, and a capacitor (not shown) extending along a third direction (eg, oy direction) may be formed on a top surface of the capacitor plug to form a storage structure.

[0101] In the above-mentioned semiconductor structure preparation method and semiconductor structure, the present disclosure utilizes the interface layer formed by the reaction between the seed layer and the top surface of the initial region, and uses the conductive contact plug as a barrier layer between the plug and the conductive layer at the same time. The bit line contact plug in the present disclosure includes a conductive contact plug, and an interface layer between the conductive contact plug and the active area directly below it, so that the contact resistance between the active area and the bit line contact plug can be reduced; at the same time, the conductive contact plug is also used as a bit line barrier layer, so that the bit line layer can be directly formed on the top of the conductive contact plug, so as to save the process steps of preparing the barrier layer in the related art, thereby improving the preparation efficiency of the semiconductor structure, and also reducing the preparation cost. Due to the reduction of the contact resistance between the active layer and the bit line plug, the stability of the current is improved, the heat generation of the device is reduced, and the power consumption is reduced, thereby extending the service life of the memory, so as to obtain a memory device with better electrical performance.

[0102] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0103] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0104] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the disclosed patent shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: It includes a substrate, a bit line contact plug and an insulating structure; The substrate includes a plurality of active areas arranged in an array and an isolation structure for defining the active areas; The bit line contact plugs are arranged corresponding to the active area, and the adjacent bit line contact plugs are insulated from each other via the insulating structure; The bit line contact plug includes a conductive contact plug and an interface layer between the conductive contact plug and a corresponding active area; the resistivity of the conductive contact plug is within a preset range.

2. The semiconductor structure according to claim 1, characterized in that: The preset range is less than 25 μΩ·cm.

3. The semiconductor structure according to claim 1, characterized in that: The material of the conductive contact plug includes titanium nitride.

4. The semiconductor structure according to claim 1, characterized in that The material of the interface layer includes titanium silicon alloy.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The thickness of the conductive contact plug is greater than or equal to 35 nm and less than or equal to 45 nm.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that: Also includes: A bit line is connected to the bit line contact plug, and the bit line extends along a first direction and is arranged at intervals along a second direction; wherein the first direction is perpendicular to the second direction.

7. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The top surface of the active region is flush with the top surface of the isolation structure; or The substrate includes a groove arranged corresponding to the active area, and the bit line contact plug is connected to the active area exposed by the groove.

8. The semiconductor structure according to claim 6, characterized in that: The substrate also includes: The word lines are located at two opposite sides of the isolation structure along the first direction. The word lines extend along the second direction and are arranged at intervals along the first direction.

9. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate includes a plurality of initial regions arranged in an array and an isolation structure for defining the initial regions; forming an insulating structure on a top surface of the isolation structure; forming a seed layer on the top surface of the initial region, and allowing a portion of the initial region connected to the seed layer to react with the seed layer to form an interface layer, and the remaining initial region to form an active region; A conductive contact plug is formed on the interface layer, wherein the resistivity of the conductive contact plug is within a preset range; wherein the conductive contact plug and the interface layer together constitute a bit line contact plug, and adjacent bit line contact plugs are insulated from each other via the insulating structure.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: Forming the seed layer comprises: forming the seed layer on the top surface of the initial region by a chemical vapor deposition process; and / or Forming the conductive contact plug includes: The conductive contact plug is formed on the interface layer by an atomic layer deposition process.

11. The method for preparing a semiconductor structure according to claim 9 or 10, characterized in that: The thickness of the seed layer is greater than or equal to 5 nm and less than or equal to 7 nm.

12. The method for preparing a semiconductor structure according to claim 9 or 10, characterized in that: The material of the seed layer includes metal titanium.

13. The method for preparing a semiconductor structure according to claim 9 or 10, characterized in that: The material of the conductive contact plug includes titanium nitride.

14. The method for preparing a semiconductor structure according to claim 9 or 10, characterized in that: After forming the conductive contact plug, the method further includes: A bit line is formed on the top surface of the bit line contact plug, and the bit line extends along a first direction and is arranged at intervals along a second direction; wherein the first direction is perpendicular to the second direction.

15. The method for preparing a semiconductor structure according to claim 9 or 10, characterized in that: The top surface of the active region is flush with the top surface of the isolation structure; or The substrate includes grooves arranged corresponding to the active regions, and the bit line contact plugs are connected to the active regions exposed by the grooves.

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