Method for removing dummy gate in high-k metal gate process

Abstract

The invention provides a method for removing a dummy gate in a high-k metal gate process, and the method comprises the steps: 1, providing a substrate, and sequentially forming the dummy gate, a contact hole etching stop layer and an interlayer dielectric layer on the substrate; step 2, removing part of the dummy gate; step 3, performing irradiation treatment to enable the interlayer dielectric layer to have a porous structure and convert the shape of the dummy gate into an inverted trapezoid shape at the same time; and step 4, removing the residual dummy gate. When the dummy gate is removed, irradiation treatment is carried out to change the stress distribution of the interlayer dielectric layer, and the bottom chamfer morphology of the dummy gate is converted into an inverted trapezoidal morphology, so that the etching time is shortened, no polycrystalline silicon residue is formed, and the reliability of the device is improved at the same time.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for removing a dummy gate in a high-k metal gate process. Background Art

[0002] In the existing high-k metal gate process, the dummy gate is removed by dry etching. The hydrogen plasma in the dry etching process causes rich Si-H covalent bonds to form at the silicon interface, which makes the negative bias temperature instability (NBTI) of the device worse. In order to solve this problem, the method of reducing the over-etching time of the dry etching process is usually adopted. However, reducing the over-etching time will increase the risk of polysilicon residue, so the existing process cannot take into account both device reliability and process window at the same time. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for removing a dummy gate in a high-k metal gate process, so as to solve the problem that the prior art cannot take into account both device reliability and process window when removing the dummy gate.

[0004] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for removing a dummy gate in a high-k metal gate process, comprising:

[0005] Step 1, providing a substrate, and sequentially forming a dummy gate, a contact hole etching stop layer and an interlayer dielectric layer on the substrate;

[0006] Step 2, removing part of the dummy gate;

[0007] Step 3, performing irradiation treatment to make the interlayer dielectric layer have a porous structure and transform the morphology of the dummy gate into an inverted trapezoid;

[0008] Step 4: remove the remaining dummy gate.

[0009] Preferably, in step 2, a portion exceeding half of the height of the dummy gate is removed.

[0010] Preferably, the process conditions of the irradiation treatment in step three include: ultraviolet light irradiation time 60s-300s, temperature 200°C-400°C.

[0011] Preferably, the ultraviolet light irradiation time is adjusted according to the thickness of the interlayer dielectric layer.

[0012] Preferably, the material of the interlayer dielectric layer is a material having a low dielectric constant that can be transformed into a porous structure by radiation treatment.

[0013] Preferably, the material of the contact hole etching stop layer includes silicon nitride.

[0014] Preferably, in step 2 and step 4, the dummy gate is removed by an etching process.

[0015] Preferably, the etching process is dry etching.

[0016] Preferably, sidewall structures are formed on both sides of the dummy gate.

[0017] Preferably, an interface layer and a high-K dielectric layer are stacked from bottom to top and formed below the dummy gate.

[0018] As described above, the method for removing the dummy gate in the high-k metal gate process provided in the present application has the following beneficial effects: when removing the dummy gate, irradiation treatment is implemented to change the stress distribution of the interlayer dielectric layer, and the bottom chamfer morphology of the dummy gate is transformed into an inverted trapezoidal morphology, thereby shortening the etching time without forming polysilicon residue, and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 (a) shows the comparison of NBTI under different over-etching times;

[0021] Figure 1 (b) An electron photograph showing the residual formed at the polysilicon chamfer by reducing the over-etching time using the existing dummy gate removal process;

[0022] Figure 2 A flow chart showing a method for removing a dummy gate in a high-k metal gate process provided by an embodiment of the present application;

[0023] Figure 3A-3D Shown is a schematic diagram of a device cross-sectional structure formed after each step is completed in a method for removing a dummy gate in a high-k metal gate process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0028] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0029] like Figure 1 As shown in (a), when the over-etching (OE) time is reduced, the NBTI increases significantly and the device reliability becomes stronger. Figure 1 As shown in (b), when the over-etching time is reduced, polysilicon residue is likely to occur at the bottom chamfer of the dummy gate, that is, the etching process window becomes smaller. Therefore, the existing dummy gate removal process cannot take into account both device reliability and process window at the same time.

[0030] In order to solve this problem, the present application provides a method for removing a dummy gate in a high-k metal gate process.

[0031] See also Figure 2 , which shows a flow chart of a method for removing a dummy gate in a high-k metal gate process provided in an embodiment of the present application.

[0032] like Figure 2 As shown, the method for removing the dummy gate in the high-k metal gate process includes the following steps:

[0033] Step 1, providing a substrate, and sequentially forming a dummy gate, a contact hole etching stop layer and an interlayer dielectric layer on the substrate;

[0034] Step 2, removing part of the dummy gate;

[0035] Step 3, performing irradiation treatment to make the interlayer dielectric layer have a porous structure and transform the morphology of the dummy gate into an inverted trapezoid;

[0036] Step 4: remove the remaining dummy gate.

[0037] In step one, if Figure 3A As shown, optionally, the substrate 300 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate 300 may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate 300 according to the type of device structure formed on the substrate 300, so the type of the substrate 300 should not limit the protection scope of the present invention.

[0038] As an example, the steps of forming a dummy gate 301 on a substrate 300 include: forming a dummy gate material layer (usually a polysilicon layer) on the substrate 300 by a deposition process; forming a mask layer having a dummy gate 301 pattern on the dummy gate material layer by deposition, photolithography and etching processes; using the mask layer as a mask, etching the dummy gate material layer to form the dummy gate 301; and removing the mask layer.

[0039] After forming the dummy gate 301, a sidewall structure 302 is formed on both sides of the dummy gate 301. Exemplarily, the sidewall structure 302 is composed of silicon oxide, silicon nitride, or a stacked combination of the two. An interface layer and a high-K dielectric layer stacked from bottom to top are also formed below the dummy gate 301 (not shown in the figure for simplicity).

[0040] After the sidewall structure 302 is formed, a contact hole etching stop layer 303 and an interlayer dielectric layer 305 are sequentially formed on the substrate 300 through a deposition process. After the deposition is completed, a grinding process is performed until the dummy gate 301 and the top of the sidewall structure 302 are exposed.

[0041] As an example, the material of the contact hole etching stop layer 303 includes silicon nitride. The material of the interlayer dielectric layer 305 is selected from a material with a low dielectric constant (<3.9) that can be transformed into a porous structure by subsequent irradiation treatment, such as BDII (a dielectric material composed of elements such as C, H, O, and Si).

[0042] In step 2, if Figure 3B As shown, part of the dummy gate 301 is removed by an etching process. Exemplarily, the etching process is dry etching.

[0043] In order to ensure that the subsequent step three can more effectively transform the morphology of the dummy gate into an inverted trapezoid, the removed portion should exceed half of the height of the dummy gate 301 .

[0044] In step three, as an example, the process conditions of the irradiation treatment include: ultraviolet light irradiation time of 60s-300s (the time can be adjusted according to the thickness of the interlayer dielectric layer 305), and temperature of 200°C-400°C.

[0045] After the irradiation treatment, the interlayer dielectric layer 305 is transformed into a porous structure (density is weakened), and the stress generated by the contact hole etching stop layer 303 is applied to the interlayer dielectric layer 305, so that the morphology of the remaining pseudo gate 301 is transformed into an inverted trapezoidal shape, such as Figure 3C As shown, the bottom chamfer of the dummy gate is eliminated to avoid the formation of polysilicon residues when the subsequent step four is implemented.

[0046] In step 4, the remaining dummy gate 301 is removed by an etching process. Exemplarily, the etching process is dry etching. Figure 3D As shown, no polysilicon residue is formed after etching is completed.

[0047] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] In summary, the method for removing the dummy gate in the high-k metal gate process of the present application implements irradiation treatment to change the stress distribution of the interlayer dielectric layer when removing the dummy gate, transforms the bottom chamfer morphology of the dummy gate into an inverted trapezoidal morphology, shortens the etching time while not forming polysilicon residue, and improves device reliability. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0049] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.

Claims

1. A method for removing a dummy gate in a high-k metal gate process, characterized in that: The method comprises: Step 1, providing a substrate, and sequentially forming a dummy gate, a contact hole etching stop layer and an interlayer dielectric layer on the substrate; Step 2, removing part of the dummy gate; Step three, performing irradiation treatment to make the interlayer dielectric layer have a porous structure and transform the morphology of the dummy gate into an inverted trapezoid; Step 4: remove the remaining dummy gate.

2. The method according to claim 1, characterized in that In the step 2, the removed portion exceeds half of the height of the dummy gate.

3. The method according to claim 1, characterized in that The process conditions of the irradiation treatment in step three include: ultraviolet light irradiation time of 60s-300s and temperature of 200°C-400°C.

4. The method according to claim 3, characterized in that The ultraviolet light irradiation time is adjusted according to the thickness of the interlayer dielectric layer.

5. The method according to claim 1, characterized in that The material of the interlayer dielectric layer is selected from a material having a low dielectric constant that can be transformed into a porous structure through the radiation treatment.

6. The method according to claim 1, characterized in that The material of the contact hole etching stop layer includes silicon nitride.

7. The method according to claim 1, characterized in that In the step 2 and the step 4, the dummy gate is removed by an etching process.

8. The method according to claim 7, characterized in that The etching process is dry etching.

9. The method according to claim 1, characterized in that: Sidewall structures are formed on both sides of the dummy gate.

10. The method according to claim 1, characterized in that An interface layer and a high-K dielectric layer are stacked from bottom to top and are formed below the dummy gate.

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