Fast recovery diode, preparation method and preparation system thereof, and storage medium

Abstract

The invention discloses a fast recovery diode, a preparation method and a preparation system thereof, and a storage medium, and belongs to the field of electronic equipment. The front surface of the diode is provided with a P-type active region, a terminal P-type region, and an oxide layer and front surface metal covering the P-type active region and the terminal P-type region; and the back surface is provided with P-type ion implantation regions which are arranged at intervals and have narrow upper parts and wide lower parts. The method comprises the following steps: carrying out Taiko thinning on an N-type semiconductor substrate to a target thickness; carrying out photoetching and ion implantation on the front surface of the wafer; turning over the wafer, and carrying out photoetching and P-type ion implantation on the back surface of the wafer again; carrying out annealing treatment on the wafer; sequentially carrying out etching and deposition processes on the front surface of the wafer; performing ion implantation on the back surface of the wafer; and performing an electron irradiation process on the wafer. According to the fast recovery diode and the preparation method thereof provided by the invention, the effects of high diode reliability and high injected effective hole concentration can be achieved.

Description

Technical Field

[0001] The invention relates to electronic equipment, in particular to a fast recovery diode and a preparation method, a preparation system and a storage medium thereof. Background Art

[0002] In modern high-power wind power, photovoltaic inverters, and energy storage converter applications, diodes are important components for freewheeling, and their dynamic avalanche capability affects the basic performance of the device. Poor dynamic avalanche capability can easily lead to sudden failure of diodes under extreme conditions.

[0003] To solve this problem, the industry started with back-side lithography and designed a structure similar to the traditional FCE to improve the dynamic avalanche performance. At the test level, it can suppress small current oscillations to a certain extent and reduce voltage spikes or current slopes. However, since a part of the back side is a P-type region, it also brings a significant increase in the on-state voltage drop. The proportion of the injected P-type region has a greater impact on the on-state voltage drop, and the reliability of the diode is not high. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide a fast recovery diode with high diode reliability and high injection effective hole concentration, and a preparation method, preparation system, and storage medium thereof.

[0005] Technical solution: The fast recovery diode described in the present invention includes a front side and a back side, wherein the front side has a P-type active area, a terminal P-type area, and an oxide layer and a front metal covering the P-type active area and the terminal P-type area; the back side has P-type ion implantation areas which are arranged at intervals and present a narrow upper and wide lower morphology, an N-type substrate area is connected to the P-type ion implantation area, a back side N-type area covers one side of the P-type ion implantation area, and the other side of the back side N-type area is connected to the back side metal.

[0006] Preferably, the P-type active region and the terminal P-type region can be formed by photolithography once, or can be formed successively by photolithography twice.

[0007] Preferably, the effective junction depth formed by the P-type ion implantation region is 5 to 10 μm;

[0008] Further preferably, the effective junction depth formed by the P-type ion implantation region is 7 μm;

[0009] A method for preparing a fast recovery diode according to the present invention comprises the following steps:

[0010] The N-type semiconductor substrate is subjected to Taiko thinning to a target thickness;

[0011] Photolithography and ion implantation are performed on the front side of the wafer;

[0012] Flip the wafer and perform photolithography and P-type ion implantation on the back of the wafer again;

[0013] Anneal the wafer and activate the ions implanted on the front and back sides;

[0014] Performing etching and deposition processes on the front side of the wafer in sequence;

[0015] Ion implantation is performed on the back of the wafer to form a high-concentration N-type region and back metal;

[0016] The wafer is subjected to an electron irradiation process and annealing.

[0017] Preferably, the resistivity of the N-type substrate is 30-90Ωcm, which may be but is not limited to 30Ωcm, 40Ωcm, 50Ωcm, 60Ωcm, 70Ωcm, 80Ωcm, 90Ωcm, and is preferably 30Ωcm; the wafer thinning thickness is 50-130μm, which may be but is not limited to 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 110μm, 120μm, 130μm, and is preferably 65μm.

[0018] Preferably, the ion implantation is performed using boron ion implantation, with a dose of 1e12 to 1e14 cm -2 , can be but not limited to 1e12cm -2 、1e13cm -2 、1e14cm -2 , preferably 1e14cm -2 .

[0019] Preferably, during the annealing process of the wafer, 1200-1250°C is used for pushing and bonding, preferably 1200°C; the pushing and bonding time is 200-500 minutes, which can be but is not limited to 200min, 300min, 400min, 500min, preferably 300min.

[0020] Preferably, phosphorus is used in the high-concentration N-type region on the back of the wafer, with an implantation dose of 5e14 to 3e15 cm -2 , can be but not limited to 5e14cm -2 、6e14cm -2 、7e14cm -2 、8e14cm -2 , 1e15 cm -2 , 2e15 cm -2 、3e15cm -2 , preferably 1e15 cm -2 .

[0021] Preferably, in the electron irradiation process, the electron irradiation dose is selected from 10 to 90 KGY, which can be but is not limited to 10 KGY, 20 KGY, 30 KGY, 40 KGY, 50 KGY, 60 KGY, 70 KGY, 80 KGY, 90 KGY, preferably 70 KGY.

[0022] The fast recovery diode manufacturing system of the present invention comprises the following modules:

[0023] Thinning module: N-type semiconductor substrate, Taiko thinning to target thickness;

[0024] A primary lithography module, used for lithography and ion implantation on the front side of the wafer;

[0025] The secondary photolithography module is used to flip the wafer and perform photolithography and P-type ion implantation on the back of the wafer again;

[0026] Annealing module, used to anneal the wafer and activate the ions implanted on the front and back sides;

[0027] An etching and deposition module is used to sequentially perform etching and deposition processes on the front side of the wafer;

[0028] Ion implantation module, used for ion implantation on the back of the wafer to form a high-concentration N-type area and back metal;

[0029] The electron irradiation module is used to perform electron irradiation process on the wafer and perform annealing.

[0030] The computer-readable storage medium of the present invention stores a computer program, and the computer program implements the above-mentioned fast recovery diode method when executed by a processor.

[0031] Principle of the invention: By introducing a P-type region on the back side, sufficient holes are provided to maintain a certain concentration of carriers during the reverse recovery process of the device, while reducing the high electric field at the back side FS, thereby suppressing the oscillation phenomenon when a small current is turned off.

[0032] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: (1) The present invention completes the formation of the back structure in advance through the two-step operation of S3 and S4, forming a structure with a deeper junction depth. The junction depth formed by this method is 5-10μm. The greater junction depth can, on the one hand, make the effective hole concentration injected higher, and on the other hand, make the reliability of the diode higher; (2) Under the premise of ensuring the back hole injection efficiency, the present invention does not need to increase the on-state voltage drop of the device as a price, and the process is simple and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of the overall appearance of the diode of the present invention;

[0034] Figure 2 The figure is a schematic flow chart of the method for preparing the diode of the present invention;

[0035] Figure 3 Schematic diagram of the N-type substrate structure obtained in step S1;

[0036] Figure 4 Schematic diagram of the N-type substrate structure obtained in step S2;

[0037] Figure 5 This is a schematic diagram of the N-type substrate structure obtained in step S3;

[0038] Figure 6 This is a schematic diagram of the N-type substrate structure obtained in step S4;

[0039] Figure 7 This is a schematic diagram of the N-type substrate structure obtained in step S5;

[0040] Figure 8 This is a schematic diagram of the N-type substrate structure obtained in step S6;

[0041] Fig. 9 This is a schematic diagram of the N-type substrate structure obtained in step S7. DETAILED DESCRIPTION

[0042] The technical solution of the present invention is further described below in conjunction with embodiments.

[0043] Example 1

[0044] like Figure 1 As shown, the fast recovery diode described in the present invention includes a front side and a back side, and is characterized in that the front side has a P-type active area 1, a terminal P-type area 2, and an oxide layer 3 and a front metal 4 covering the P-type active area 1 and the terminal P-type area 2; the back side has P-type ion implantation areas 5 which are arranged at intervals and present a narrow upper and wide lower morphology, an N-type substrate area 6 connected to the P-type ion implantation area 5, a back side N-type area 7 covering one side of the P-type ion implantation area 5, and the other side of the back side N-type area 7 connected to the back side metal 8.

[0045] like Figure 2-9 As shown, the method for preparing the fast recovery diode of the present invention comprises the following steps:

[0046] S1: Based on an N-type semiconductor substrate, a FZ silicon wafer with a substrate resistivity of 30Ωcm is used for Taiko thinning to a thickness of 65μm. The schematic diagram of the N-type substrate structure is shown in the figure. Figure 3 shown.

[0047] S2: Photolithography is performed on the front side of the wafer, based on boron ion implantation, with a dose of 1e14cm-2 , forming an anode terminal P-type region and a P-type active region, such as Figure 4 shown.

[0048] S3: Flip the wafer, perform photolithography on the back of the wafer again, and then perform boron ion implantation, such as Figure 5 shown.

[0049] S4: Send the wafer into a high-temperature furnace tube for annealing. The annealing temperature is 1200°C and the annealing time is 300 minutes. The ions injected on the front and back sides are activated to form an anode active area and a terminal area on the front side and a cathode P-type area on the back side. The junction depth can reach 7μm. Figure 6 shown.

[0050] S5: Perform wafer front etching and deposition processes in sequence to form through holes and front metal, such as Figure 7 shown.

[0051] S6: Ion implantation is performed on the back side of the wafer, and the dose is selected to be 1e15cm -2 , forming a high-concentration N-type region and back metal. The high-concentration N-type region on the back compensates for the impurities in the P-type region to ensure that the back is a complete N-type region. Figure 8 shown.

[0052] S7: The wafer is subjected to electron irradiation process with an irradiation dose of 70KGY. After irradiation, high temperature annealing is performed at a temperature of 350°C to effectively control the final minority carrier lifetime. Fig. 9 shown.

[0053] Junction depth test method: This value can be obtained by testing the SRP junction depth through equipment.

[0054] Example 2

[0055] The same parts of this embodiment as those of embodiment 1 are not described in detail, and the differences are as follows:

[0056] In step S4, the annealing temperature is 1200°C and the annealing time is 200 minutes. The ions injected into the front and back sides are activated to form an anode active area and a terminal area on the front side and a cathode P-type area on the back side. The junction depth can reach 6.2 μm.

[0057] Comparative Example 1

[0058] The same parts as those in Example 1 are not described in detail here, except that:

[0059] In step S4, the annealing temperature is 1100°C and the annealing time is 300 minutes. The ions injected into the front and back sides are activated to form an anode active area and a terminal area on the front side and a cathode P-type area on the back side. The junction depth can reach 4.5 μm.

[0060] It can be seen from the experimental results of Examples 1-2 and Comparative Example 1 that the annealing temperature and annealing time in step S4 are key parameters in this process. The annealing temperature is within the range of 1200-1250°C and the annealing time is within the range of 200-500min to achieve the beneficial effect of an effective junction depth of 5 to 10 μm formed in the P-type ion implantation region of the diode described in the present invention.

[0061] In the traditional process, after the P-type ion implantation is performed on the back side, the front process structure has been formed, and high temperature annealing cannot be performed, and a diode with a deeper junction depth cannot be obtained. However, the present invention completes the formation of the back structure in advance through the two-step operation of S3 and S4, forming a structure with a deeper junction depth, thereby suppressing small current oscillations. The junction depth formed by this method is 5-10μm, while the junction depth of the traditional method is less than 1μm. A larger junction depth can, on the one hand, increase the concentration of injected effective holes, and on the other hand, increase the reliability of the diode.

Claims

1. A fast recovery diode, comprising a front side and a back side, characterized in that: The front side has a P-type active area (1), a terminal P-type area (2), and an oxide layer (3) and a front metal (4) covering the P-type active area (1) and the terminal P-type area (2); the back side has P-type ion implantation areas (5) arranged at intervals and presenting a top narrow and bottom wide morphology, an N-type substrate area (6) connected to the P-type ion implantation area (5), a back side N-type area (7) covering one side of the P-type ion implantation area (5), and the other side of the back side N-type area (7) connected to the back side metal (8).

2. The fast recovery diode according to claim 1, characterized in that: The P-type active region (1) and the terminal P-type region (2) can be formed by photolithography once, or can be formed by photolithography twice in sequence.

3. The fast recovery diode according to claim 1, characterized in that: The effective junction depth formed by the P-type ion implantation region (5) is 5 to 10 μm.

4. A method for preparing a fast recovery diode according to claim 1, characterized in that: The steps include: The N-type semiconductor substrate is subjected to Taiko thinning to a target thickness; Photolithography and ion implantation are performed on the front side of the wafer; Flip the wafer and perform photolithography and P-type ion implantation on the back of the wafer again; Anneal the wafer and activate the ions implanted on the front and back sides; Performing etching and deposition processes on the front side of the wafer in sequence; Ion implantation is performed on the back of the wafer to form a high-concentration N-type region and back metal; The wafer is subjected to an electron irradiation process and annealing.

5. The method for preparing a fast recovery diode according to claim 4, characterized in that: The resistivity of the N-type substrate is 30-90Ωcm, and the wafer thinning thickness is 50-130μm; the ion implantation adopts boron ion implantation, and the selected dose is 1e12-1e14cm -2 .

6. The method for preparing a fast recovery diode according to claim 4, characterized in that: In the annealing process of the wafer, 1200-1250° C. is used for annealing, and the annealing time is 200-500 minutes.

7. The method for preparing a fast recovery diode according to claim 4, characterized in that: The high concentration N-type area on the back of the wafer adopts phosphorus, and the implantation dose is 5e14~3e15cm -2 .

8. The method for preparing a fast recovery diode according to claim 4, characterized in that: In the electron irradiation process, the electron irradiation dose is selected to be 10 to 90 KGY.

9. A system for preparing a fast recovery diode, characterized in that: Includes the following modules: Thinning module: N-type semiconductor substrate, Taiko thinning to target thickness; A primary lithography module, used for lithography and ion implantation on the front side of the wafer; The secondary photolithography module is used to flip the wafer and perform photolithography and P-type ion implantation on the back of the wafer again; Annealing module, used to anneal the wafer and activate the ions implanted on the front and back sides; An etching and deposition module is used to sequentially perform etching and deposition processes on the front side of the wafer; Ion implantation module, used for ion implantation on the back of the wafer to form a high-concentration N-type area and back metal; The electron irradiation module is used to perform electron irradiation process on the wafer and perform annealing.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 4 to 8 is implemented.

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